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// megafunction wizard: %ALTGX%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: alt4gxb 

// ============================================================

// File Name: altera_tse_alt4gxb_gige.v

// Megafunction Name(s):

//                      alt4gxb

//

// Simulation Library Files(s):

//                      stratixiv_hssi

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 12.0 Internal Build 147 03/05/2012 PN Full Version

// ************************************************************

//Copyright (C) 1991-2012 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic 

//functions, and any output files from any of the foregoing 

//(including device programming or simulation files), and any 

//associated documentation or information are expressly subject 

//to the terms and conditions of the Altera Program License 

//Subscription Agreement, Altera MegaCore Function License 

//Agreement, or other applicable license agreement, including, 

//without limitation, that your use is for the sole purpose of 

//programming logic devices manufactured by Altera and sold by 

//Altera or its authorized distributors.  Please refer to the 

//applicable agreement for further details.

//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset

//VERSION_BEGIN 12.0 cbx_alt4gxb 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_tgx 2012:03:05:21:09:17:PN  VERSION_END

// synthesis VERILOG_INPUT_VERSION VERILOG_2001

// altera message_off 10463

//synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1 

//synopsys translate_off

`timescale 1 ps / 1 ps

//synopsys translate_on

(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=c104"} *)

module  altera_tse_alt4gxb_gige_alt4gxb_lnca

        (

        cal_blk_clk,

        fixedclk,

        fixedclk_fast,

        gxb_powerdown,

        pll_inclk,

        pll_locked,

        pll_powerdown,

        reconfig_clk,

        reconfig_fromgxb,

        reconfig_togxb,

        rx_analogreset,

        rx_clkout,

        rx_cruclk,

        rx_ctrldetect,

        rx_datain,

        rx_dataout,

        rx_digitalreset,

        rx_disperr,

        rx_errdetect,

        rx_freqlocked,

        rx_patterndetect,

        rx_recovclkout,

        rx_rlv,

        rx_rmfifodatadeleted,

        rx_rmfifodatainserted,

        rx_runningdisp,

        rx_seriallpbken,

        rx_syncstatus,

        tx_clkout,

        tx_ctrlenable,

        tx_datain,

        tx_dataout,

        tx_digitalreset) /* synthesis synthesis_clearbox=2 */;

        input   cal_blk_clk;

        input   fixedclk;

        input   [5:0]  fixedclk_fast;

        input   [0:0]  gxb_powerdown;

        input   pll_inclk;

        output   [0:0]  pll_locked;

        input   [0:0]  pll_powerdown;

        input   reconfig_clk;

        output   [16:0]  reconfig_fromgxb;

        input   [3:0]  reconfig_togxb;

        input   [0:0]  rx_analogreset;

        output   [0:0]  rx_clkout;

        input   [0:0]  rx_cruclk;

        output   [0:0]  rx_ctrldetect;

        input   [0:0]  rx_datain;

        output   [7:0]  rx_dataout;

        input   [0:0]  rx_digitalreset;

        output   [0:0]  rx_disperr;

        output   [0:0]  rx_errdetect;

        output   [0:0]  rx_freqlocked;

        output   [0:0]  rx_patterndetect;

        output   [0:0]  rx_recovclkout;

        output   [0:0]  rx_rlv;

        output   [0:0]  rx_rmfifodatadeleted;

        output   [0:0]  rx_rmfifodatainserted;

        output   [0:0]  rx_runningdisp;

        input   [0:0]  rx_seriallpbken;

        output   [0:0]  rx_syncstatus;

        output   [0:0]  tx_clkout;

        input   [0:0]  tx_ctrlenable;

        input   [7:0]  tx_datain;

        output   [0:0]  tx_dataout;

        input   [0:0]  tx_digitalreset;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_off

`endif

        tri0   cal_blk_clk;

        tri0   fixedclk;

        tri1   [5:0]  fixedclk_fast;

        tri0   [0:0]  gxb_powerdown;

        tri0   pll_inclk;

        tri0   [0:0]  pll_powerdown;

        tri0   reconfig_clk;

        tri0   [0:0]  rx_analogreset;

        tri0   [0:0]  rx_cruclk;

        tri0   [0:0]  rx_digitalreset;

        tri0   [0:0]  rx_seriallpbken;

        tri0   [0:0]  tx_ctrlenable;

        tri0   [7:0]  tx_datain;

        tri0   [0:0]  tx_digitalreset;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_on

`endif

        parameter       starting_channel_number = 0;

        reg     fixedclk_div0quad0c;

        wire    wire_fixedclk_div0quad0c_clk;

        reg     fixedclk_div1quad0c;

        wire    wire_fixedclk_div1quad0c_clk;

        reg     fixedclk_div2quad0c;

        wire    wire_fixedclk_div2quad0c_clk;

        reg     fixedclk_div3quad0c;

        wire    wire_fixedclk_div3quad0c_clk;

        reg     fixedclk_div4quad0c;

        wire    wire_fixedclk_div4quad0c_clk;

        reg     fixedclk_div5quad0c;

        wire    wire_fixedclk_div5quad0c_clk;

        reg     [1:0]    reconfig_togxb_busy_reg;

        wire  wire_cal_blk0_nonusertocmu;

        wire  [1:0]   wire_ch_clk_div0_analogfastrefclkout;

        wire  [1:0]   wire_ch_clk_div0_analogrefclkout;

        wire  wire_ch_clk_div0_analogrefclkpulse;

        wire  [99:0]   wire_ch_clk_div0_dprioout;

        wire  [599:0]   wire_cent_unit0_cmudividerdprioout;

        wire  [1799:0]   wire_cent_unit0_cmuplldprioout;

        wire  wire_cent_unit0_dpriodisableout;

        wire  wire_cent_unit0_dprioout;

        wire  [1:0]   wire_cent_unit0_pllpowerdn;

        wire  [1:0]   wire_cent_unit0_pllresetout;

        wire  wire_cent_unit0_quadresetout;

        wire  [5:0]   wire_cent_unit0_rxanalogresetout;

        wire  [5:0]   wire_cent_unit0_rxcrupowerdown;

        wire  [5:0]   wire_cent_unit0_rxcruresetout;

        wire  [3:0]   wire_cent_unit0_rxdigitalresetout;

        wire  [5:0]   wire_cent_unit0_rxibpowerdown;

        wire  [1599:0]   wire_cent_unit0_rxpcsdprioout;

        wire  [1799:0]   wire_cent_unit0_rxpmadprioout;

        wire  [5:0]   wire_cent_unit0_txanalogresetout;

        wire  [3:0]   wire_cent_unit0_txctrlout;

        wire  [31:0]   wire_cent_unit0_txdataout;

        wire  [5:0]   wire_cent_unit0_txdetectrxpowerdown;

        wire  [3:0]   wire_cent_unit0_txdigitalresetout;

        wire  [5:0]   wire_cent_unit0_txobpowerdown;

        wire  [599:0]   wire_cent_unit0_txpcsdprioout;

        wire  [1799:0]   wire_cent_unit0_txpmadprioout;

        wire  [3:0]   wire_rx_cdr_pll0_clk;

        wire  [1:0]   wire_rx_cdr_pll0_dataout;

        wire  [299:0]   wire_rx_cdr_pll0_dprioout;

        wire  wire_rx_cdr_pll0_freqlocked;

        wire  wire_rx_cdr_pll0_locked;

        wire  wire_rx_cdr_pll0_pfdrefclkout;

        wire  [3:0]   wire_tx_pll0_clk;

        wire  [299:0]   wire_tx_pll0_dprioout;

        wire  wire_tx_pll0_locked;

        wire  wire_receive_pcs0_cdrctrllocktorefclkout;

        wire  wire_receive_pcs0_clkout;

        wire  [3:0]   wire_receive_pcs0_ctrldetect;

        wire  [39:0]   wire_receive_pcs0_dataout;

        wire  [3:0]   wire_receive_pcs0_disperr;

        wire  [399:0]   wire_receive_pcs0_dprioout;

        wire  [3:0]   wire_receive_pcs0_errdetect;

        wire  [3:0]   wire_receive_pcs0_patterndetect;

        wire  wire_receive_pcs0_rlv;

        wire  [3:0]   wire_receive_pcs0_rmfifodatadeleted;

        wire  [3:0]   wire_receive_pcs0_rmfifodatainserted;

        wire  [3:0]   wire_receive_pcs0_runningdisp;

        wire  [3:0]   wire_receive_pcs0_syncstatus;

        wire  [7:0]   wire_receive_pma0_analogtestbus;

        wire  wire_receive_pma0_clockout;

        wire  wire_receive_pma0_dataout;

        wire  [299:0]   wire_receive_pma0_dprioout;

        wire  wire_receive_pma0_locktorefout;

        wire  [63:0]   wire_receive_pma0_recoverdataout;

        wire  wire_receive_pma0_signaldetect;

        wire  wire_transmit_pcs0_clkout;

        wire  [19:0]   wire_transmit_pcs0_dataout;

        wire  [149:0]   wire_transmit_pcs0_dprioout;

        wire  wire_transmit_pcs0_forceelecidleout;

        wire  wire_transmit_pcs0_txdetectrx;

        wire  wire_transmit_pma0_clockout;

        wire  wire_transmit_pma0_dataout;

        wire  [299:0]   wire_transmit_pma0_dprioout;

        wire  wire_transmit_pma0_seriallpbkout;

        wire  [1:0]  analogfastrefclkout;

        wire  [1:0]  analogrefclkout;

        wire  [0:0]  analogrefclkpulse;

        wire cal_blk_powerdown;

        wire  [599:0]  cent_unit_cmudividerdprioout;

        wire  [1799:0]  cent_unit_cmuplldprioout;

        wire  [1:0]  cent_unit_pllpowerdn;

        wire  [1:0]  cent_unit_pllresetout;

        wire  [0:0]  cent_unit_quadresetout;

        wire  [5:0]  cent_unit_rxcrupowerdn;

        wire  [5:0]  cent_unit_rxibpowerdn;

        wire  [1599:0]  cent_unit_rxpcsdprioin;

        wire  [1599:0]  cent_unit_rxpcsdprioout;

        wire  [1799:0]  cent_unit_rxpmadprioin;

        wire  [1799:0]  cent_unit_rxpmadprioout;

        wire  [1199:0]  cent_unit_tx_dprioin;

        wire  [31:0]  cent_unit_tx_xgmdataout;

        wire  [3:0]  cent_unit_txctrlout;

        wire  [5:0]  cent_unit_txdetectrxpowerdn;

        wire  [599:0]  cent_unit_txdprioout;

        wire  [5:0]  cent_unit_txobpowerdn;

        wire  [1799:0]  cent_unit_txpmadprioin;

        wire  [1799:0]  cent_unit_txpmadprioout;

        wire  [599:0]  clk_div_cmudividerdprioin;

        wire  [5:0]  fixedclk_div_in;

        wire  [0:0]  fixedclk_enable;

        wire  [5:0]  fixedclk_in;

        wire  [0:0]  fixedclk_sel;

        wire  [5:0]  fixedclk_to_cmu;

        wire  [0:0]  nonusertocmu_out;

        wire  [9:0]  pll0_clkin;

        wire  [299:0]  pll0_dprioin;

        wire  [299:0]  pll0_dprioout;

        wire  [3:0]  pll0_out;

        wire  [1:0]  pll_ch_dataout_wire;

        wire  [299:0]  pll_ch_dprioout;

        wire  [1799:0]  pll_cmuplldprioout;

        wire  [0:0]  pll_inclk_wire;

        wire  [0:0]  pll_locked_out;

        wire  [1:0]  pllpowerdn_in;

        wire  [1:0]  pllreset_in;

        wire  [0:0]  reconfig_togxb_busy;

        wire  [0:0]  reconfig_togxb_disable;

        wire  [0:0]  reconfig_togxb_in;

        wire  [0:0]  reconfig_togxb_load;

        wire  [5:0]  rx_analogreset_in;

        wire  [5:0]  rx_analogreset_out;

        wire  [0:0]  rx_clkout_wire;

        wire  [0:0]  rx_coreclk_in;

        wire  [9:0]  rx_cruclk_in;

        wire  [3:0]  rx_deserclock_in;

        wire  [3:0]  rx_digitalreset_in;

        wire  [3:0]  rx_digitalreset_out;

        wire [0:0]  rx_enapatternalign;

        wire  [0:0]  rx_freqlocked_wire;

        wire [0:0]  rx_locktodata;

        wire  [0:0]  rx_locktodata_wire;

        wire [0:0]  rx_locktorefclk;

        wire  [0:0]  rx_locktorefclk_wire;

        wire  [7:0]  rx_out_wire;

        wire  [1599:0]  rx_pcsdprioin_wire;

        wire  [1599:0]  rx_pcsdprioout;

        wire [0:0]  rx_phfifordenable;

        wire [0:0]  rx_phfiforeset;

        wire [0:0]  rx_phfifowrdisable;

        wire  [0:0]  rx_pldcruclk_in;

        wire  [3:0]  rx_pll_clkout;

        wire  [0:0]  rx_pll_pfdrefclkout_wire;

        wire  [0:0]  rx_plllocked_wire;

        wire  [16:0]  rx_pma_analogtestbus;

        wire  [0:0]  rx_pma_clockout;

        wire  [0:0]  rx_pma_dataout;

        wire  [0:0]  rx_pma_locktorefout;

        wire  [19:0]  rx_pma_recoverdataout_wire;

        wire  [1799:0]  rx_pmadprioin_wire;

        wire  [1799:0]  rx_pmadprioout;

        wire [0:0]  rx_powerdown;

        wire  [5:0]  rx_powerdown_in;

        wire [0:0]  rx_prbscidenable;

        wire [0:0]  rx_rmfiforeset;

        wire  [5:0]  rx_rxcruresetout;

        wire  [1799:0]  rxpll_dprioin;

        wire  [5:0]  tx_analogreset_out;

        wire  [0:0]  tx_clkout_int_wire;

        wire  [0:0]  tx_core_clkout_wire;

        wire  [0:0]  tx_coreclk_in;

        wire  [7:0]  tx_datain_wire;

        wire  [19:0]  tx_dataout_pcs_to_pma;

        wire  [3:0]  tx_digitalreset_in;

        wire  [3:0]  tx_digitalreset_out;

        wire  [1199:0]  tx_dprioin_wire;

        wire  [0:0]  tx_forcedisp_wire;

        wire [0:0]  tx_invpolarity;

        wire  [0:0]  tx_localrefclk;

        wire [0:0]  tx_phfiforeset;

        wire  [1799:0]  tx_pmadprioin_wire;

        wire  [1799:0]  tx_pmadprioout;

        wire  [0:0]  tx_serialloopbackout;

        wire  [599:0]  tx_txdprioout;

        wire  [0:0]  txdetectrxout;

        wire  [0:0]  w_cent_unit_dpriodisableout1w;

        // synopsys translate_off

        initial

                fixedclk_div0quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div0quad0c_clk)

                  fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);

        assign

                wire_fixedclk_div0quad0c_clk = fixedclk_in[0];

        // synopsys translate_off

        initial

                fixedclk_div1quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div1quad0c_clk)

                  fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);

        assign

                wire_fixedclk_div1quad0c_clk = fixedclk_in[1];

        // synopsys translate_off

        initial

                fixedclk_div2quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div2quad0c_clk)

                  fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);

        assign

                wire_fixedclk_div2quad0c_clk = fixedclk_in[2];

        // synopsys translate_off

        initial

                fixedclk_div3quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div3quad0c_clk)

                  fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);

        assign

                wire_fixedclk_div3quad0c_clk = fixedclk_in[3];

        // synopsys translate_off

        initial

                fixedclk_div4quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div4quad0c_clk)

                  fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);

        assign

                wire_fixedclk_div4quad0c_clk = fixedclk_in[4];

        // synopsys translate_off

        initial

                fixedclk_div5quad0c = 0;

        // synopsys translate_on

        always @ ( posedge wire_fixedclk_div5quad0c_clk)

                  fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);

        assign

                wire_fixedclk_div5quad0c_clk = fixedclk_in[5];

        // synopsys translate_off

        initial

                reconfig_togxb_busy_reg = 0;

        // synopsys translate_on

        always @ ( negedge fixedclk)

                  reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};

        stratixiv_hssi_calibration_block   cal_blk0

        (

        .calibrationstatus(),

        .clk(cal_blk_clk),

        .enabletestbus(1'b1),

        .nonusertocmu(wire_cal_blk0_nonusertocmu),

        .powerdn(cal_blk_powerdown)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .testctrl(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        stratixiv_hssi_clock_divider   ch_clk_div0

        (

        .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),

        .analogfastrefclkoutshifted(),

        .analogrefclkout(wire_ch_clk_div0_analogrefclkout),

        .analogrefclkoutshifted(),

        .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),

        .analogrefclkpulseshifted(),

        .clk0in(pll0_out[3:0]),

        .coreclkout(),

        .dpriodisable(w_cent_unit_dpriodisableout1w[0]),

        .dprioin(cent_unit_cmudividerdprioout[99:0]),

        .dprioout(wire_ch_clk_div0_dprioout),

        .quadreset(cent_unit_quadresetout[0]),

        .rateswitchbaseclock(),

        .rateswitchdone(),

        .rateswitchout(),

        .refclkout()

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .clk1in({4{1'b0}}),

        .powerdn(1'b0),

        .rateswitch(1'b0),

        .rateswitchbaseclkin({2{1'b0}}),

        .rateswitchdonein({2{1'b0}}),

        .refclkdig(1'b0),

        .refclkin({2{1'b0}}),

        .vcobypassin(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        defparam

                ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),

                ch_clk_div0.divide_by = 5,

                ch_clk_div0.divider_type = "CHANNEL_REGULAR",

                ch_clk_div0.effective_data_rate = "1250.0 Mbps",

                ch_clk_div0.enable_dynamic_divider = "false",

                ch_clk_div0.enable_refclk_out = "false",

                ch_clk_div0.inclk_select = 0,

                ch_clk_div0.logical_channel_address = (starting_channel_number + 0),

                ch_clk_div0.pre_divide_by = 1,

                ch_clk_div0.select_local_rate_switch_done = "false",

                ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,

                ch_clk_div0.sim_analogrefclkout_phase_shift = 0,

                ch_clk_div0.sim_coreclkout_phase_shift = 0,

                ch_clk_div0.sim_refclkout_phase_shift = 0,

                ch_clk_div0.use_coreclk_out_post_divider = "false",

                ch_clk_div0.use_refclk_post_divider = "false",

                ch_clk_div0.use_vco_bypass = "false",

                ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";

        stratixiv_hssi_cmu   cent_unit0

        (

        .adet({4{1'b0}}),

        .alignstatus(),

        .autospdx4configsel(),

        .autospdx4rateswitchout(),

        .autospdx4spdchg(),

        .clkdivpowerdn(),

        .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),

        .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),

        .cmuplldprioin(pll_cmuplldprioout[1799:0]),

        .cmuplldprioout(wire_cent_unit0_cmuplldprioout),

        .digitaltestout(),

        .dpclk(reconfig_clk),

        .dpriodisable(reconfig_togxb_disable),

        .dpriodisableout(wire_cent_unit0_dpriodisableout),

        .dprioin(reconfig_togxb_in),

        .dprioload(reconfig_togxb_load),

        .dpriooe(),

        .dprioout(wire_cent_unit0_dprioout),

        .enabledeskew(),

        .extra10gout(),

        .fiforesetrd(),

        .fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),

        .lccmutestbus(),

        .nonuserfromcal(nonusertocmu_out[0]),

        .phfifiox4ptrsreset(),

        .pllpowerdn(wire_cent_unit0_pllpowerdn),

        .pllresetout(wire_cent_unit0_pllresetout),

        .quadreset(gxb_powerdown[0]),

        .quadresetout(wire_cent_unit0_quadresetout),

        .rdalign({4{1'b0}}),

        .rdenablesync(1'b0),

        .recovclk(1'b0),

        .refclkdividerdprioin({2{1'b0}}),

        .refclkdividerdprioout(),

        .rxadcepowerdown(),

        .rxadceresetout(),

        .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),

        .rxanalogresetout(wire_cent_unit0_rxanalogresetout),

        .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),

        .rxcruresetout(wire_cent_unit0_rxcruresetout),

        .rxctrl({4{1'b0}}),

        .rxctrlout(),

        .rxdatain({32{1'b0}}),

        .rxdataout(),

        .rxdatavalid({4{1'b0}}),

        .rxdigitalreset({rx_digitalreset_in[3:0]}),

        .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),

        .rxibpowerdown(wire_cent_unit0_rxibpowerdown),

        .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),

        .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),

        .rxphfifox4byteselout(),

        .rxphfifox4rdenableout(),

        .rxphfifox4wrclkout(),

        .rxphfifox4wrenableout(),

        .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),

        .rxpmadprioout(wire_cent_unit0_rxpmadprioout),

        .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),

        .rxrunningdisp({4{1'b0}}),

        .scanout(),

        .syncstatus({4{1'b0}}),

        .testout(),

        .txanalogresetout(wire_cent_unit0_txanalogresetout),

        .txctrl({4{1'b0}}),

        .txctrlout(wire_cent_unit0_txctrlout),

        .txdatain({32{1'b0}}),

        .txdataout(wire_cent_unit0_txdataout),

        .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),

        .txdigitalreset({tx_digitalreset_in[3:0]}),

        .txdigitalresetout(wire_cent_unit0_txdigitalresetout),

        .txdividerpowerdown(),

        .txobpowerdown(wire_cent_unit0_txobpowerdown),

        .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),

        .txpcsdprioout(wire_cent_unit0_txpcsdprioout),

        .txphfifox4byteselout(),

        .txphfifox4rdclkout(),

        .txphfifox4rdenableout(),

        .txphfifox4wrenableout(),

        .txpllreset({{1{1'b0}}, pll_powerdown[0]}),

        .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),

        .txpmadprioout(wire_cent_unit0_txpmadprioout)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .extra10gin({7{1'b0}}),

        .lccmurtestbussel({3{1'b0}}),

        .pmacramtest(1'b0),

        .rateswitch(1'b0),

        .rateswitchdonein(1'b0),

        .rxclk(1'b0),

        .rxcoreclk(1'b0),

        .rxphfifordenable(1'b1),

        .rxphfiforeset(1'b0),

        .rxphfifowrdisable(1'b0),

        .scanclk(1'b0),

        .scanin({23{1'b0}}),

        .scanmode(1'b0),

        .scanshift(1'b0),

        .testin({10000{1'b0}}),

        .txclk(1'b0),

        .txcoreclk(1'b0),

        .txphfiforddisable(1'b0),

        .txphfiforeset(1'b0),

        .txphfifowrenable(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        defparam

                cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,

                cent_unit0.auto_spd_phystatus_notify_count = 0,

                cent_unit0.bonded_quad_mode = "none",

                cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),

                cent_unit0.in_xaui_mode = "false",

                cent_unit0.offset_all_errors_align = "false",

                cent_unit0.pipe_auto_speed_nego_enable = "false",

                cent_unit0.pipe_freq_scale_mode = "Frequency",

                cent_unit0.pma_done_count = 249950,

                cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),

                cent_unit0.rx0_auto_spd_self_switch_enable = "false",

                cent_unit0.rx0_channel_bonding = "none",

                cent_unit0.rx0_clk1_mux_select = "recovered clock",

                cent_unit0.rx0_clk2_mux_select = "local reference clock",

                cent_unit0.rx0_ph_fifo_reg_mode = "false",

                cent_unit0.rx0_rd_clk_mux_select = "core clock",

                cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",

                cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",

                cent_unit0.rx0_use_double_data_mode = "false",

                cent_unit0.tx0_auto_spd_self_switch_enable = "false",

                cent_unit0.tx0_channel_bonding = "none",

                cent_unit0.tx0_ph_fifo_reg_mode = "false",

                cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",

                cent_unit0.tx0_use_double_data_mode = "false",

                cent_unit0.tx0_wr_clk_mux_select = "core_clk",

                cent_unit0.use_deskew_fifo = "false",