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// megafunction wizard: %ALTGX%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: alt_c3gxb 

// ============================================================

// File Name: altera_tse_altgx_civgx_gige_wo_rmfifo.v

// Megafunction Name(s):

//                      alt_c3gxb

//

// Simulation Library Files(s):

//                      altera_mf;cycloneiv_hssi

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 12.0 Internal Build 147 03/05/2012 PN Full Version

// ************************************************************

//Copyright (C) 1991-2012 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic 

//functions, and any output files from any of the foregoing 

//(including device programming or simulation files), and any 

//associated documentation or information are expressly subject 

//to the terms and conditions of the Altera Program License 

//Subscription Agreement, Altera MegaCore Function License 

//Agreement, or other applicable license agreement, including, 

//without limitation, that your use is for the sole purpose of 

//programming logic devices manufactured by Altera and sold by 

//Altera or its authorized distributors.  Please refer to the 

//applicable agreement for further details.

//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="1111100" rx_align_pattern_length=7 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="none" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altera_tse_altgx_civgx_gige_wo_rmfifo" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"

//VERSION_BEGIN 12.0 cbx_alt_c3gxb 2012:03:05:21:09:17:PN cbx_altclkbuf 2012:03:05:21:09:17:PN cbx_altiobuf_bidir 2012:03:05:21:09:17:PN cbx_altiobuf_in 2012:03:05:21:09:17:PN cbx_altiobuf_out 2012:03:05:21:09:17:PN cbx_altpll 2012:03:05:21:09:17:PN cbx_cycloneii 2012:03:05:21:09:17:PN cbx_lpm_add_sub 2012:03:05:21:09:17:PN cbx_lpm_compare 2012:03:05:21:09:17:PN cbx_lpm_counter 2012:03:05:21:09:17:PN cbx_lpm_decode 2012:03:05:21:09:17:PN cbx_lpm_mux 2012:03:05:21:09:17:PN cbx_mgl 2012:03:05:22:13:55:PN cbx_stingray 2012:03:05:21:09:16:PN cbx_stratix 2012:03:05:21:09:18:PN cbx_stratixii 2012:03:05:21:09:18:PN cbx_stratixiii 2012:03:05:21:09:18:PN cbx_stratixv 2012:03:05:21:09:18:PN cbx_util_mgl 2012:03:05:21:09:17:PN  VERSION_END

// synthesis VERILOG_INPUT_VERSION VERILOG_2001

// altera message_off 10463

//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3 

//synopsys translate_off

`timescale 1 ps / 1 ps

//synopsys translate_on

(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)

module  altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_ut08

        (

        cal_blk_clk,

        fixedclk,

        fixedclk_fast,

        gxb_powerdown,

        pll_areset,

        pll_inclk,

        pll_locked,

        reconfig_clk,

        reconfig_fromgxb,

        reconfig_togxb,

        rx_analogreset,

        rx_clkout,

        rx_ctrldetect,

        rx_datain,

        rx_dataout,

        rx_digitalreset,

        rx_disperr,

        rx_errdetect,

        rx_freqlocked,

        rx_patterndetect,

        rx_recovclkout,

        rx_rlv,

        rx_rmfifodatadeleted,

        rx_rmfifodatainserted,

        rx_runningdisp,

        rx_syncstatus,

        tx_clkout,

        tx_ctrlenable,

        tx_datain,

        tx_dataout,

        tx_digitalreset) /* synthesis synthesis_clearbox=2 */;

        input   cal_blk_clk;

        input   fixedclk;

        input   [3:0]  fixedclk_fast;

        input   [0:0]  gxb_powerdown;

        input   [0:0]  pll_areset;

        input   [0:0]  pll_inclk;

        output   [0:0]  pll_locked;

        input   reconfig_clk;

        output   [4:0]  reconfig_fromgxb;

        input   [3:0]  reconfig_togxb;

        input   [0:0]  rx_analogreset;

        output   [0:0]  rx_clkout;

        output   [0:0]  rx_ctrldetect;

        input   [0:0]  rx_datain;

        output   [7:0]  rx_dataout;

        input   [0:0]  rx_digitalreset;

        output   [0:0]  rx_disperr;

        output   [0:0]  rx_errdetect;

        output   [0:0]  rx_freqlocked;

        output   [0:0]  rx_patterndetect;

        output   [0:0]  rx_recovclkout;

        output   [0:0]  rx_rlv;

        output   [0:0]  rx_rmfifodatadeleted;

        output   [0:0]  rx_rmfifodatainserted;

        output   [0:0]  rx_runningdisp;

        output   [0:0]  rx_syncstatus;

        output   [0:0]  tx_clkout;

        input   [0:0]  tx_ctrlenable;

        input   [7:0]  tx_datain;

        output   [0:0]  tx_dataout;

        input   [0:0]  tx_digitalreset;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_off

`endif

        tri0   cal_blk_clk;

        tri0   fixedclk;

        tri1   [3:0]  fixedclk_fast;

        tri0   [0:0]  gxb_powerdown;

        tri0   [0:0]  pll_areset;

        tri0   reconfig_clk;

        tri0   [0:0]  rx_analogreset;

        tri0   [0:0]  rx_digitalreset;

        tri0   [0:0]  tx_ctrlenable;

        tri0   [7:0]  tx_datain;

        tri0   [0:0]  tx_digitalreset;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_on

`endif

        parameter       starting_channel_number = 0;

        wire  [5:0]   wire_pll0_clk;

        wire  wire_pll0_fref;

        wire  wire_pll0_icdrclk;

        wire  wire_pll0_locked;

        wire  wire_cal_blk0_nonusertocmu;

        wire  wire_cent_unit0_dpriodisableout;

        wire  wire_cent_unit0_dprioout;

        wire  wire_cent_unit0_quadresetout;

        wire  [3:0]   wire_cent_unit0_rxanalogresetout;

        wire  [3:0]   wire_cent_unit0_rxcrupowerdown;

        wire  [3:0]   wire_cent_unit0_rxdigitalresetout;

        wire  [3:0]   wire_cent_unit0_rxibpowerdown;

        wire  [1599:0]   wire_cent_unit0_rxpcsdprioout;

        wire  [1199:0]   wire_cent_unit0_rxpmadprioout;

        wire  [3:0]   wire_cent_unit0_txanalogresetout;

        wire  [3:0]   wire_cent_unit0_txdetectrxpowerdown;

        wire  [3:0]   wire_cent_unit0_txdigitalresetout;

        wire  [3:0]   wire_cent_unit0_txdividerpowerdown;

        wire  [3:0]   wire_cent_unit0_txobpowerdown;

        wire  [599:0]   wire_cent_unit0_txpcsdprioout;

        wire  [1199:0]   wire_cent_unit0_txpmadprioout;

        wire  wire_receive_pcs0_cdrctrllocktorefclkout;

        wire  wire_receive_pcs0_clkout;

        wire  [1:0]   wire_receive_pcs0_ctrldetect;

        wire  [19:0]   wire_receive_pcs0_dataout;

        wire  [1:0]   wire_receive_pcs0_disperr;

        wire  [399:0]   wire_receive_pcs0_dprioout;

        wire  [1:0]   wire_receive_pcs0_errdetect;

        wire  [1:0]   wire_receive_pcs0_patterndetect;

        wire  wire_receive_pcs0_rlv;

        wire  [1:0]   wire_receive_pcs0_rmfifodatadeleted;

        wire  [1:0]   wire_receive_pcs0_rmfifodatainserted;

        wire  [1:0]   wire_receive_pcs0_runningdisp;

        wire  [1:0]   wire_receive_pcs0_syncstatus;

        wire  [7:0]   wire_receive_pma0_analogtestbus;

        wire  wire_receive_pma0_clockout;

        wire  wire_receive_pma0_diagnosticlpbkout;

        wire  [299:0]   wire_receive_pma0_dprioout;

        wire  wire_receive_pma0_freqlocked;

        wire  wire_receive_pma0_locktorefout;

        wire  [9:0]   wire_receive_pma0_recoverdataout;

        wire  wire_receive_pma0_reverselpbkout;

        wire  wire_receive_pma0_signaldetect;

        wire  wire_transmit_pcs0_clkout;

        wire  [9:0]   wire_transmit_pcs0_dataout;

        wire  [149:0]   wire_transmit_pcs0_dprioout;

        wire  wire_transmit_pcs0_txdetectrx;

        wire  wire_transmit_pma0_clockout;

        wire  wire_transmit_pma0_dataout;

        wire  [299:0]   wire_transmit_pma0_dprioout;

        wire  wire_transmit_pma0_seriallpbkout;

        reg     [0:0]     fixedclk_div;

        reg     [1:0]    reconfig_togxb_busy_reg;

        wire cal_blk_powerdown;

        wire  [0:0]  cent_unit_quadresetout;

        wire  [3:0]  cent_unit_rxcrupowerdn;

        wire  [3:0]  cent_unit_rxibpowerdn;

        wire  [1599:0]  cent_unit_rxpcsdprioin;

        wire  [1599:0]  cent_unit_rxpcsdprioout;

        wire  [1199:0]  cent_unit_rxpmadprioin;

        wire  [1199:0]  cent_unit_rxpmadprioout;

        wire  [599:0]  cent_unit_tx_dprioin;

        wire  [3:0]  cent_unit_txdetectrxpowerdn;

        wire  [3:0]  cent_unit_txdividerpowerdown;

        wire  [599:0]  cent_unit_txdprioout;

        wire  [3:0]  cent_unit_txobpowerdn;

        wire  [1199:0]  cent_unit_txpmadprioin;

        wire  [1199:0]  cent_unit_txpmadprioout;

        wire  [0:0]  fixedclk_div_in;

        wire  [0:0]  fixedclk_enable;

        wire  [0:0]  fixedclk_sel;

        wire  [3:0]  fixedclk_to_cmu;

        wire  [0:0]  nonusertocmu_out;

        wire [0:0]  pll_powerdown;

        wire  [0:0]  reconfig_togxb_busy;

        wire  [0:0]  reconfig_togxb_disable;

        wire  [0:0]  reconfig_togxb_in;

        wire  [0:0]  reconfig_togxb_load;

        wire  [3:0]  rx_analogreset_in;

        wire  [3:0]  rx_analogreset_out;

        wire  [0:0]  rx_clkout_wire;

        wire  [0:0]  rx_coreclk_in;

        wire  [0:0]  rx_deserclock_in;

        wire  [3:0]  rx_digitalreset_in;

        wire  [3:0]  rx_digitalreset_out;

        wire [0:0]  rx_enapatternalign;

        wire [0:0]  rx_locktodata;

        wire [0:0]  rx_locktorefclk;

        wire  [0:0]  rx_locktorefclk_wire;

        wire  [7:0]  rx_out_wire;

        wire  [1599:0]  rx_pcsdprioin_wire;

        wire  [1599:0]  rx_pcsdprioout;

        wire [0:0]  rx_phfifordenable;

        wire [0:0]  rx_phfiforeset;

        wire [0:0]  rx_phfifowrdisable;

        wire  [0:0]  rx_pll_pfdrefclkout_wire;

        wire  [4:0]  rx_pma_analogtestbus;

        wire  [0:0]  rx_pma_clockout;

        wire  [9:0]  rx_pma_recoverdataout_wire;

        wire  [1199:0]  rx_pmadprioin_wire;

        wire  [1199:0]  rx_pmadprioout;

        wire [0:0]  rx_powerdown;

        wire  [3:0]  rx_powerdown_in;

        wire [0:0]  rx_prbscidenable;

        wire  [0:0]  rx_reverselpbkout;

        wire  [0:0]  rx_signaldetect_wire;

        wire  [3:0]  tx_analogreset_out;

        wire  [0:0]  tx_clkout_int_wire;

        wire  [0:0]  tx_core_clkout_wire;

        wire  [0:0]  tx_coreclk_in;

        wire  [7:0]  tx_datain_wire;

        wire  [9:0]  tx_dataout_pcs_to_pma;

        wire  [0:0]  tx_diagnosticlpbkin;

        wire  [3:0]  tx_digitalreset_in;

        wire  [3:0]  tx_digitalreset_out;

        wire  [599:0]  tx_dprioin_wire;

        wire  [0:0]  tx_forcedisp_wire;

        wire [0:0]  tx_invpolarity;

        wire  [0:0]  tx_localrefclk;

        wire [0:0]  tx_phfiforeset;

        wire  [0:0]  tx_pma_fastrefclk0in;

        wire  [0:0]  tx_pma_refclk0in;

        wire  [0:0]  tx_pma_refclk0inpulse;

        wire  [1199:0]  tx_pmadprioin_wire;

        wire  [1199:0]  tx_pmadprioout;

        wire  [0:0]  tx_serialloopbackout;

        wire  [599:0]  tx_txdprioout;

        wire  [0:0]  txdataout;

        wire  [0:0]  txdetectrxout;

        wire  [0:0]  w_cent_unit_dpriodisableout1w;

        altpll   pll0

        (

        .activeclock(),

        .areset((pll_areset[0] | pll_powerdown[0])),

        .clk(wire_pll0_clk),

        .clkbad(),

        .clkloss(),

        .enable0(),

        .enable1(),

        .extclk(),

        .fbout(),

        .fref(wire_pll0_fref),

        .icdrclk(wire_pll0_icdrclk),

        .inclk({{1{1'b0}}, pll_inclk[0]}),

        .locked(wire_pll0_locked),

        .phasedone(),

        .scandataout(),

        .scandone(),

        .sclkout0(),

        .sclkout1(),

        .vcooverrange(),

        .vcounderrange()

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .clkena({6{1'b1}}),

        .clkswitch(1'b0),

        .configupdate(1'b0),

        .extclkena({4{1'b1}}),

        .fbin(1'b1),

        .pfdena(1'b1),

        .phasecounterselect({4{1'b1}}),

        .phasestep(1'b1),

        .phaseupdown(1'b1),

        .pllena(1'b1),

        .scanaclr(1'b0),

        .scanclk(1'b0),

        .scanclkena(1'b1),

        .scandata(1'b0),

        .scanread(1'b0),

        .scanwrite(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        defparam

                pll0.bandwidth_type = "HIGH",

                pll0.clk0_divide_by = 1,

                pll0.clk0_multiply_by = 5,

                pll0.clk1_divide_by = 5,

                pll0.clk1_multiply_by = 5,

                pll0.clk2_divide_by = 5,

                pll0.clk2_duty_cycle = 20,

                pll0.clk2_multiply_by = 5,

                pll0.dpa_divide_by = 1,

                pll0.dpa_multiply_by = 5,

                pll0.inclk0_input_frequency = 8000,

                pll0.operation_mode = "no_compensation",

                pll0.intended_device_family = "Cyclone IV GX",

                pll0.lpm_type = "altpll";

        cycloneiv_hssi_calibration_block   cal_blk0

        (

        .calibrationstatus(),

        .clk(cal_blk_clk),

        .nonusertocmu(wire_cal_blk0_nonusertocmu),

        .powerdn(cal_blk_powerdown)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .testctrl(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        cycloneiv_hssi_cmu   cent_unit0

        (

        .adet({4{1'b0}}),

        .alignstatus(),

        .coreclkout(),

        .digitaltestout(),

        .dpclk(reconfig_clk),

        .dpriodisable(reconfig_togxb_disable),

        .dpriodisableout(wire_cent_unit0_dpriodisableout),

        .dprioin(reconfig_togxb_in),

        .dprioload(reconfig_togxb_load),

        .dpriooe(),

        .dprioout(wire_cent_unit0_dprioout),

        .enabledeskew(),

        .fiforesetrd(),

        .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),

        .nonuserfromcal(nonusertocmu_out[0]),

        .quadreset(gxb_powerdown[0]),

        .quadresetout(wire_cent_unit0_quadresetout),

        .rdalign({4{1'b0}}),

        .rdenablesync(1'b0),

        .recovclk(1'b0),

        .refclkout(),

        .rxanalogreset({rx_analogreset_in[3:0]}),

        .rxanalogresetout(wire_cent_unit0_rxanalogresetout),

        .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),

        .rxctrl({4{1'b0}}),

        .rxctrlout(),

        .rxdatain({32{1'b0}}),

        .rxdataout(),

        .rxdatavalid({4{1'b0}}),

        .rxdigitalreset({rx_digitalreset_in[3:0]}),

        .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),

        .rxibpowerdown(wire_cent_unit0_rxibpowerdown),

        .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),

        .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),

        .rxphfifox4byteselout(),

        .rxphfifox4rdenableout(),

        .rxphfifox4wrclkout(),

        .rxphfifox4wrenableout(),

        .rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),

        .rxpmadprioout(wire_cent_unit0_rxpmadprioout),

        .rxpowerdown({rx_powerdown_in[3:0]}),

        .rxrunningdisp({4{1'b0}}),

        .syncstatus({4{1'b0}}),

        .testout(),

        .txanalogresetout(wire_cent_unit0_txanalogresetout),

        .txctrl({4{1'b0}}),

        .txctrlout(),

        .txdatain({32{1'b0}}),

        .txdataout(),

        .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),

        .txdigitalreset({tx_digitalreset_in[3:0]}),

        .txdigitalresetout(wire_cent_unit0_txdigitalresetout),

        .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),

        .txobpowerdown(wire_cent_unit0_txobpowerdown),

        .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),

        .txpcsdprioout(wire_cent_unit0_txpcsdprioout),

        .txphfifox4byteselout(),

        .txphfifox4rdclkout(),

        .txphfifox4rdenableout(),

        .txphfifox4wrenableout(),

        .txpmadprioin({cent_unit_txpmadprioin[1199:0]}),

        .txpmadprioout(wire_cent_unit0_txpmadprioout)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .pmacramtest(1'b0),

        .refclkdig(1'b0),

        .rxcoreclk(1'b0),

        .rxphfifordenable(1'b1),

        .rxphfiforeset(1'b0),

        .rxphfifowrdisable(1'b0),

        .scanclk(1'b0),

        .scanmode(1'b0),

        .scanshift(1'b0),

        .testin({2000{1'b0}}),

        .txclk(1'b0),

        .txcoreclk(1'b0),

        .txphfiforddisable(1'b0),

        .txphfiforeset(1'b0),

        .txphfifowrenable(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        defparam

                cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,

                cent_unit0.auto_spd_phystatus_notify_count = 0,

                cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),

                cent_unit0.dprio_config_mode = 6'h01,

                cent_unit0.in_xaui_mode = "false",

                cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),

                cent_unit0.rx0_channel_bonding = "none",

                cent_unit0.rx0_clk1_mux_select = "recovered clock",

                cent_unit0.rx0_clk2_mux_select = "recovered clock",

                cent_unit0.rx0_ph_fifo_reg_mode = "false",

                cent_unit0.rx0_rd_clk_mux_select = "core clock",

                cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",

                cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",

                cent_unit0.rx0_use_double_data_mode = "false",

                cent_unit0.tx0_channel_bonding = "none",

                cent_unit0.tx0_rd_clk_mux_select = "central",

                cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",

                cent_unit0.tx0_use_double_data_mode = "false",

                cent_unit0.tx0_wr_clk_mux_select = "core_clk",

                cent_unit0.use_coreclk_out_post_divider = "false",

                cent_unit0.use_deskew_fifo = "false",

                cent_unit0.lpm_type = "cycloneiv_hssi_cmu";

        cycloneiv_hssi_rx_pcs   receive_pcs0

        (

        .a1a2size(1'b0),

        .a1a2sizeout(),

        .a1detect(),

        .a2detect(),

        .adetectdeskew(),

        .alignstatus(1'b0),

        .alignstatussync(1'b0),

        .alignstatussyncout(),

        .bistdone(),

        .bisterr(),

        .bitslipboundaryselectout(),

        .byteorderalignstatus(),

        .cdrctrlearlyeios(),

        .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),

        .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),

        .clkout(wire_receive_pcs0_clkout),

        .coreclk(rx_coreclk_in[0]),

        .coreclkout(),

        .ctrldetect(wire_receive_pcs0_ctrldetect),

        .datain(rx_pma_recoverdataout_wire[9:0]),

        .dataout(wire_receive_pcs0_dataout),

        .dataoutfull(),

        .digitalreset(rx_digitalreset_out[0]),

        .disperr(wire_receive_pcs0_disperr),

        .dpriodisable(w_cent_unit_dpriodisableout1w[0]),

        .dprioin(rx_pcsdprioin_wire[399:0]),

        .dprioout(wire_receive_pcs0_dprioout),

        .enabledeskew(1'b0),

        .enabyteord(1'b0),

        .enapatternalign(rx_enapatternalign[0]),

        .errdetect(wire_receive_pcs0_errdetect),

        .fifordin(1'b0),

        .fifordout(),

        .fiforesetrd(1'b0),

        .hipdataout(),

        .hipdatavalid(),

        .hipelecidle(),

        .hipphydonestatus(),

        .hipstatus(),

        .invpol(1'b0),

        .k1detect(),

        .k2detect(),

        .masterclk(1'b0),

        .parallelfdbk({20{1'b0}}),

        .patterndetect(wire_receive_pcs0_patterndetect),

        .phfifooverflow(),

        .phfifordenable(rx_phfifordenable[0]),

        .phfifordenableout(),

        .phfiforeset(rx_phfiforeset[0]),

        .phfiforesetout(),

        .phfifounderflow(),

        .phfifowrdisable(rx_phfifowrdisable[0]),

        .phfifowrdisableout(),

        .pipebufferstat(),

        .pipedatavalid(),

        .pipeelecidle(),

        .pipephydonestatus(),

        .pipepowerdown({2{1'b0}}),

        .pipepowerstate({4{1'b0}}),

        .pipestatetransdoneout(),

        .pipestatus(),

        .prbscidenable(rx_prbscidenable[0]),

        .quadreset(cent_unit_quadresetout[0]),

        .rdalign(),

        .recoveredclk(rx_pma_clockout[0]),

        .revbitorderwa(1'b0),

        .revparallelfdbkdata(),

        .rlv(wire_receive_pcs0_rlv),

        .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),

        .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),

        .rmfifoempty(),

        .rmfifofull(),

        .rmfifordena(1'b0),

        .rmfiforeset(1'b0),

        .rmfifowrena(1'b0),

        .runningdisp(wire_receive_pcs0_runningdisp),

        .rxdetectvalid(1'b0),

        .rxfound({2{1'b0}}),

        .signaldetect(),

        .signaldetected(rx_signaldetect_wire[0]),

        .syncstatus(wire_receive_pcs0_syncstatus),

        .syncstatusdeskew(),

        .xauidelcondmetout(),

        .xauififoovrout(),

        .xauiinsertincompleteout(),

        .xauilatencycompout(),

        .xgmctrldet(),

        .xgmctrlin(1'b0),

        .xgmdatain({8{1'b0}}),

        .xgmdataout(),

        .xgmdatavalid(),

        .xgmrunningdisp()

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_off

        `endif

        ,

        .bitslip(1'b0),

        .elecidleinfersel({3{1'b0}}),

        .grayelecidleinferselfromtx({3{1'b0}}),

        .hip8b10binvpolarity(1'b0),

        .hipelecidleinfersel({3{1'b0}}),

        .hippowerdown({2{1'b0}}),

        .localrefclk(1'b0),

        .phfifox4bytesel(1'b0),

        .phfifox4rdenable(1'b0),

        .phfifox4wrclk(1'b0),

        .phfifox4wrenable(1'b0),

        .pipe8b10binvpolarity(1'b0),

        .pipeenrevparallellpbkfromtx(1'b0),

        .pmatestbusin({8{1'b0}}),

        .powerdn({2{1'b0}}),

        .refclk(1'b0),

        .revbyteorderwa(1'b0),

        .wareset(1'b0),

        .xauidelcondmet(1'b0),

        .xauififoovr(1'b0),

        .xauiinsertincomplete(1'b0),

        .xauilatencycomp(1'b0)

        `ifndef FORMAL_VERIFICATION

        // synopsys translate_on

        `endif

        );

        defparam

                receive_pcs0.align_pattern = "1111100",

                receive_pcs0.align_pattern_length = 7,

                receive_pcs0.allow_align_polarity_inversion = "false",

                receive_pcs0.allow_pipe_polarity_inversion = "false",

                receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,

                receive_pcs0.auto_spd_phystatus_notify_count = 0,

                receive_pcs0.bit_slip_enable = "false",

                receive_pcs0.byte_order_mode = "none",

                receive_pcs0.byte_order_pad_pattern = "0",