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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
//
// $Revision: #1 $
// $Date: 2012/06/21 $
// Check in by : $Author: swbranch $
// Author      : Siew Kong NG
//
// Project     : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description : 
//
// RX_SYNC alignment for Alt2gxb, Alt4gxb
 
// 
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
module altera_tse_gxb_aligned_rxsync (
 
  input clk,
  input reset,
 
  input [7:0] alt_dataout,
  input alt_sync,
  input alt_disperr,
  input alt_ctrldetect,
  input alt_errdetect,
  input alt_rmfifodatadeleted,
  input alt_rmfifodatainserted,
  input alt_runlengthviolation,
  input alt_patterndetect,
  input alt_runningdisp,
 
  output reg [7:0] altpcs_dataout,
  output altpcs_sync,
  output reg altpcs_disperr,
  output reg altpcs_ctrldetect,
  output reg altpcs_errdetect,
  output reg altpcs_rmfifodatadeleted,
  output reg altpcs_rmfifodatainserted,
  output reg altpcs_carrierdetect) ;
  parameter DEVICE_FAMILY         = "ARRIAGX";    //  The device family the the core is targetted for. 
  parameter ENABLE_DET_LATENCY      = 0;
 
  //-------------------------------------------------------------------------------
  // intermediate wires
 
 
  //reg altpcs_dataout
 
  // pipelined 1
  reg [7:0] alt_dataout_reg1;
  reg alt_sync_reg1;
  reg alt_sync_reg2;
  reg alt_disperr_reg1;
  reg alt_ctrldetect_reg1;
  reg alt_errdetect_reg1;
  reg alt_rmfifodatadeleted_reg1;
  reg alt_rmfifodatainserted_reg1;
  reg alt_patterndetect_reg1;
  reg alt_runningdisp_reg1;
  reg alt_runlengthviolation_latched;
  //-------------------------------------------------------------------------------
 
 
  always @(posedge reset or posedge clk)
    begin
        if (reset == 1'b1)
            begin
                // pipelined 1
                alt_dataout_reg1            <= 8'h0;
                alt_sync_reg1               <= 1'b0;
                alt_disperr_reg1            <= 1'b0;
                alt_ctrldetect_reg1         <= 1'b0;
                alt_errdetect_reg1          <= 1'b0;
                alt_rmfifodatadeleted_reg1  <= 1'b0;
                alt_rmfifodatainserted_reg1 <= 1'b0;
                alt_patterndetect_reg1      <= 1'b0;
                alt_runningdisp_reg1        <= 1'b0;
            end
        else
            begin
                // pipelined 1
                alt_dataout_reg1            <= alt_dataout;
                alt_sync_reg1               <= alt_sync;
                alt_disperr_reg1            <= alt_disperr;
                alt_ctrldetect_reg1         <= alt_ctrldetect;
                alt_errdetect_reg1          <= alt_errdetect;
                alt_rmfifodatadeleted_reg1  <= alt_rmfifodatadeleted;
                alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
                alt_patterndetect_reg1      <= alt_patterndetect;
                alt_runningdisp_reg1        <= alt_runningdisp;
            end
 
    end
 
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX" || (DEVICE_FAMILY == "STRATIXV" && ENABLE_DET_LATENCY == 1))
begin
                always @ (posedge reset or posedge clk)
                begin
                 if (reset == 1'b1)
                        begin
                                altpcs_dataout              <= 8'h0;
                                altpcs_disperr              <= 1'b1;
                                altpcs_ctrldetect           <= 1'b0;
                                altpcs_errdetect            <= 1'b1;
                                altpcs_rmfifodatadeleted    <= 1'b0;
                                altpcs_rmfifodatainserted   <= 1'b0;
                        end
                 else
                        begin
                           if (alt_sync == 1'b1 )
                                 begin
                                        altpcs_dataout              <= alt_dataout_reg1;
                                        altpcs_disperr              <= alt_disperr_reg1;
                                        altpcs_ctrldetect           <= alt_ctrldetect_reg1;
                                        altpcs_errdetect            <= alt_errdetect_reg1;
                                        altpcs_rmfifodatadeleted    <= alt_rmfifodatadeleted_reg1;
                                        altpcs_rmfifodatainserted   <= alt_rmfifodatainserted_reg1;
                                 end
                           else
                                 begin
                                        altpcs_dataout              <= 8'h0;
                                        altpcs_disperr              <= 1'b1;
                                        altpcs_ctrldetect           <= 1'b0;
                                        altpcs_errdetect            <= 1'b1;
                                        altpcs_rmfifodatadeleted    <= 1'b0;
                                        altpcs_rmfifodatainserted   <= 1'b0;
                                 end
                        end
                end
                assign altpcs_sync              = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGZ"   || DEVICE_FAMILY == "STRATIXV" || DEVICE_FAMILY == "ARRIAV" || DEVICE_FAMILY == "CYCLONEV")
begin
        always @ (posedge reset or posedge clk)
    begin
     if (reset == 1'b1)
        begin
            altpcs_dataout              <= 8'h0;
            altpcs_disperr              <= 1'b1;
            altpcs_ctrldetect           <= 1'b0;
            altpcs_errdetect            <= 1'b1;
            altpcs_rmfifodatadeleted    <= 1'b0;
            altpcs_rmfifodatainserted   <= 1'b0;
                        alt_sync_reg2               <= 1'b0;
        end
     else
        begin
                altpcs_dataout              <= alt_dataout_reg1;
                altpcs_disperr              <= alt_disperr_reg1;
                altpcs_ctrldetect           <= alt_ctrldetect_reg1;
                altpcs_errdetect            <= alt_errdetect_reg1;
                altpcs_rmfifodatadeleted    <= alt_rmfifodatadeleted_reg1;
                altpcs_rmfifodatainserted   <= alt_rmfifodatainserted_reg1;
                                alt_sync_reg2               <= alt_sync_reg1 ;
        end
 
    end
 
 
    assign altpcs_sync              = alt_sync_reg2;
end
endgenerate
 
 
 
 
 
   //latched runlength violation assertion for "carrier_detect" signal generation block
   //reset the latch value after carrier_detect goes de-asserted
//   always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
//    begin
//       if (altpcs_carrierdetect == 1'b0)
//        begin
//           alt_runlengthviolation_latched <= 1'b0;
//        end 
//       else
//        begin 
//           if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
//            begin
//               alt_runlengthviolation_latched <= 1'b1;
//            end
//        end       
//    end
 
 
//    always @ (posedge reset or posedge clk)
//     begin
//      if (reset == 1'b1)
//         begin
//             alt_runlengthviolation_latched_reg <= 1'b0;
//         end
//      else
//         begin
//             alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
//         end
//     end
 
    always @ (posedge reset or posedge clk)
     begin
      if (reset == 1'b1)
         begin
             alt_runlengthviolation_latched <= 1'b0;
         end
      else
       begin
           if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
            begin
               alt_runlengthviolation_latched <= 1'b0;
            end
           else
            begin
               if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
                begin
                   alt_runlengthviolation_latched <= 1'b1;
                end
            end
       end
     end
 
 
   // carrier_detect signal generation
   always @ (posedge reset or posedge clk)
    begin
     if (reset == 1'b1)
        begin
            altpcs_carrierdetect <= 1'b1;
        end
     else
        begin
           if (  (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
                    & alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0                 ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                    & alt_runningdisp_reg1 == 1'b1                                                                                      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                    & alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1                                             ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b1
                   & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
                      (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 ))                               ) |
 
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0                                                                                       ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
                   & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
                      (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 ))                               ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
                                                     (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
              )
 
             begin
                altpcs_carrierdetect              <= 1'b0;
             end
           else
             begin
                altpcs_carrierdetect              <= 1'b1;
             end
        end
 
    end
 
 
 
 
endmodule

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_gxb_aligned_rxsync.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $`
8			`//`
9			`// $Revision: #1 $`
10	20	jefflieu	`// $Date: 2012/06/21 $`
11			`// Check in by : $Author: swbranch $`
12	9	jefflieu	`// Author : Siew Kong NG`
13			`//`
14			`// Project : Triple Speed Ethernet - 1000 BASE-X PCS`
15			`//`
16			`// Description :`
17			`//`
18			`// RX_SYNC alignment for Alt2gxb, Alt4gxb`
19
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2007 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`module altera_tse_gxb_aligned_rxsync (`
29
30			`input clk,`
31			`input reset,`
32
33			`input [7:0] alt_dataout,`
34			`input alt_sync,`
35			`input alt_disperr,`
36			`input alt_ctrldetect,`
37			`input alt_errdetect,`
38			`input alt_rmfifodatadeleted,`
39			`input alt_rmfifodatainserted,`
40			`input alt_runlengthviolation,`
41			`input alt_patterndetect,`
42			`input alt_runningdisp,`
43
44			`output reg [7:0] altpcs_dataout,`
45			`output altpcs_sync,`
46			`output reg altpcs_disperr,`
47			`output reg altpcs_ctrldetect,`
48			`output reg altpcs_errdetect,`
49			`output reg altpcs_rmfifodatadeleted,`
50			`output reg altpcs_rmfifodatainserted,`
51			`output reg altpcs_carrierdetect) ;`
52			`parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.`
53	20	jefflieu	`parameter ENABLE_DET_LATENCY = 0;`
54	9	jefflieu
55			`//-------------------------------------------------------------------------------`
56			`// intermediate wires`
57
58
59			`//reg altpcs_dataout`
60
61			`// pipelined 1`
62			`reg [7:0] alt_dataout_reg1;`
63			`reg alt_sync_reg1;`
64			`reg alt_sync_reg2;`
65			`reg alt_disperr_reg1;`
66			`reg alt_ctrldetect_reg1;`
67			`reg alt_errdetect_reg1;`
68			`reg alt_rmfifodatadeleted_reg1;`
69			`reg alt_rmfifodatainserted_reg1;`
70			`reg alt_patterndetect_reg1;`
71			`reg alt_runningdisp_reg1;`
72			`reg alt_runlengthviolation_latched;`
73			`//-------------------------------------------------------------------------------`
74
75
76			`always @(posedge reset or posedge clk)`
77			`begin`
78			`if (reset == 1'b1)`
79			`begin`
80			`// pipelined 1`
81			`alt_dataout_reg1 <= 8'h0;`
82			`alt_sync_reg1 <= 1'b0;`
83			`alt_disperr_reg1 <= 1'b0;`
84			`alt_ctrldetect_reg1 <= 1'b0;`
85			`alt_errdetect_reg1 <= 1'b0;`
86			`alt_rmfifodatadeleted_reg1 <= 1'b0;`
87			`alt_rmfifodatainserted_reg1 <= 1'b0;`
88			`alt_patterndetect_reg1 <= 1'b0;`
89			`alt_runningdisp_reg1 <= 1'b0;`
90			`end`
91			`else`
92			`begin`
93			`// pipelined 1`
94			`alt_dataout_reg1 <= alt_dataout;`
95			`alt_sync_reg1 <= alt_sync;`
96			`alt_disperr_reg1 <= alt_disperr;`
97			`alt_ctrldetect_reg1 <= alt_ctrldetect;`
98			`alt_errdetect_reg1 <= alt_errdetect;`
99			`alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;`
100			`alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;`
101			`alt_patterndetect_reg1 <= alt_patterndetect;`
102			`alt_runningdisp_reg1 <= alt_runningdisp;`
103			`end`
104
105			`end`
106
107	20	jefflieu	`generate if ( DEVICE_FAMILY == "STRATIXIIGX" \|\| DEVICE_FAMILY == "ARRIAGX" \|\| (DEVICE_FAMILY == "STRATIXV" && ENABLE_DET_LATENCY == 1))`
108	9	jefflieu	`begin`
109			`always @ (posedge reset or posedge clk)`
110			`begin`
111			`if (reset == 1'b1)`
112			`begin`
113			`altpcs_dataout <= 8'h0;`
114			`altpcs_disperr <= 1'b1;`
115			`altpcs_ctrldetect <= 1'b0;`
116			`altpcs_errdetect <= 1'b1;`
117			`altpcs_rmfifodatadeleted <= 1'b0;`
118			`altpcs_rmfifodatainserted <= 1'b0;`
119			`end`
120			`else`
121			`begin`
122			`if (alt_sync == 1'b1 )`
123			`begin`
124			`altpcs_dataout <= alt_dataout_reg1;`
125			`altpcs_disperr <= alt_disperr_reg1;`
126			`altpcs_ctrldetect <= alt_ctrldetect_reg1;`
127			`altpcs_errdetect <= alt_errdetect_reg1;`
128			`altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;`
129			`altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;`
130			`end`
131			`else`
132			`begin`
133			`altpcs_dataout <= 8'h0;`
134			`altpcs_disperr <= 1'b1;`
135			`altpcs_ctrldetect <= 1'b0;`
136			`altpcs_errdetect <= 1'b1;`
137			`altpcs_rmfifodatadeleted <= 1'b0;`
138			`altpcs_rmfifodatainserted <= 1'b0;`
139			`end`
140			`end`
141			`end`
142			`assign altpcs_sync = alt_sync_reg1;`
143			`end`
144	20	jefflieu	`else if ( DEVICE_FAMILY == "STRATIXIV" \|\| DEVICE_FAMILY == "ARRIAIIGX" \|\| DEVICE_FAMILY == "CYCLONEIVGX" \|\| DEVICE_FAMILY == "HARDCOPYIV" \|\| DEVICE_FAMILY == "ARRIAIIGZ" \|\| DEVICE_FAMILY == "STRATIXV" \|\| DEVICE_FAMILY == "ARRIAV" \|\| DEVICE_FAMILY == "CYCLONEV")`
145	9	jefflieu	`begin`
146			`always @ (posedge reset or posedge clk)`
147			`begin`
148			`if (reset == 1'b1)`
149			`begin`
150			`altpcs_dataout <= 8'h0;`
151			`altpcs_disperr <= 1'b1;`
152			`altpcs_ctrldetect <= 1'b0;`
153			`altpcs_errdetect <= 1'b1;`
154			`altpcs_rmfifodatadeleted <= 1'b0;`
155			`altpcs_rmfifodatainserted <= 1'b0;`
156			`alt_sync_reg2 <= 1'b0;`
157			`end`
158			`else`
159			`begin`
160			`altpcs_dataout <= alt_dataout_reg1;`
161			`altpcs_disperr <= alt_disperr_reg1;`
162			`altpcs_ctrldetect <= alt_ctrldetect_reg1;`
163			`altpcs_errdetect <= alt_errdetect_reg1;`
164			`altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;`
165			`altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;`
166			`alt_sync_reg2 <= alt_sync_reg1 ;`
167			`end`
168
169			`end`
170
171
172			`assign altpcs_sync = alt_sync_reg2;`
173			`end`
174			`endgenerate`
175
176
177
178
179
180			`//latched runlength violation assertion for "carrier_detect" signal generation block`
181			`//reset the latch value after carrier_detect goes de-asserted`
182			`// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)`
183			`// begin`
184			`// if (altpcs_carrierdetect == 1'b0)`
185			`// begin`
186			`// alt_runlengthviolation_latched <= 1'b0;`
187			`// end`
188			`// else`
189			`// begin`
190			`// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)`
191			`// begin`
192			`// alt_runlengthviolation_latched <= 1'b1;`
193			`// end`
194			`// end`
195			`// end`
196
197
198			`// always @ (posedge reset or posedge clk)`
199			`// begin`
200			`// if (reset == 1'b1)`
201			`// begin`
202			`// alt_runlengthviolation_latched_reg <= 1'b0;`
203			`// end`
204			`// else`
205			`// begin`
206			`// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;`
207			`// end`
208			`// end`
209
210			`always @ (posedge reset or posedge clk)`
211			`begin`
212			`if (reset == 1'b1)`
213			`begin`
214			`alt_runlengthviolation_latched <= 1'b0;`
215			`end`
216			`else`
217			`begin`
218			`if ((altpcs_carrierdetect == 1'b0) \| (alt_sync == 1'b0))`
219			`begin`
220			`alt_runlengthviolation_latched <= 1'b0;`
221			`end`
222			`else`
223			`begin`
224			`if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))`
225			`begin`
226			`alt_runlengthviolation_latched <= 1'b1;`
227			`end`
228			`end`
229			`end`
230			`end`
231
232
233			`// carrier_detect signal generation`
234			`always @ (posedge reset or posedge clk)`
235			`begin`
236			`if (reset == 1'b1)`
237			`begin`
238			`altpcs_carrierdetect <= 1'b1;`
239			`end`
240			`else`
241			`begin`
242			`if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1`
243			`& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) \|`
244			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) \|`
245			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) \|`
246			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
247			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
248			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
249			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
250			`& alt_runningdisp_reg1 == 1'b1 ) \|`
251			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
252			`& alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) \|`
253			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
254			`& alt_runningdisp_reg1 == 1'b1`
255			`& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)\|`
256			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 )) ) \|`
257
258			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
259			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
260			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
261			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
262			`& alt_runningdisp_reg1 == 1'b0 ) \|`
263			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
264			`& alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1`
265			`& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)\|`
266			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) \|`
267			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
268			`& alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)\|`
269			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )`
270			`)`
271
272			`begin`
273			`altpcs_carrierdetect <= 1'b0;`
274			`end`
275			`else`
276			`begin`
277			`altpcs_carrierdetect <= 1'b1;`
278			`end`
279			`end`
280
281			`end`
282
283
284
285
286			`endmodule`