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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
//
// $Revision: #1 $
// $Date: 2011/11/10 $
// Check in by : $Author: max $
// Author      : Siew Kong NG
//
// Project     : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description : 
//
// RX_SYNC alignment for Alt2gxb, Alt4gxb
 
// 
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
 
module altera_tse_gxb_aligned_rxsync (
 
  input clk,
  input reset,
 
  input [7:0] alt_dataout,
  input alt_sync,
  input alt_disperr,
  input alt_ctrldetect,
  input alt_errdetect,
  input alt_rmfifodatadeleted,
  input alt_rmfifodatainserted,
  input alt_runlengthviolation,
  input alt_patterndetect,
  input alt_runningdisp,
 
  output reg [7:0] altpcs_dataout,
  output altpcs_sync,
  output reg altpcs_disperr,
  output reg altpcs_ctrldetect,
  output reg altpcs_errdetect,
  output reg altpcs_rmfifodatadeleted,
  output reg altpcs_rmfifodatainserted,
  output reg altpcs_carrierdetect) ;
  parameter DEVICE_FAMILY         = "ARRIAGX";    //  The device family the the core is targetted for. 
 
  //-------------------------------------------------------------------------------
  // intermediate wires
 
 
  //reg altpcs_dataout
 
  // pipelined 1
  reg [7:0] alt_dataout_reg1;
  reg alt_sync_reg1;
  reg alt_sync_reg2;
  reg alt_disperr_reg1;
  reg alt_ctrldetect_reg1;
  reg alt_errdetect_reg1;
  reg alt_rmfifodatadeleted_reg1;
  reg alt_rmfifodatainserted_reg1;
  reg alt_patterndetect_reg1;
  reg alt_runningdisp_reg1;
  reg alt_runlengthviolation_latched;
  //-------------------------------------------------------------------------------
 
 
  always @(posedge reset or posedge clk)
    begin
        if (reset == 1'b1)
            begin
                // pipelined 1
                alt_dataout_reg1            <= 8'h0;
                alt_sync_reg1               <= 1'b0;
                alt_disperr_reg1            <= 1'b0;
                alt_ctrldetect_reg1         <= 1'b0;
                alt_errdetect_reg1          <= 1'b0;
                alt_rmfifodatadeleted_reg1  <= 1'b0;
                alt_rmfifodatainserted_reg1 <= 1'b0;
                alt_patterndetect_reg1      <= 1'b0;
                alt_runningdisp_reg1        <= 1'b0;
            end
        else
            begin
                // pipelined 1
                alt_dataout_reg1            <= alt_dataout;
                alt_sync_reg1               <= alt_sync;
                alt_disperr_reg1            <= alt_disperr;
                alt_ctrldetect_reg1         <= alt_ctrldetect;
                alt_errdetect_reg1          <= alt_errdetect;
                alt_rmfifodatadeleted_reg1  <= alt_rmfifodatadeleted;
                alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
                alt_patterndetect_reg1      <= alt_patterndetect;
                alt_runningdisp_reg1        <= alt_runningdisp;
            end
 
    end
 
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX"  || DEVICE_FAMILY == "STRATIXV" || DEVICE_FAMILY == "ARRIAV")
begin
                always @ (posedge reset or posedge clk)
                begin
                 if (reset == 1'b1)
                        begin
                                altpcs_dataout              <= 8'h0;
                                altpcs_disperr              <= 1'b1;
                                altpcs_ctrldetect           <= 1'b0;
                                altpcs_errdetect            <= 1'b1;
                                altpcs_rmfifodatadeleted    <= 1'b0;
                                altpcs_rmfifodatainserted   <= 1'b0;
                        end
                 else
                        begin
                           if (alt_sync == 1'b1 )
                                 begin
                                        altpcs_dataout              <= alt_dataout_reg1;
                                        altpcs_disperr              <= alt_disperr_reg1;
                                        altpcs_ctrldetect           <= alt_ctrldetect_reg1;
                                        altpcs_errdetect            <= alt_errdetect_reg1;
                                        altpcs_rmfifodatadeleted    <= alt_rmfifodatadeleted_reg1;
                                        altpcs_rmfifodatainserted   <= alt_rmfifodatainserted_reg1;
                                 end
                           else
                                 begin
                                        altpcs_dataout              <= 8'h0;
                                        altpcs_disperr              <= 1'b1;
                                        altpcs_ctrldetect           <= 1'b0;
                                        altpcs_errdetect            <= 1'b1;
                                        altpcs_rmfifodatadeleted    <= 1'b0;
                                        altpcs_rmfifodatainserted   <= 1'b0;
                                 end
                        end
                end
                assign altpcs_sync              = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGZ")
begin
        always @ (posedge reset or posedge clk)
    begin
     if (reset == 1'b1)
        begin
            altpcs_dataout              <= 8'h0;
            altpcs_disperr              <= 1'b1;
            altpcs_ctrldetect           <= 1'b0;
            altpcs_errdetect            <= 1'b1;
            altpcs_rmfifodatadeleted    <= 1'b0;
            altpcs_rmfifodatainserted   <= 1'b0;
                        alt_sync_reg2               <= 1'b0;
        end
     else
        begin
                altpcs_dataout              <= alt_dataout_reg1;
                altpcs_disperr              <= alt_disperr_reg1;
                altpcs_ctrldetect           <= alt_ctrldetect_reg1;
                altpcs_errdetect            <= alt_errdetect_reg1;
                altpcs_rmfifodatadeleted    <= alt_rmfifodatadeleted_reg1;
                altpcs_rmfifodatainserted   <= alt_rmfifodatainserted_reg1;
                                alt_sync_reg2               <= alt_sync_reg1 ;
        end
 
    end
 
 
    assign altpcs_sync              = alt_sync_reg2;
end
endgenerate
 
 
 
 
 
   //latched runlength violation assertion for "carrier_detect" signal generation block
   //reset the latch value after carrier_detect goes de-asserted
//   always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
//    begin
//       if (altpcs_carrierdetect == 1'b0)
//        begin
//           alt_runlengthviolation_latched <= 1'b0;
//        end 
//       else
//        begin 
//           if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
//            begin
//               alt_runlengthviolation_latched <= 1'b1;
//            end
//        end       
//    end
 
 
//    always @ (posedge reset or posedge clk)
//     begin
//      if (reset == 1'b1)
//         begin
//             alt_runlengthviolation_latched_reg <= 1'b0;
//         end
//      else
//         begin
//             alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
//         end
//     end
 
    always @ (posedge reset or posedge clk)
     begin
      if (reset == 1'b1)
         begin
             alt_runlengthviolation_latched <= 1'b0;
         end
      else
       begin
           if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
            begin
               alt_runlengthviolation_latched <= 1'b0;
            end
           else
            begin
               if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
                begin
                   alt_runlengthviolation_latched <= 1'b1;
                end
            end
       end
     end
 
 
   // carrier_detect signal generation
   always @ (posedge reset or posedge clk)
    begin
     if (reset == 1'b1)
        begin
            altpcs_carrierdetect <= 1'b1;
        end
     else
        begin
           if (  (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
                    & alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0                 ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                    & alt_runningdisp_reg1 == 1'b1                                                                                      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                    & alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1                                             ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b1
                   & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
                      (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 ))                               ) |
 
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0      ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0                                                                                       ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
                   & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
                      (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 ))                               ) |
                 (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
                   & alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
                                                     (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
              )
 
             begin
                altpcs_carrierdetect              <= 1'b0;
             end
           else
             begin
                altpcs_carrierdetect              <= 1'b1;
             end
        end
 
    end
 
 
 
 
endmodule

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_gxb_aligned_rxsync.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// Revision Control Information`
5			`//`
6			`// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $`
7			`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $`
8			`//`
9			`// $Revision: #1 $`
10			`// $Date: 2011/11/10 $`
11			`// Check in by : $Author: max $`
12			`// Author : Siew Kong NG`
13			`//`
14			`// Project : Triple Speed Ethernet - 1000 BASE-X PCS`
15			`//`
16			`// Description :`
17			`//`
18			`// RX_SYNC alignment for Alt2gxb, Alt4gxb`
19
20			`//`
21			`// ALTERA Confidential and Proprietary`
22			`// Copyright 2007 (c) Altera Corporation`
23			`// All rights reserved`
24			`//`
25			`// -------------------------------------------------------------------------`
26			`// -------------------------------------------------------------------------`
27
28			`module altera_tse_gxb_aligned_rxsync (`
29
30			`input clk,`
31			`input reset,`
32
33			`input [7:0] alt_dataout,`
34			`input alt_sync,`
35			`input alt_disperr,`
36			`input alt_ctrldetect,`
37			`input alt_errdetect,`
38			`input alt_rmfifodatadeleted,`
39			`input alt_rmfifodatainserted,`
40			`input alt_runlengthviolation,`
41			`input alt_patterndetect,`
42			`input alt_runningdisp,`
43
44			`output reg [7:0] altpcs_dataout,`
45			`output altpcs_sync,`
46			`output reg altpcs_disperr,`
47			`output reg altpcs_ctrldetect,`
48			`output reg altpcs_errdetect,`
49			`output reg altpcs_rmfifodatadeleted,`
50			`output reg altpcs_rmfifodatainserted,`
51			`output reg altpcs_carrierdetect) ;`
52			`parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.`
53
54			`//-------------------------------------------------------------------------------`
55			`// intermediate wires`
56
57
58			`//reg altpcs_dataout`
59
60			`// pipelined 1`
61			`reg [7:0] alt_dataout_reg1;`
62			`reg alt_sync_reg1;`
63			`reg alt_sync_reg2;`
64			`reg alt_disperr_reg1;`
65			`reg alt_ctrldetect_reg1;`
66			`reg alt_errdetect_reg1;`
67			`reg alt_rmfifodatadeleted_reg1;`
68			`reg alt_rmfifodatainserted_reg1;`
69			`reg alt_patterndetect_reg1;`
70			`reg alt_runningdisp_reg1;`
71			`reg alt_runlengthviolation_latched;`
72			`//-------------------------------------------------------------------------------`
73
74
75			`always @(posedge reset or posedge clk)`
76			`begin`
77			`if (reset == 1'b1)`
78			`begin`
79			`// pipelined 1`
80			`alt_dataout_reg1 <= 8'h0;`
81			`alt_sync_reg1 <= 1'b0;`
82			`alt_disperr_reg1 <= 1'b0;`
83			`alt_ctrldetect_reg1 <= 1'b0;`
84			`alt_errdetect_reg1 <= 1'b0;`
85			`alt_rmfifodatadeleted_reg1 <= 1'b0;`
86			`alt_rmfifodatainserted_reg1 <= 1'b0;`
87			`alt_patterndetect_reg1 <= 1'b0;`
88			`alt_runningdisp_reg1 <= 1'b0;`
89			`end`
90			`else`
91			`begin`
92			`// pipelined 1`
93			`alt_dataout_reg1 <= alt_dataout;`
94			`alt_sync_reg1 <= alt_sync;`
95			`alt_disperr_reg1 <= alt_disperr;`
96			`alt_ctrldetect_reg1 <= alt_ctrldetect;`
97			`alt_errdetect_reg1 <= alt_errdetect;`
98			`alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;`
99			`alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;`
100			`alt_patterndetect_reg1 <= alt_patterndetect;`
101			`alt_runningdisp_reg1 <= alt_runningdisp;`
102			`end`
103
104			`end`
105
106			`generate if ( DEVICE_FAMILY == "STRATIXIIGX" \|\| DEVICE_FAMILY == "ARRIAGX" \|\| DEVICE_FAMILY == "STRATIXV" \|\| DEVICE_FAMILY == "ARRIAV")`
107			`begin`
108			`always @ (posedge reset or posedge clk)`
109			`begin`
110			`if (reset == 1'b1)`
111			`begin`
112			`altpcs_dataout <= 8'h0;`
113			`altpcs_disperr <= 1'b1;`
114			`altpcs_ctrldetect <= 1'b0;`
115			`altpcs_errdetect <= 1'b1;`
116			`altpcs_rmfifodatadeleted <= 1'b0;`
117			`altpcs_rmfifodatainserted <= 1'b0;`
118			`end`
119			`else`
120			`begin`
121			`if (alt_sync == 1'b1 )`
122			`begin`
123			`altpcs_dataout <= alt_dataout_reg1;`
124			`altpcs_disperr <= alt_disperr_reg1;`
125			`altpcs_ctrldetect <= alt_ctrldetect_reg1;`
126			`altpcs_errdetect <= alt_errdetect_reg1;`
127			`altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;`
128			`altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;`
129			`end`
130			`else`
131			`begin`
132			`altpcs_dataout <= 8'h0;`
133			`altpcs_disperr <= 1'b1;`
134			`altpcs_ctrldetect <= 1'b0;`
135			`altpcs_errdetect <= 1'b1;`
136			`altpcs_rmfifodatadeleted <= 1'b0;`
137			`altpcs_rmfifodatainserted <= 1'b0;`
138			`end`
139			`end`
140			`end`
141			`assign altpcs_sync = alt_sync_reg1;`
142			`end`
143			`else if ( DEVICE_FAMILY == "STRATIXIV" \|\| DEVICE_FAMILY == "ARRIAIIGX" \|\| DEVICE_FAMILY == "CYCLONEIVGX" \|\| DEVICE_FAMILY == "HARDCOPYIV" \|\| DEVICE_FAMILY == "ARRIAIIGZ")`
144			`begin`
145			`always @ (posedge reset or posedge clk)`
146			`begin`
147			`if (reset == 1'b1)`
148			`begin`
149			`altpcs_dataout <= 8'h0;`
150			`altpcs_disperr <= 1'b1;`
151			`altpcs_ctrldetect <= 1'b0;`
152			`altpcs_errdetect <= 1'b1;`
153			`altpcs_rmfifodatadeleted <= 1'b0;`
154			`altpcs_rmfifodatainserted <= 1'b0;`
155			`alt_sync_reg2 <= 1'b0;`
156			`end`
157			`else`
158			`begin`
159			`altpcs_dataout <= alt_dataout_reg1;`
160			`altpcs_disperr <= alt_disperr_reg1;`
161			`altpcs_ctrldetect <= alt_ctrldetect_reg1;`
162			`altpcs_errdetect <= alt_errdetect_reg1;`
163			`altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;`
164			`altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;`
165			`alt_sync_reg2 <= alt_sync_reg1 ;`
166			`end`
167
168			`end`
169
170
171			`assign altpcs_sync = alt_sync_reg2;`
172			`end`
173			`endgenerate`
174
175
176
177
178
179			`//latched runlength violation assertion for "carrier_detect" signal generation block`
180			`//reset the latch value after carrier_detect goes de-asserted`
181			`// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)`
182			`// begin`
183			`// if (altpcs_carrierdetect == 1'b0)`
184			`// begin`
185			`// alt_runlengthviolation_latched <= 1'b0;`
186			`// end`
187			`// else`
188			`// begin`
189			`// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)`
190			`// begin`
191			`// alt_runlengthviolation_latched <= 1'b1;`
192			`// end`
193			`// end`
194			`// end`
195
196
197			`// always @ (posedge reset or posedge clk)`
198			`// begin`
199			`// if (reset == 1'b1)`
200			`// begin`
201			`// alt_runlengthviolation_latched_reg <= 1'b0;`
202			`// end`
203			`// else`
204			`// begin`
205			`// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;`
206			`// end`
207			`// end`
208
209			`always @ (posedge reset or posedge clk)`
210			`begin`
211			`if (reset == 1'b1)`
212			`begin`
213			`alt_runlengthviolation_latched <= 1'b0;`
214			`end`
215			`else`
216			`begin`
217			`if ((altpcs_carrierdetect == 1'b0) \| (alt_sync == 1'b0))`
218			`begin`
219			`alt_runlengthviolation_latched <= 1'b0;`
220			`end`
221			`else`
222			`begin`
223			`if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))`
224			`begin`
225			`alt_runlengthviolation_latched <= 1'b1;`
226			`end`
227			`end`
228			`end`
229			`end`
230
231
232			`// carrier_detect signal generation`
233			`always @ (posedge reset or posedge clk)`
234			`begin`
235			`if (reset == 1'b1)`
236			`begin`
237			`altpcs_carrierdetect <= 1'b1;`
238			`end`
239			`else`
240			`begin`
241			`if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1`
242			`& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) \|`
243			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) \|`
244			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) \|`
245			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
246			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
247			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
248			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
249			`& alt_runningdisp_reg1 == 1'b1 ) \|`
250			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
251			`& alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) \|`
252			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
253			`& alt_runningdisp_reg1 == 1'b1`
254			`& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)\|`
255			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 )) ) \|`
256
257			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
258			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
259			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) \|`
260			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
261			`& alt_runningdisp_reg1 == 1'b0 ) \|`
262			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
263			`& alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1`
264			`& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)\|`
265			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) \|`
266			`(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0`
267			`& alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)\|`
268			`(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )`
269			`)`
270
271			`begin`
272			`altpcs_carrierdetect <= 1'b0;`
273			`end`
274			`else`
275			`begin`
276			`altpcs_carrierdetect <= 1'b1;`
277			`end`
278			`end`
279
280			`end`
281
282
283
284
285			`endmodule`