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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: altera_tse_gxb_gige_inst.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_inst.v,v $
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//
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// Check in by : $Author: max $
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// Author : Siew Kong NG
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//
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// Project : Triple Speed Ethernet - 1000 BASE-X PCS
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//
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// Description :
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//
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// Instantiation for Alt2gxb, Alt4gxb
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2007 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module altera_tse_gxb_gige_inst (
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cal_blk_clk,
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gxb_powerdown,
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pll_inclk,
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reconfig_clk,
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reconfig_togxb,
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rx_analogreset,
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rx_cruclk,
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rx_datain,
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rx_digitalreset,
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rx_seriallpbken,
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tx_ctrlenable,
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tx_datain,
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tx_digitalreset,
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pll_powerdown,
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pll_locked,
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rx_freqlocked,
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reconfig_fromgxb,
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rx_ctrldetect,
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rx_clkout,
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rx_dataout,
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rx_disperr,
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rx_errdetect,
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rx_patterndetect,
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rx_rlv,
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rx_syncstatus,
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tx_clkout,
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tx_dataout,
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rx_recovclkout,
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rx_rmfifodatadeleted,
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rx_rmfifodatainserted,
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rx_runningdisp
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);
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parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
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parameter STARTING_CHANNEL_NUMBER = 0;
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parameter ENABLE_ALT_RECONFIG = 0;
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parameter ENABLE_SGMII = 1; // Use to determine rate match FIFO in ALTGX GIGE mode
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input cal_blk_clk;
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input gxb_powerdown;
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input pll_inclk;
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input reconfig_clk;
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input [3:0] reconfig_togxb;
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input rx_analogreset;
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input rx_cruclk;
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input rx_datain;
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input rx_digitalreset;
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input rx_seriallpbken;
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input tx_ctrlenable;
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input [7:0] tx_datain;
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input tx_digitalreset;
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input pll_powerdown;
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output pll_locked;
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output rx_freqlocked;
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output [16:0] reconfig_fromgxb;
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output rx_ctrldetect;
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output rx_clkout;
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output [7:0] rx_dataout;
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output rx_disperr;
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output rx_errdetect;
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output rx_patterndetect;
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output rx_rlv;
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output rx_syncstatus;
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output tx_clkout;
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output tx_dataout;
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output rx_recovclkout;
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output rx_rmfifodatadeleted;
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output rx_rmfifodatainserted;
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output rx_runningdisp;
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wire [16:0] reconfig_fromgxb;
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wire [2:0] reconfig_togxb_alt2gxb;
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wire reconfig_fromgxb_alt2gxb;
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wire wire_reconfig_clk;
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wire [3:0] wire_reconfig_togxb;
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(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
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wire [16:0] wire_reconfig_fromgxb;
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generate if (ENABLE_ALT_RECONFIG == 0)
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begin
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assign wire_reconfig_clk = 1'b0;
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assign wire_reconfig_togxb = 4'b0010;
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assign reconfig_fromgxb = {17{1'b0}};
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end
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else
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begin
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assign wire_reconfig_clk = reconfig_clk;
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assign wire_reconfig_togxb = reconfig_togxb;
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assign reconfig_fromgxb = wire_reconfig_fromgxb;
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end
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endgenerate
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generate if ((DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX") && (ENABLE_SGMII == 0))
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begin
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altera_tse_alt2gxb_gige the_altera_tse_alt2gxb_gige
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(
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.cal_blk_clk (cal_blk_clk),
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.gxb_powerdown (gxb_powerdown),
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.pll_inclk (pll_inclk),
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.reconfig_clk(wire_reconfig_clk),
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.reconfig_togxb(reconfig_togxb_alt2gxb),
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.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
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.rx_analogreset (rx_analogreset),
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.rx_cruclk (rx_cruclk),
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.rx_ctrldetect (rx_ctrldetect),
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.rx_clkout (rx_clkout),
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.rx_datain (rx_datain),
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.rx_dataout (rx_dataout),
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.rx_digitalreset (rx_digitalreset),
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.rx_disperr (rx_disperr),
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.rx_errdetect (rx_errdetect),
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.rx_patterndetect (rx_patterndetect),
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.rx_rlv (rx_rlv),
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.rx_seriallpbken (rx_seriallpbken),
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.rx_syncstatus (rx_syncstatus),
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.tx_clkout (tx_clkout),
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.tx_ctrlenable (tx_ctrlenable),
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.tx_datain (tx_datain),
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.tx_dataout (tx_dataout),
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.tx_digitalreset (tx_digitalreset),
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.rx_recovclkout(rx_recovclkout),
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.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
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.rx_rmfifodatainserted(rx_rmfifodatainserted),
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.rx_runningdisp(rx_runningdisp),
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.rx_freqlocked(rx_freqlocked),
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.pll_locked(pll_locked)
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);
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defparam
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the_altera_tse_alt2gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER,
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the_altera_tse_alt2gxb_gige.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
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assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
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assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
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end
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endgenerate
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generate if ((DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX") && (ENABLE_SGMII == 1))
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begin
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altera_tse_alt2gxb_gige_wo_rmfifo the_altera_tse_alt2gxb_gige_wo_rmfifo
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(
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.cal_blk_clk (cal_blk_clk),
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.gxb_powerdown (gxb_powerdown),
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.pll_inclk (pll_inclk),
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.reconfig_clk(wire_reconfig_clk),
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.reconfig_togxb(reconfig_togxb_alt2gxb),
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.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
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.rx_analogreset (rx_analogreset),
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.rx_cruclk (rx_cruclk),
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.rx_ctrldetect (rx_ctrldetect),
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.rx_clkout (rx_clkout),
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.rx_datain (rx_datain),
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.rx_dataout (rx_dataout),
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.rx_digitalreset (rx_digitalreset),
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.rx_disperr (rx_disperr),
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.rx_errdetect (rx_errdetect),
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.rx_patterndetect (rx_patterndetect),
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.rx_rlv (rx_rlv),
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.rx_seriallpbken (rx_seriallpbken),
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.rx_syncstatus (rx_syncstatus),
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.tx_clkout (tx_clkout),
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.tx_ctrlenable (tx_ctrlenable),
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.tx_datain (tx_datain),
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.tx_dataout (tx_dataout),
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.tx_digitalreset (tx_digitalreset),
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.rx_recovclkout(rx_recovclkout),
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.rx_rmfifodatadeleted(),
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.rx_rmfifodatainserted(),
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.rx_runningdisp(rx_runningdisp),
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.rx_freqlocked(rx_freqlocked),
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.pll_locked(pll_locked)
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);
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defparam
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the_altera_tse_alt2gxb_gige_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER,
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the_altera_tse_alt2gxb_gige_wo_rmfifo.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
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assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
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assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
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assign rx_rmfifodatadeleted = 1'b0;
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assign rx_rmfifodatainserted = 1'b0;
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end
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endgenerate
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generate if ((DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "ARRIAIIGZ") && (ENABLE_SGMII == 0))
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begin
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| 241 |
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altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
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(
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.cal_blk_clk (cal_blk_clk),
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| 245 |
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.fixedclk(wire_reconfig_clk),
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.fixedclk_fast(6'b0),
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| 247 |
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.gxb_powerdown (gxb_powerdown),
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| 248 |
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.pll_inclk (pll_inclk),
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| 249 |
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.reconfig_clk(wire_reconfig_clk),
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| 250 |
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.reconfig_togxb(wire_reconfig_togxb),
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| 251 |
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.reconfig_fromgxb(wire_reconfig_fromgxb),
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| 252 |
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.rx_analogreset (rx_analogreset),
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| 253 |
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.rx_cruclk (rx_cruclk),
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.rx_ctrldetect (rx_ctrldetect),
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| 255 |
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.rx_clkout (rx_clkout),
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| 256 |
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.rx_datain (rx_datain),
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| 257 |
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.rx_dataout (rx_dataout),
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| 258 |
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.rx_digitalreset (rx_digitalreset),
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| 259 |
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.rx_disperr (rx_disperr),
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| 260 |
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.rx_errdetect (rx_errdetect),
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| 261 |
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.rx_patterndetect (rx_patterndetect),
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| 262 |
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.rx_rlv (rx_rlv),
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| 263 |
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.rx_seriallpbken (rx_seriallpbken),
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| 264 |
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.rx_syncstatus (rx_syncstatus),
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| 265 |
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.tx_clkout (tx_clkout),
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| 266 |
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.tx_ctrlenable (tx_ctrlenable),
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| 267 |
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.tx_datain (tx_datain),
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| 268 |
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.tx_dataout (tx_dataout),
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| 269 |
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.tx_digitalreset (tx_digitalreset),
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| 270 |
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.rx_recovclkout(rx_recovclkout),
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| 271 |
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.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
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| 272 |
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.rx_rmfifodatainserted(rx_rmfifodatainserted),
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.rx_runningdisp(rx_runningdisp),
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| 274 |
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.pll_powerdown(pll_powerdown),
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| 275 |
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.rx_freqlocked(rx_freqlocked),
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.pll_locked(pll_locked)
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| 277 |
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);
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| 278 |
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defparam
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| 279 |
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the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
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| 280 |
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| 281 |
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end
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| 282 |
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endgenerate
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| 283 |
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| 284 |
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generate if ((DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "ARRIAIIGZ" ) && (ENABLE_SGMII == 1))
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| 285 |
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begin
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| 286 |
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| 287 |
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altera_tse_alt4gxb_gige_wo_rmfifo the_altera_tse_alt4gxb_gige_wo_rmfifo
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| 288 |
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(
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| 289 |
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.cal_blk_clk (cal_blk_clk),
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| 290 |
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.fixedclk(wire_reconfig_clk),
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| 291 |
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.fixedclk_fast(6'b0),
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| 292 |
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.gxb_powerdown (gxb_powerdown),
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| 293 |
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.pll_inclk (pll_inclk),
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| 294 |
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.reconfig_clk(wire_reconfig_clk),
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| 295 |
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.reconfig_togxb(wire_reconfig_togxb),
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| 296 |
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.reconfig_fromgxb(wire_reconfig_fromgxb),
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| 297 |
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.rx_analogreset (rx_analogreset),
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| 298 |
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.rx_cruclk (rx_cruclk),
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| 299 |
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.rx_ctrldetect (rx_ctrldetect),
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| 300 |
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.rx_clkout (rx_clkout),
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| 301 |
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.rx_datain (rx_datain),
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| 302 |
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.rx_dataout (rx_dataout),
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| 303 |
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.rx_digitalreset (rx_digitalreset),
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| 304 |
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.rx_disperr (rx_disperr),
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| 305 |
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.rx_errdetect (rx_errdetect),
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| 306 |
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.rx_patterndetect (rx_patterndetect),
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| 307 |
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.rx_rlv (rx_rlv),
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| 308 |
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.rx_seriallpbken (rx_seriallpbken),
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| 309 |
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.rx_syncstatus (rx_syncstatus),
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| 310 |
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.tx_clkout (tx_clkout),
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| 311 |
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.tx_ctrlenable (tx_ctrlenable),
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| 312 |
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.tx_datain (tx_datain),
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| 313 |
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.tx_dataout (tx_dataout),
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| 314 |
|
|
.tx_digitalreset (tx_digitalreset),
|
| 315 |
|
|
.rx_recovclkout(rx_recovclkout),
|
| 316 |
|
|
.rx_rmfifodatadeleted(),
|
| 317 |
|
|
.rx_rmfifodatainserted(),
|
| 318 |
|
|
.rx_runningdisp(rx_runningdisp),
|
| 319 |
|
|
.pll_powerdown(pll_powerdown),
|
| 320 |
|
|
.rx_freqlocked(rx_freqlocked),
|
| 321 |
|
|
.pll_locked(pll_locked)
|
| 322 |
|
|
);
|
| 323 |
|
|
defparam
|
| 324 |
|
|
the_altera_tse_alt4gxb_gige_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER;
|
| 325 |
|
|
|
| 326 |
|
|
assign rx_rmfifodatadeleted = 1'b0;
|
| 327 |
|
|
assign rx_rmfifodatainserted = 1'b0;
|
| 328 |
|
|
|
| 329 |
|
|
end
|
| 330 |
|
|
endgenerate
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
generate if ((DEVICE_FAMILY == "CYCLONEIVGX") && (ENABLE_SGMII == 0))
|
| 334 |
|
|
begin
|
| 335 |
|
|
|
| 336 |
|
|
altera_tse_altgx_civgx_gige the_altera_tse_alt_gx_civgx
|
| 337 |
|
|
(
|
| 338 |
|
|
.cal_blk_clk (cal_blk_clk),
|
| 339 |
|
|
.fixedclk(wire_reconfig_clk),
|
| 340 |
|
|
.fixedclk_fast(1'b0),
|
| 341 |
|
|
.gxb_powerdown (gxb_powerdown),
|
| 342 |
|
|
.pll_inclk (pll_inclk),
|
| 343 |
|
|
.reconfig_clk(wire_reconfig_clk),
|
| 344 |
|
|
.reconfig_togxb(wire_reconfig_togxb),
|
| 345 |
|
|
.rx_analogreset (rx_analogreset),
|
| 346 |
|
|
.rx_ctrldetect (rx_ctrldetect),
|
| 347 |
|
|
.rx_clkout (rx_clkout),
|
| 348 |
|
|
.rx_datain (rx_datain),
|
| 349 |
|
|
.rx_dataout (rx_dataout),
|
| 350 |
|
|
.rx_digitalreset (rx_digitalreset),
|
| 351 |
|
|
.rx_disperr (rx_disperr),
|
| 352 |
|
|
.rx_errdetect (rx_errdetect),
|
| 353 |
|
|
.rx_patterndetect (rx_patterndetect),
|
| 354 |
|
|
.rx_rlv (rx_rlv),
|
| 355 |
|
|
.rx_syncstatus (rx_syncstatus),
|
| 356 |
|
|
.tx_clkout (tx_clkout),
|
| 357 |
|
|
.tx_ctrlenable (tx_ctrlenable),
|
| 358 |
|
|
.tx_datain (tx_datain),
|
| 359 |
|
|
.tx_dataout (tx_dataout),
|
| 360 |
|
|
.tx_digitalreset (tx_digitalreset),
|
| 361 |
|
|
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
|
| 362 |
|
|
.rx_recovclkout(rx_recovclkout),
|
| 363 |
|
|
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
|
| 364 |
|
|
.rx_rmfifodatainserted(rx_rmfifodatainserted),
|
| 365 |
|
|
.rx_runningdisp(rx_runningdisp),
|
| 366 |
|
|
.pll_areset(pll_powerdown),
|
| 367 |
|
|
.rx_freqlocked(rx_freqlocked),
|
| 368 |
|
|
.pll_locked(pll_locked)
|
| 369 |
|
|
);
|
| 370 |
|
|
defparam
|
| 371 |
|
|
the_altera_tse_alt_gx_civgx.starting_channel_number = STARTING_CHANNEL_NUMBER;
|
| 372 |
|
|
end
|
| 373 |
|
|
endgenerate
|
| 374 |
|
|
|
| 375 |
|
|
generate if ((DEVICE_FAMILY == "CYCLONEIVGX") && (ENABLE_SGMII == 1))
|
| 376 |
|
|
begin
|
| 377 |
|
|
|
| 378 |
|
|
altera_tse_altgx_civgx_gige_wo_rmfifo the_altera_tse_alt_gx_civgx_wo_rmfifo
|
| 379 |
|
|
(
|
| 380 |
|
|
.cal_blk_clk (cal_blk_clk),
|
| 381 |
|
|
.fixedclk(wire_reconfig_clk),
|
| 382 |
|
|
.fixedclk_fast(1'b0),
|
| 383 |
|
|
.gxb_powerdown (gxb_powerdown),
|
| 384 |
|
|
.pll_inclk (pll_inclk),
|
| 385 |
|
|
.reconfig_clk(wire_reconfig_clk),
|
| 386 |
|
|
.reconfig_togxb(wire_reconfig_togxb),
|
| 387 |
|
|
.rx_analogreset (rx_analogreset),
|
| 388 |
|
|
.rx_ctrldetect (rx_ctrldetect),
|
| 389 |
|
|
.rx_clkout (rx_clkout),
|
| 390 |
|
|
.rx_datain (rx_datain),
|
| 391 |
|
|
.rx_dataout (rx_dataout),
|
| 392 |
|
|
.rx_digitalreset (rx_digitalreset),
|
| 393 |
|
|
.rx_disperr (rx_disperr),
|
| 394 |
|
|
.rx_errdetect (rx_errdetect),
|
| 395 |
|
|
.rx_patterndetect (rx_patterndetect),
|
| 396 |
|
|
.rx_rlv (rx_rlv),
|
| 397 |
|
|
.rx_syncstatus (rx_syncstatus),
|
| 398 |
|
|
.tx_clkout (tx_clkout),
|
| 399 |
|
|
.tx_ctrlenable (tx_ctrlenable),
|
| 400 |
|
|
.tx_datain (tx_datain),
|
| 401 |
|
|
.tx_dataout (tx_dataout),
|
| 402 |
|
|
.tx_digitalreset (tx_digitalreset),
|
| 403 |
|
|
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
|
| 404 |
|
|
.rx_recovclkout(rx_recovclkout),
|
| 405 |
|
|
.rx_rmfifodatadeleted(),
|
| 406 |
|
|
.rx_rmfifodatainserted(),
|
| 407 |
|
|
.rx_runningdisp(rx_runningdisp),
|
| 408 |
|
|
.pll_areset(pll_powerdown),
|
| 409 |
|
|
.rx_freqlocked(rx_freqlocked),
|
| 410 |
|
|
.pll_locked(pll_locked)
|
| 411 |
|
|
);
|
| 412 |
|
|
defparam
|
| 413 |
|
|
the_altera_tse_alt_gx_civgx_wo_rmfifo.starting_channel_number = STARTING_CHANNEL_NUMBER;
|
| 414 |
|
|
|
| 415 |
|
|
assign rx_rmfifodatadeleted = 1'b0;
|
| 416 |
|
|
assign rx_rmfifodatainserted = 1'b0;
|
| 417 |
|
|
end
|
| 418 |
|
|
endgenerate
|
| 419 |
|
|
|
| 420 |
|
|
endmodule
|
