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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// 
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation  
// All rights reserved
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
module altera_tse_lvds_reset_sequencer (
        clk,
        reset,
        rx_locked,
        rx_channel_data_align,
    pll_areset,
        rx_reset,
        rx_cda_reset
        );
 
        input           clk;
        input           reset;
        input           rx_locked;
        output          rx_channel_data_align;
        output          pll_areset;
        output          rx_reset;
        output          rx_cda_reset;
 
        reg                     rx_channel_data_align;
        reg                     pll_areset;
        reg                     rx_reset;
        reg                     rx_cda_reset;
 
        wire                    rx_locked_sync;
        reg                     rx_locked_sync_d1;
        reg                     rx_locked_sync_d2;
        reg                     rx_locked_sync_d3;
        reg                     rx_locked_stable;
 
        reg [2:0]   pulse_count;
 
        reg [2:0]        state;
        reg [2:0]        nextstate;
 
        // State Definitions
        parameter [2:0] stm_idle                 = 3'b000; //0
        parameter [2:0] stm_pll_areset           = 3'b001; //1
        parameter [2:0] stm_rx_reset             = 3'b010; //2
        parameter [2:0] stm_rx_cda_reset = 3'b011; //3
        parameter [2:0] stm_word_alignment       = 3'b100; //4
 
        altera_std_synchronizer #(2) rx_locked_altera_std_synchronizer (
                .clk ( clk ),
                .reset_n ( ~reset ),
                .din ( rx_locked ),
                .dout ( rx_locked_sync )
        );
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset == 1'b1) begin
                        rx_locked_sync_d1 <= 1'b0;
                        rx_locked_sync_d2 <= 1'b0;
                        rx_locked_sync_d3 <= 1'b0;
                end
                else begin
                        rx_locked_sync_d1 <= rx_locked_sync;
                        rx_locked_sync_d2 <= rx_locked_sync_d1;
                        rx_locked_sync_d3 <= rx_locked_sync_d2;
                end
        end
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset == 1'b1) begin
                        rx_locked_stable <= 1'b0;
                end
                else begin
                        rx_locked_stable <= rx_locked_sync & rx_locked_sync_d1 & rx_locked_sync_d2 & rx_locked_sync_d3;
                end
        end
 
 
        // FSM
        always @ (posedge clk or posedge reset)
        begin
                if (reset == 1'b1) begin
                        state <= stm_pll_areset;
                end
                else begin
                        state <= nextstate;
                end
        end
 
        always @ (*)
        begin
    case (state)
        stm_idle:
                if (reset == 1'b1) begin
                        nextstate = stm_pll_areset;
                end
                else begin
                        nextstate = stm_idle;
                end
        stm_pll_areset:
                begin
                        nextstate = stm_rx_reset;
                end
        stm_rx_reset:
                if (rx_locked_stable == 1'b0) begin
                        nextstate = stm_rx_reset;
                end
                else begin
                        nextstate = stm_rx_cda_reset;
                end
        stm_rx_cda_reset:
        begin
                        nextstate = stm_word_alignment;
                end
    stm_word_alignment:
                if (pulse_count == 4) begin
                        nextstate = stm_idle;
                end
                else begin
                        nextstate = stm_word_alignment;
                end
        default:
                begin
                        nextstate = stm_idle;
                end
        endcase
        end
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset == 1'b1) begin
                        pll_areset <= 1'b1;
                        rx_reset <= 1'b1;
                        rx_cda_reset <= 1'b0;
            rx_channel_data_align <= 1'b0;
            pulse_count <= 3'b000;
                end
                else begin
                case (nextstate)
                stm_idle:
                        begin
                                pll_areset <= 1'b0;
                                rx_reset <= 1'b0;
                                rx_cda_reset <= 1'b0;
                rx_channel_data_align <= 1'b0;
                pulse_count <= 3'b000;
                        end
                stm_pll_areset:
                        begin
                                pll_areset <= 1'b1;
                                rx_reset <= 1'b1;
                                rx_cda_reset <= 1'b0;
                rx_channel_data_align <= 1'b0;
                pulse_count <= 3'b000;
                        end
                stm_rx_reset:
                        begin
                                pll_areset <= 1'b0;
                                rx_cda_reset <= 1'b0;
                rx_channel_data_align <= 1'b0;
                pulse_count <= 3'b000;
                        end
                stm_rx_cda_reset:
                        begin
                                pll_areset <= 1'b0;
                                rx_reset <= 1'b0;
                                rx_cda_reset <= 1'b1;
                rx_channel_data_align <= 1'b0;
                pulse_count <= 3'b000;
                        end
        stm_word_alignment:
                        begin
                                pll_areset <= 1'b0;
                                rx_reset <= 1'b0;
                                rx_cda_reset <= 1'b0;
                rx_channel_data_align <= ~rx_channel_data_align;
                pulse_count <= pulse_count +1'b1;
                        end
                default:
                        begin
                                pll_areset <= 1'b0;
                                rx_reset <= 1'b0;
                                rx_cda_reset <= 1'b0;
                rx_channel_data_align <= 1'b0;
                pulse_count <= 3'b000;
                        end
                endcase
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	9	jefflieu	`// -------------------------------------------------------------------------`
2			`// -------------------------------------------------------------------------`
3			`//`
4			`// ALTERA Confidential and Proprietary`
5			`// Copyright 2006 (c) Altera Corporation`
6			`// All rights reserved`
7			`// -------------------------------------------------------------------------`
8			`// -------------------------------------------------------------------------`
9			`module altera_tse_lvds_reset_sequencer (`
10			`clk,`
11			`reset,`
12			`rx_locked,`
13			`rx_channel_data_align,`
14			`pll_areset,`
15			`rx_reset,`
16			`rx_cda_reset`
17			`);`
18
19			`input clk;`
20			`input reset;`
21			`input rx_locked;`
22			`output rx_channel_data_align;`
23			`output pll_areset;`
24			`output rx_reset;`
25			`output rx_cda_reset;`
26
27			`reg rx_channel_data_align;`
28			`reg pll_areset;`
29			`reg rx_reset;`
30			`reg rx_cda_reset;`
31
32			`wire rx_locked_sync;`
33			`reg rx_locked_sync_d1;`
34			`reg rx_locked_sync_d2;`
35			`reg rx_locked_sync_d3;`
36			`reg rx_locked_stable;`
37
38			`reg [2:0] pulse_count;`
39
40			`reg [2:0] state;`
41			`reg [2:0] nextstate;`
42
43			`// State Definitions`
44			`parameter [2:0] stm_idle = 3'b000; //0`
45			`parameter [2:0] stm_pll_areset = 3'b001; //1`
46			`parameter [2:0] stm_rx_reset = 3'b010; //2`
47			`parameter [2:0] stm_rx_cda_reset = 3'b011; //3`
48			`parameter [2:0] stm_word_alignment = 3'b100; //4`
49
50			`altera_std_synchronizer #(2) rx_locked_altera_std_synchronizer (`
51			`.clk ( clk ),`
52			`.reset_n ( ~reset ),`
53			`.din ( rx_locked ),`
54			`.dout ( rx_locked_sync )`
55			`);`
56
57			`always @ (posedge clk or posedge reset)`
58			`begin`
59			`if (reset == 1'b1) begin`
60			`rx_locked_sync_d1 <= 1'b0;`
61			`rx_locked_sync_d2 <= 1'b0;`
62			`rx_locked_sync_d3 <= 1'b0;`
63			`end`
64			`else begin`
65			`rx_locked_sync_d1 <= rx_locked_sync;`
66			`rx_locked_sync_d2 <= rx_locked_sync_d1;`
67			`rx_locked_sync_d3 <= rx_locked_sync_d2;`
68			`end`
69			`end`
70
71			`always @ (posedge clk or posedge reset)`
72			`begin`
73			`if (reset == 1'b1) begin`
74			`rx_locked_stable <= 1'b0;`
75			`end`
76			`else begin`
77			`rx_locked_stable <= rx_locked_sync & rx_locked_sync_d1 & rx_locked_sync_d2 & rx_locked_sync_d3;`
78			`end`
79			`end`
80
81
82			`// FSM`
83			`always @ (posedge clk or posedge reset)`
84			`begin`
85			`if (reset == 1'b1) begin`
86			`state <= stm_pll_areset;`
87			`end`
88			`else begin`
89			`state <= nextstate;`
90			`end`
91			`end`
92
93			`always @ (*)`
94			`begin`
95			`case (state)`
96			`stm_idle:`
97			`if (reset == 1'b1) begin`
98			`nextstate = stm_pll_areset;`
99			`end`
100			`else begin`
101			`nextstate = stm_idle;`
102			`end`
103			`stm_pll_areset:`
104			`begin`
105			`nextstate = stm_rx_reset;`
106			`end`
107			`stm_rx_reset:`
108			`if (rx_locked_stable == 1'b0) begin`
109			`nextstate = stm_rx_reset;`
110			`end`
111			`else begin`
112			`nextstate = stm_rx_cda_reset;`
113			`end`
114			`stm_rx_cda_reset:`
115			`begin`
116			`nextstate = stm_word_alignment;`
117			`end`
118			`stm_word_alignment:`
119			`if (pulse_count == 4) begin`
120			`nextstate = stm_idle;`
121			`end`
122			`else begin`
123			`nextstate = stm_word_alignment;`
124			`end`
125			`default:`
126			`begin`
127			`nextstate = stm_idle;`
128			`end`
129			`endcase`
130			`end`
131
132			`always @ (posedge clk or posedge reset)`
133			`begin`
134			`if (reset == 1'b1) begin`
135			`pll_areset <= 1'b1;`
136			`rx_reset <= 1'b1;`
137			`rx_cda_reset <= 1'b0;`
138			`rx_channel_data_align <= 1'b0;`
139			`pulse_count <= 3'b000;`
140			`end`
141			`else begin`
142			`case (nextstate)`
143			`stm_idle:`
144			`begin`
145			`pll_areset <= 1'b0;`
146			`rx_reset <= 1'b0;`
147			`rx_cda_reset <= 1'b0;`
148			`rx_channel_data_align <= 1'b0;`
149			`pulse_count <= 3'b000;`
150			`end`
151			`stm_pll_areset:`
152			`begin`
153			`pll_areset <= 1'b1;`
154			`rx_reset <= 1'b1;`
155			`rx_cda_reset <= 1'b0;`
156			`rx_channel_data_align <= 1'b0;`
157			`pulse_count <= 3'b000;`
158			`end`
159			`stm_rx_reset:`
160			`begin`
161			`pll_areset <= 1'b0;`
162			`rx_cda_reset <= 1'b0;`
163			`rx_channel_data_align <= 1'b0;`
164			`pulse_count <= 3'b000;`
165			`end`
166			`stm_rx_cda_reset:`
167			`begin`
168			`pll_areset <= 1'b0;`
169			`rx_reset <= 1'b0;`
170			`rx_cda_reset <= 1'b1;`
171			`rx_channel_data_align <= 1'b0;`
172			`pulse_count <= 3'b000;`
173			`end`
174			`stm_word_alignment:`
175			`begin`
176			`pll_areset <= 1'b0;`
177			`rx_reset <= 1'b0;`
178			`rx_cda_reset <= 1'b0;`
179			`rx_channel_data_align <= ~rx_channel_data_align;`
180			`pulse_count <= pulse_count +1'b1;`
181			`end`
182			`default:`
183			`begin`
184			`pll_areset <= 1'b0;`
185			`rx_reset <= 1'b0;`
186			`rx_cda_reset <= 1'b0;`
187			`rx_channel_data_align <= 1'b0;`
188			`pulse_count <= 3'b000;`
189			`end`
190			`endcase`
191			`end`
192			`end`
193
194			`endmodule`

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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_lvds_reset_sequencer.v] - Blame information for rev 9