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jefflieu |
// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: altera_tse_mac_pcs.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs.v,v $
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//
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// $Revision: #1 $
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// $Date: 2011/11/10 $
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// Check in by : $Author: max $
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// Author : Arul Paniandi
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//
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// Project : Triple Speed Ethernet
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//
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// Description :
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//
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// Top level module for Triple Speed Ethernet MAC + PCS
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
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module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
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clk, // Avalon slave - clock
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read, // Avalon slave - read
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write, // Avalon slave - write
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address, // Avalon slave - address
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writedata, // Avalon slave - writedata
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readdata, // Avalon slave - readdata
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waitrequest, // Avalon slave - waitrequest
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reset, // Avalon slave - reset
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reset_rx_clk,
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reset_tx_clk,
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reset_ff_rx_clk,
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reset_ff_tx_clk,
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ff_rx_clk, // AtlanticII source - clk
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ff_rx_data, // AtlanticII source - data
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ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
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ff_rx_sop, // AtlanticII source - startofpacket
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ff_rx_eop, // AtlanticII source - endofpacket
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rx_err, // AtlanticII source - error
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rx_err_stat, // AtlanticII source - component_specific_signal(eop)
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rx_frm_type, // AtlanticII source - component_specific_signal(data)
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ff_rx_rdy, // AtlanticII source - ready
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ff_rx_dval, // AtlanticII source - valid
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ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
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ff_tx_clk, // AtlanticII sink - clk
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ff_tx_data, // AtlanticII sink - data
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ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
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ff_tx_sop, // AtlanticII sink - startofpacket
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ff_tx_eop, // AtlanticII sink - endofpacket
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ff_tx_err, // AtlanticII sink - error
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ff_tx_wren, // AtlanticII sink - valid
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ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
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ff_tx_rdy, // AtlanticII sink - ready
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ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
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tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
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ff_rx_a_full,
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ff_rx_a_empty,
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ff_tx_a_full,
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ff_tx_a_empty,
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xoff_gen,
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xon_gen,
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magic_sleep_n,
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magic_wakeup,
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mdc,
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mdio_in,
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mdio_out,
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mdio_oen,
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tbi_rx_clk,
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tbi_tx_clk,
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tbi_rx_d,
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tbi_tx_d,
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sd_loopback,
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powerdown,
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led_col,
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led_an,
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led_char_err,
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led_disp_err,
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led_crs,
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led_link
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);
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parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
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parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
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parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
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parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
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parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
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parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
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parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
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parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
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parameter EG_FIFO = 256 ; // Egress FIFO Depth
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parameter EG_ADDR = 8 ; // Egress FIFO Depth
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parameter ING_FIFO = 256 ; // Ingress FIFO Depth
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parameter ING_ADDR = 8 ; // Egress FIFO Depth
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parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
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parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
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parameter CORE_VERSION = 16'h3; // ALTERA Core Version
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parameter CUST_VERSION = 1 ; // Customer Core Version
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parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
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parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
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parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
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parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
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parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
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parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
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parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
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parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
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parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
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parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
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parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
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parameter RAM_TYPE = "AUTO"; // Specify the RAM type
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parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
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parameter PHY_IDENTIFIER = 32'h 00000000;
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parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
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parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
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parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
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parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
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parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
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parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
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parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
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input clk; // 25MHz Host Interface Clock
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input read; // Register Read Strobe
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input write; // Register Write Strobe
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input [7:0] address; // Register Address
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input [31:0] writedata; // Write Data for Host Bus
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output [31:0] readdata; // Read Data to Host Bus
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output waitrequest; // Interface Busy
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input reset; // Asynchronous Reset
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input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
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input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
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input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
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input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
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input ff_rx_clk; // Transmit Local Clock
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output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
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output [1:0] ff_rx_mod; // Data Modulo
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output ff_rx_sop; // Start of Packet
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output ff_rx_eop; // End of Packet
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output [5:0] rx_err; // Errored Packet Indication
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output [17:0] rx_err_stat; // Packet Length and Status Word
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output [3:0] rx_frm_type; // Unicast Frame Indication
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input ff_rx_rdy; // PHY Application Ready
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output ff_rx_dval; // Data Valid Strobe
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output ff_rx_dsav; // Data Available
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input ff_tx_clk; // Transmit Local Clock
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input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
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input [1:0] ff_tx_mod; // Data Modulo
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input ff_tx_sop; // Start of Packet
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input ff_tx_eop; // End of Packet
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input ff_tx_err; // Errored Packet
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input ff_tx_wren; // Write Enable
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input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
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output ff_tx_rdy; // FIFO Ready
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output ff_tx_septy; // FIFO has space for at least one section
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output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
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output ff_rx_a_full; // Receive FIFO Almost Full
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output ff_rx_a_empty; // Receive FIFO Almost Empty
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output ff_tx_a_full; // Transmit FIFO Almost Full
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output ff_tx_a_empty; // Transmit FIFO Almost Empty
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input xoff_gen; // Xoff Pause frame generate
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input xon_gen; // Xon Pause frame generate
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input magic_sleep_n; // Enable Sleep Mode
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output magic_wakeup; // Wake Up Request
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output mdc; // 2.5MHz Inteface
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input mdio_in; // MDIO Input
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output mdio_out; // MDIO Output
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output mdio_oen; // MDIO Output Enable
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input tbi_rx_clk; // 125MHz Recoved Clock
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input tbi_tx_clk; // 125MHz Transmit Clock
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input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
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output [9:0] tbi_tx_d; // Transmit TBI Interface
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output sd_loopback; // SERDES Loopback Enable
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output powerdown; // Powerdown Enable
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output led_crs; // Carrier Sense
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output led_link; // Valid Link
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output led_col; // Collision Indication
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output led_an; // Auto-Negotiation Status
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output led_char_err; // Character Error
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output led_disp_err; // Disparity Error
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wire [31:0] reg_data_out;
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wire reg_busy;
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wire [ENABLE_ENA-1:0] ff_rx_data;
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wire [1:0] ff_rx_mod;
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wire ff_rx_sop;
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wire ff_rx_eop;
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wire ff_rx_dval;
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wire ff_rx_dsav;
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wire ff_tx_rdy;
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wire ff_tx_septy;
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wire tx_ff_uflow;
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wire magic_wakeup;
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wire ff_rx_a_full;
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wire ff_rx_a_empty;
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wire ff_tx_a_full;
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wire ff_tx_a_empty;
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wire mdc;
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wire mdio_out;
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wire mdio_oen;
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wire [9:0] tbi_tx_d;
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wire sd_loopback;
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wire powerdown;
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wire led_crs;
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wire led_link;
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wire led_col;
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wire led_an;
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wire led_char_err;
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wire led_disp_err;
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wire rx_clk;
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wire tx_clk;
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wire rx_clkena;
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wire tx_clkena;
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wire [7:0] gm_rx_d; // GMII Receive Data
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wire gm_rx_dv; // GMII Receive Frame Enable
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wire gm_rx_err; // GMII Receive Frame Error
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wire [7:0] gm_tx_d; // GMII Transmit Data
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wire gm_tx_en; // GMII Transmit Frame Enable
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wire gm_tx_err; // GMII Transmit Frame Error
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wire [3:0] m_rx_d; // MII Receive Data
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wire m_rx_dv; // MII Receive Frame Enable
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wire m_rx_err; // MII Receive Drame Error
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wire [3:0] m_tx_d; // MII Transmit Data
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wire m_tx_en; // MII Transmit Frame Enable
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wire m_tx_err; // MII Transmit Frame Error
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wire m_rx_crs; // Carrier Sense
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wire m_rx_col; // Collition
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wire set_1000; // Gigabit Mode Enable
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wire set_10; // 10Mbps Mode Enable
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wire pcs_en;
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wire [31:0]readdata_mac;
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wire waitrequest_mac;
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wire [31:0]readdata_pcs;
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wire waitrequest_pcs;
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wire write_pcs;
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wire read_pcs;
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wire write_mac;
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wire read_mac;
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wire [5:0] rx_err;
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wire [17:0] rx_err_stat;
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wire [3:0] rx_frm_type;
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// Reset Lines
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// -----------
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wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
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wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
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wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
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wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
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wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
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// This is done because the PCS address space is from 0x80 to 0x9F
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// ---------------------------------------------------------------
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assign pcs_en = address[7] & !address[6] & !address[5];
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assign write_pcs = pcs_en? write : 1'b0;
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assign read_pcs = pcs_en? read : 1'b0;
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assign write_mac = pcs_en? 1'b0 : write;
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assign read_mac = pcs_en? 1'b0 : read;
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assign readdata = pcs_en? readdata_pcs : readdata_mac;
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assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
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assign readdata_pcs[31:16] = {16{1'b0}};
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// Programmable Reset Options
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// --------------------------
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generate if (USE_SYNC_RESET == 1)
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begin
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altera_tse_reset_synchronizer reset_sync_0 (
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.clk(rx_clk),
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.reset_in(reset),
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.reset_out(reset_rx_clk_int)
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);
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altera_tse_reset_synchronizer reset_sync_1 (
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.clk(tx_clk),
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.reset_in(reset),
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.reset_out(reset_tx_clk_int)
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);
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altera_tse_reset_synchronizer reset_sync_2 (
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.clk(ff_rx_clk),
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.reset_in(reset),
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.reset_out(reset_ff_rx_clk_int)
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);
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altera_tse_reset_synchronizer reset_sync_3 (
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.clk(ff_tx_clk),
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.reset_in(reset),
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.reset_out(reset_ff_tx_clk_int)
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);
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altera_tse_reset_synchronizer reset_sync_4 (
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.clk(clk),
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.reset_in(reset),
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.reset_out(reset_reg_clk_int)
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);
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end
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else
|
316 |
|
|
begin
|
317 |
|
|
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
|
318 |
|
|
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
|
319 |
|
|
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
|
320 |
|
|
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
|
321 |
|
|
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
|
322 |
|
|
end
|
323 |
|
|
endgenerate
|
324 |
|
|
|
325 |
|
|
// --------------------------
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
altera_tse_top_gen_host top_gen_host_inst(
|
329 |
|
|
.reset_ff_rx_clk(reset_ff_rx_clk_int),
|
330 |
|
|
.reset_ff_tx_clk(reset_ff_tx_clk_int),
|
331 |
|
|
.reset_reg_clk(reset_reg_clk_int),
|
332 |
|
|
.reset_rx_clk(reset_rx_clk_int),
|
333 |
|
|
.reset_tx_clk(reset_tx_clk_int),
|
334 |
|
|
.rx_clk(rx_clk),
|
335 |
|
|
.tx_clk(tx_clk),
|
336 |
|
|
.rx_clkena(rx_clkena),
|
337 |
|
|
.tx_clkena(tx_clkena),
|
338 |
|
|
.gm_rx_dv(gm_rx_dv),
|
339 |
|
|
.gm_rx_d(gm_rx_d),
|
340 |
|
|
.gm_rx_err(gm_rx_err),
|
341 |
|
|
.m_rx_en(m_rx_dv),
|
342 |
|
|
.m_rx_d(m_rx_d),
|
343 |
|
|
.m_rx_err(m_rx_err),
|
344 |
|
|
.m_rx_col(m_rx_col),
|
345 |
|
|
.m_rx_crs(m_rx_crs),
|
346 |
|
|
.set_1000(set_1000),
|
347 |
|
|
.set_10(set_10),
|
348 |
|
|
.ff_rx_clk(ff_rx_clk),
|
349 |
|
|
.ff_rx_rdy(ff_rx_rdy),
|
350 |
|
|
.ff_tx_clk(ff_tx_clk),
|
351 |
|
|
.ff_tx_wren(ff_tx_wren),
|
352 |
|
|
.ff_tx_data(ff_tx_data),
|
353 |
|
|
.ff_tx_mod(ff_tx_mod),
|
354 |
|
|
.ff_tx_sop(ff_tx_sop),
|
355 |
|
|
.ff_tx_eop(ff_tx_eop),
|
356 |
|
|
.ff_tx_err(ff_tx_err),
|
357 |
|
|
.ff_tx_crc_fwd(ff_tx_crc_fwd),
|
358 |
|
|
.reg_clk(clk),
|
359 |
|
|
.reg_addr(address),
|
360 |
|
|
.reg_data_in(writedata),
|
361 |
|
|
.reg_rd(read_mac),
|
362 |
|
|
.reg_wr(write_mac),
|
363 |
|
|
.mdio_in(mdio_in),
|
364 |
|
|
.gm_tx_en(gm_tx_en),
|
365 |
|
|
.gm_tx_d(gm_tx_d),
|
366 |
|
|
.gm_tx_err(gm_tx_err),
|
367 |
|
|
.m_tx_en(m_tx_en),
|
368 |
|
|
.m_tx_d(m_tx_d),
|
369 |
|
|
.m_tx_err(m_tx_err),
|
370 |
|
|
.eth_mode(),
|
371 |
|
|
.ena_10(),
|
372 |
|
|
.ff_rx_dval(ff_rx_dval),
|
373 |
|
|
.ff_rx_data(ff_rx_data),
|
374 |
|
|
.ff_rx_mod(ff_rx_mod),
|
375 |
|
|
.ff_rx_sop(ff_rx_sop),
|
376 |
|
|
.ff_rx_eop(ff_rx_eop),
|
377 |
|
|
.ff_rx_dsav(ff_rx_dsav),
|
378 |
|
|
.rx_err(rx_err),
|
379 |
|
|
.rx_err_stat(rx_err_stat),
|
380 |
|
|
.rx_frm_type(rx_frm_type),
|
381 |
|
|
.ff_tx_rdy(ff_tx_rdy),
|
382 |
|
|
.ff_tx_septy(ff_tx_septy),
|
383 |
|
|
.tx_ff_uflow(tx_ff_uflow),
|
384 |
|
|
.rx_a_full(ff_rx_a_full),
|
385 |
|
|
.rx_a_empty(ff_rx_a_empty),
|
386 |
|
|
.tx_a_full(ff_tx_a_full),
|
387 |
|
|
.tx_a_empty(ff_tx_a_empty),
|
388 |
|
|
.xoff_gen(xoff_gen),
|
389 |
|
|
.xon_gen(xon_gen),
|
390 |
|
|
.reg_data_out(readdata_mac),
|
391 |
|
|
.reg_busy(waitrequest_mac),
|
392 |
|
|
.reg_sleepN(magic_sleep_n),
|
393 |
|
|
.reg_wakeup(magic_wakeup),
|
394 |
|
|
.mdc(mdc),
|
395 |
|
|
.mdio_out(mdio_out),
|
396 |
|
|
.mdio_oen(mdio_oen));
|
397 |
|
|
|
398 |
|
|
defparam
|
399 |
|
|
top_gen_host_inst.EG_FIFO = EG_FIFO,
|
400 |
|
|
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
|
401 |
|
|
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
|
402 |
|
|
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
|
403 |
|
|
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
|
404 |
|
|
top_gen_host_inst.EG_ADDR = EG_ADDR,
|
405 |
|
|
top_gen_host_inst.ENA_HASH = ENA_HASH,
|
406 |
|
|
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
|
407 |
|
|
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
|
408 |
|
|
top_gen_host_inst.ING_FIFO = ING_FIFO,
|
409 |
|
|
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
|
410 |
|
|
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
|
411 |
|
|
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
|
412 |
|
|
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
|
413 |
|
|
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
|
414 |
|
|
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
|
415 |
|
|
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
|
416 |
|
|
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
|
417 |
|
|
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
|
418 |
|
|
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
|
419 |
|
|
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
|
420 |
|
|
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
|
421 |
|
|
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
|
422 |
|
|
top_gen_host_inst.ING_ADDR = ING_ADDR,
|
423 |
|
|
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
|
424 |
|
|
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
|
425 |
|
|
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
|
426 |
|
|
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
|
427 |
|
|
top_gen_host_inst.INSERT_TA = INSERT_TA,
|
428 |
|
|
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
|
429 |
|
|
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
|
430 |
|
|
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
|
431 |
|
|
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
|
432 |
|
|
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
|
433 |
|
|
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
altera_tse_top_1000_base_x top_1000_base_x_inst(
|
438 |
|
|
.reset_rx_clk(reset_rx_clk_int),
|
439 |
|
|
.reset_tx_clk(reset_tx_clk_int),
|
440 |
|
|
.reset_reg_clk(reset_reg_clk_int),
|
441 |
|
|
.rx_clk(rx_clk),
|
442 |
|
|
.tx_clk(tx_clk),
|
443 |
|
|
.rx_clkena(rx_clkena),
|
444 |
|
|
.tx_clkena(tx_clkena),
|
445 |
|
|
.ref_clk(1'b0),
|
446 |
|
|
.gmii_rx_dv(gm_rx_dv),
|
447 |
|
|
.gmii_rx_d(gm_rx_d),
|
448 |
|
|
.gmii_rx_err(gm_rx_err),
|
449 |
|
|
.gmii_tx_en(gm_tx_en),
|
450 |
|
|
.gmii_tx_d(gm_tx_d),
|
451 |
|
|
.gmii_tx_err(gm_tx_err),
|
452 |
|
|
.mii_rx_dv(m_rx_dv),
|
453 |
|
|
.mii_rx_d(m_rx_d),
|
454 |
|
|
.mii_rx_err(m_rx_err),
|
455 |
|
|
.mii_tx_en(m_tx_en),
|
456 |
|
|
.mii_tx_d(m_tx_d),
|
457 |
|
|
.mii_tx_err(m_tx_err),
|
458 |
|
|
.mii_col(m_rx_col),
|
459 |
|
|
.mii_crs(m_rx_crs),
|
460 |
|
|
.tbi_rx_clk(tbi_rx_clk),
|
461 |
|
|
.tbi_tx_clk(tbi_tx_clk),
|
462 |
|
|
.tbi_rx_d(tbi_rx_d),
|
463 |
|
|
.tbi_tx_d(tbi_tx_d),
|
464 |
|
|
.sd_loopback(sd_loopback),
|
465 |
|
|
.reg_clk(clk),
|
466 |
|
|
.reg_rd(read_pcs),
|
467 |
|
|
.reg_wr(write_pcs),
|
468 |
|
|
.reg_addr(address[4:0]),
|
469 |
|
|
.reg_data_in(writedata[15:0]),
|
470 |
|
|
.reg_data_out(readdata_pcs[15:0]),
|
471 |
|
|
.reg_busy(waitrequest_pcs),
|
472 |
|
|
.powerdown(powerdown),
|
473 |
|
|
.set_10(set_10),
|
474 |
|
|
.set_100(),
|
475 |
|
|
.set_1000(set_1000),
|
476 |
|
|
.hd_ena(),
|
477 |
|
|
.led_col(led_col),
|
478 |
|
|
.led_an(led_an),
|
479 |
|
|
.led_char_err(led_char_err),
|
480 |
|
|
.led_disp_err(led_disp_err),
|
481 |
|
|
.led_crs(led_crs),
|
482 |
|
|
.led_link(led_link));
|
483 |
|
|
|
484 |
|
|
defparam
|
485 |
|
|
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
|
486 |
|
|
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
|
487 |
|
|
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
endmodule
|