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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: altera_tse_mac_pcs_pma.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma.v,v $
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//
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// $Revision: #1 $
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jefflieu |
// $Date: 2012/06/21 $
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// Check in by : $Author: swbranch $
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jefflieu |
// Author : Arul Paniandi
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//
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// Project : Triple Speed Ethernet
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//
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// Description :
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//
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// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
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module altera_tse_mac_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,C105\"" */ (
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// inputs:
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address,
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clk,
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ff_rx_clk,
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ff_rx_rdy,
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ff_tx_clk,
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ff_tx_crc_fwd,
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ff_tx_data,
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ff_tx_mod,
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ff_tx_eop,
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ff_tx_err,
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ff_tx_sop,
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ff_tx_wren,
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gxb_cal_blk_clk,
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gxb_pwrdn_in,
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magic_sleep_n,
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mdio_in,
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read,
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ref_clk,
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reset,
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rxp,
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write,
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writedata,
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xoff_gen,
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xon_gen,
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// outputs:
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ff_rx_a_empty,
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ff_rx_a_full,
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ff_rx_data,
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ff_rx_mod,
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ff_rx_dsav,
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ff_rx_dval,
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ff_rx_eop,
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ff_rx_sop,
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ff_tx_a_empty,
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ff_tx_a_full,
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ff_tx_rdy,
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ff_tx_septy,
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led_an,
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led_char_err,
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led_col,
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led_crs,
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led_disp_err,
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led_link,
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magic_wakeup,
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mdc,
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mdio_oen,
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mdio_out,
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pcs_pwrdn_out,
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readdata,
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rx_err,
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rx_err_stat,
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rx_frm_type,
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tx_ff_uflow,
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txp,
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rx_recovclkout,
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waitrequest
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);
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// Parameters to configure the core for different variations
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// ---------------------------------------------------------
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parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
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parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
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parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
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parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
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parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
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parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
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parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
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parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
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parameter EG_FIFO = 256 ; // Egress FIFO Depth
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parameter EG_ADDR = 8 ; // Egress FIFO Depth
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parameter ING_FIFO = 256 ; // Ingress FIFO Depth
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parameter ING_ADDR = 8 ; // Egress FIFO Depth
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parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
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parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
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parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
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parameter CUST_VERSION = 1 ; // Customer Core Version
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parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
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parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
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parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
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parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
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parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
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parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
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parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
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parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
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parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
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parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
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parameter RAM_TYPE = "AUTO"; // Specify the RAM type
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parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
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parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
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parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
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parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
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parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
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parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
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parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
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parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
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parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
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parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
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parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 ? LVDS I/O
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parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
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parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
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output ff_rx_a_empty;
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output ff_rx_a_full;
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output [ENABLE_ENA-1:0] ff_rx_data;
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output [1:0] ff_rx_mod;
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output ff_rx_dsav;
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output ff_rx_dval;
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output ff_rx_eop;
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output ff_rx_sop;
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output ff_tx_a_empty;
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output ff_tx_a_full;
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output ff_tx_rdy;
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output ff_tx_septy;
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output led_an;
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output led_char_err;
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output led_col;
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output led_crs;
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output led_disp_err;
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output led_link;
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output magic_wakeup;
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output mdc;
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output mdio_oen;
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output mdio_out;
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output pcs_pwrdn_out;
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output [31: 0] readdata;
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output [5: 0] rx_err;
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output [17: 0] rx_err_stat;
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output [3: 0] rx_frm_type;
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output tx_ff_uflow;
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output txp;
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output rx_recovclkout;
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output waitrequest;
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input [7: 0] address;
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input clk;
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input ff_rx_clk;
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input ff_rx_rdy;
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input ff_tx_clk;
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input ff_tx_crc_fwd;
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input [ENABLE_ENA-1:0] ff_tx_data;
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input [1:0] ff_tx_mod;
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input ff_tx_eop;
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input ff_tx_err;
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input ff_tx_sop;
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input ff_tx_wren;
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input gxb_cal_blk_clk;
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input gxb_pwrdn_in;
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input magic_sleep_n;
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input mdio_in;
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input read;
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input ref_clk;
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input reset;
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input rxp;
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input write;
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input [31:0] writedata;
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input xoff_gen;
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input xon_gen;
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wire MAC_PCS_reset;
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wire ff_rx_a_empty;
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wire ff_rx_a_full;
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wire [ENABLE_ENA-1:0] ff_rx_data;
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wire [1:0] ff_rx_mod;
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wire ff_rx_dsav;
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wire ff_rx_dval;
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wire ff_rx_eop;
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wire ff_rx_sop;
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wire ff_tx_a_empty;
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wire ff_tx_a_full;
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wire ff_tx_rdy;
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wire ff_tx_septy;
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wire led_an;
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wire led_char_err;
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wire led_col;
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wire led_crs;
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wire led_disp_err;
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wire led_link;
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wire magic_wakeup;
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wire mdc;
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wire mdio_oen;
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wire mdio_out;
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wire pcs_pwrdn_out_sig;
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wire gxb_pwrdn_in_sig;
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wire gxb_cal_blk_clk_sig;
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wire [31:0] readdata;
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wire [5:0] rx_err;
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wire [17: 0] rx_err_stat;
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wire [3:0] rx_frm_type;
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wire sd_loopback;
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wire tbi_rx_clk;
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wire [9:0] tbi_rx_d;
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wire tbi_tx_clk;
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wire [9:0] tbi_tx_d;
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wire tx_ff_uflow;
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wire txp;
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wire waitrequest;
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wire [9:0] tbi_rx_d_lvds;
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reg [9:0] tbi_rx_d_flip;
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reg [9:0] tbi_tx_d_flip;
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wire reset_ref_clk_int;
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wire reset_tbi_rx_clk_int;
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wire pll_areset,rx_cda_reset,rx_channel_data_align,rx_locked;
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wire rx_reset;
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// Export recovered clock
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assign rx_recovclkout = tbi_rx_clk;
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// Assign the digital reset of the PMA to the MAC_PCS logic
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// --------------------------------------------------------
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assign MAC_PCS_reset = rx_reset;
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// Instantiation of the MAC_PCS core that connects to a PMA
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// --------------------------------------------------------
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altera_tse_mac_pcs_pma_ena altera_tse_mac_pcs_pma_ena_inst
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(
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.address (address),
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.clk (clk),
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.ff_rx_a_empty (ff_rx_a_empty),
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.ff_rx_a_full (ff_rx_a_full),
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.ff_rx_clk (ff_rx_clk),
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.ff_rx_data (ff_rx_data),
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.ff_rx_mod (ff_rx_mod),
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.ff_rx_dsav (ff_rx_dsav),
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.ff_rx_dval (ff_rx_dval),
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.ff_rx_eop (ff_rx_eop),
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.ff_rx_rdy (ff_rx_rdy),
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.ff_rx_sop (ff_rx_sop),
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280 |
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.ff_tx_a_empty (ff_tx_a_empty),
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.ff_tx_a_full (ff_tx_a_full),
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282 |
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.ff_tx_clk (ff_tx_clk),
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283 |
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.ff_tx_crc_fwd (ff_tx_crc_fwd),
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.ff_tx_data (ff_tx_data),
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.ff_tx_mod (ff_tx_mod),
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.ff_tx_eop (ff_tx_eop),
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.ff_tx_err (ff_tx_err),
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288 |
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.ff_tx_rdy (ff_tx_rdy),
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289 |
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.ff_tx_septy (ff_tx_septy),
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.ff_tx_sop (ff_tx_sop),
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.ff_tx_wren (ff_tx_wren),
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.led_an (led_an),
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293 |
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.led_char_err (led_char_err),
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294 |
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.led_col (led_col),
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295 |
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.led_crs (led_crs),
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296 |
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.led_disp_err (led_disp_err),
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297 |
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.led_link (led_link),
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.magic_sleep_n (magic_sleep_n),
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299 |
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.magic_wakeup (magic_wakeup),
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.mdc (mdc),
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301 |
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.mdio_in (mdio_in),
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302 |
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.mdio_oen (mdio_oen),
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303 |
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.mdio_out (mdio_out),
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.powerdown (pcs_pwrdn_out_sig),
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.read (read),
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.readdata (readdata),
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.reset (MAC_PCS_reset),
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.rx_err (rx_err),
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309 |
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.rx_err_stat (rx_err_stat),
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310 |
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.rx_frm_type (rx_frm_type),
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311 |
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.sd_loopback (sd_loopback),
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312 |
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.tbi_rx_clk (tbi_rx_clk),
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313 |
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.tbi_rx_d (tbi_rx_d),
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314 |
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.tbi_tx_clk (tbi_tx_clk),
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315 |
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.tbi_tx_d (tbi_tx_d),
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316 |
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.tx_ff_uflow (tx_ff_uflow),
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.waitrequest (waitrequest),
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318 |
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.write (write),
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.writedata (writedata),
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320 |
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.xoff_gen (xoff_gen),
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321 |
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.xon_gen (xon_gen)
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);
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323 |
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324 |
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defparam
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325 |
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altera_tse_mac_pcs_pma_ena_inst.ENABLE_ENA = ENABLE_ENA,
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326 |
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altera_tse_mac_pcs_pma_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
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327 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
|
328 |
|
|
altera_tse_mac_pcs_pma_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
|
329 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
|
330 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENA_HASH = ENA_HASH,
|
331 |
|
|
altera_tse_mac_pcs_pma_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
|
332 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
|
333 |
|
|
altera_tse_mac_pcs_pma_ena_inst.EG_FIFO = EG_FIFO,
|
334 |
|
|
altera_tse_mac_pcs_pma_ena_inst.EG_ADDR = EG_ADDR,
|
335 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ING_FIFO = ING_FIFO,
|
336 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ING_ADDR = ING_ADDR,
|
337 |
|
|
altera_tse_mac_pcs_pma_ena_inst.RESET_LEVEL = RESET_LEVEL,
|
338 |
|
|
altera_tse_mac_pcs_pma_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
|
339 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CORE_VERSION = CORE_VERSION,
|
340 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CUST_VERSION = CUST_VERSION,
|
341 |
|
|
altera_tse_mac_pcs_pma_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
|
342 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
|
343 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
|
344 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
|
345 |
|
|
altera_tse_mac_pcs_pma_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
|
346 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
|
347 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
|
348 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
|
349 |
|
|
altera_tse_mac_pcs_pma_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
|
350 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
|
351 |
|
|
altera_tse_mac_pcs_pma_ena_inst.INSERT_TA = INSERT_TA,
|
352 |
|
|
altera_tse_mac_pcs_pma_ena_inst.RAM_TYPE = RAM_TYPE,
|
353 |
|
|
altera_tse_mac_pcs_pma_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
|
354 |
|
|
altera_tse_mac_pcs_pma_ena_inst.DEV_VERSION = DEV_VERSION,
|
355 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
|
356 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
|
357 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
|
358 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
|
359 |
|
|
altera_tse_mac_pcs_pma_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
|
360 |
|
|
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
|
361 |
|
|
|
362 |
|
|
|
363 |
|
|
|
364 |
|
|
// Export powerdown signal or wire it internally
|
365 |
|
|
// ---------------------------------------------
|
366 |
|
|
generate if (EXPORT_PWRDN == 1)
|
367 |
|
|
begin
|
368 |
|
|
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
|
369 |
|
|
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
|
370 |
|
|
end
|
371 |
|
|
else
|
372 |
|
|
begin
|
373 |
|
|
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
|
374 |
|
|
end
|
375 |
|
|
endgenerate
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
// Either one of these blocks below will be instantiated depending on the parameterization
|
381 |
|
|
// that is chosen.
|
382 |
|
|
// ---------------------------------------------------------------------------------------
|
383 |
|
|
|
384 |
|
|
// Instantiation of the Alt2gxb block as the PMA for devices other than ArriaGX
|
385 |
|
|
// ----------------------------------------------------------------------------
|
386 |
|
|
|
387 |
|
|
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
|
388 |
|
|
// ----------------------------------------------------------------
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
|
394 |
|
|
//
|
395 |
|
|
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
|
396 |
|
|
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
|
397 |
|
|
// reversal algorithm.
|
398 |
|
|
// -------------------------------------------------------------------------
|
399 |
|
|
|
400 |
|
|
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
|
401 |
|
|
begin
|
402 |
|
|
|
403 |
|
|
assign tbi_tx_clk = ref_clk;
|
404 |
|
|
assign tbi_rx_d = tbi_rx_d_flip;
|
405 |
|
|
|
406 |
|
|
altera_tse_reset_synchronizer reset_sync_0 (
|
407 |
|
|
.clk(ref_clk),
|
408 |
|
|
.reset_in(reset),
|
409 |
|
|
.reset_out(reset_ref_clk_int)
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
altera_tse_reset_synchronizer reset_sync_1 (
|
413 |
|
|
.clk(tbi_rx_clk),
|
414 |
|
|
.reset_in(reset),
|
415 |
|
|
.reset_out(reset_tbi_rx_clk_int)
|
416 |
|
|
);
|
417 |
|
|
|
418 |
|
|
always @(posedge tbi_rx_clk or posedge reset_tbi_rx_clk_int)
|
419 |
|
|
begin
|
420 |
|
|
if (reset_tbi_rx_clk_int == 1)
|
421 |
|
|
tbi_rx_d_flip <= 0;
|
422 |
|
|
else
|
423 |
|
|
begin
|
424 |
|
|
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
|
425 |
|
|
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
|
426 |
|
|
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
|
427 |
|
|
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
|
428 |
|
|
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
|
429 |
|
|
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
|
430 |
|
|
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
|
431 |
|
|
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
|
432 |
|
|
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
|
433 |
|
|
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
|
434 |
|
|
end
|
435 |
|
|
end
|
436 |
|
|
|
437 |
|
|
always @(posedge ref_clk or posedge reset_ref_clk_int)
|
438 |
|
|
begin
|
439 |
|
|
if (reset_ref_clk_int == 1)
|
440 |
|
|
tbi_tx_d_flip <= 0;
|
441 |
|
|
else
|
442 |
|
|
begin
|
443 |
|
|
tbi_tx_d_flip[0] <= tbi_tx_d[9];
|
444 |
|
|
tbi_tx_d_flip[1] <= tbi_tx_d[8];
|
445 |
|
|
tbi_tx_d_flip[2] <= tbi_tx_d[7];
|
446 |
|
|
tbi_tx_d_flip[3] <= tbi_tx_d[6];
|
447 |
|
|
tbi_tx_d_flip[4] <= tbi_tx_d[5];
|
448 |
|
|
tbi_tx_d_flip[5] <= tbi_tx_d[4];
|
449 |
|
|
tbi_tx_d_flip[6] <= tbi_tx_d[3];
|
450 |
|
|
tbi_tx_d_flip[7] <= tbi_tx_d[2];
|
451 |
|
|
tbi_tx_d_flip[8] <= tbi_tx_d[1];
|
452 |
|
|
tbi_tx_d_flip[9] <= tbi_tx_d[0];
|
453 |
|
|
end
|
454 |
|
|
end
|
455 |
|
|
|
456 |
|
|
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
|
457 |
|
|
(
|
458 |
|
|
.pll_areset ( reset ),
|
459 |
|
|
.rx_cda_reset ( rx_cda_reset ),
|
460 |
|
|
.rx_channel_data_align ( rx_channel_data_align ),
|
461 |
|
|
.rx_locked ( rx_locked ),
|
462 |
|
|
.rx_divfwdclk (tbi_rx_clk),
|
463 |
|
|
.rx_in (rxp),
|
464 |
|
|
.rx_inclock (ref_clk),
|
465 |
|
|
.rx_out (tbi_rx_d_lvds),
|
466 |
|
|
.rx_outclock (),
|
467 |
|
|
.rx_reset (rx_reset)
|
468 |
|
|
);
|
469 |
|
|
|
470 |
|
|
altera_tse_lvds_reset_sequencer the_altera_tse_lvds_reset_sequencer (
|
471 |
|
|
.clk ( clk ),
|
472 |
|
|
.reset ( reset_ref_clk_int ),
|
473 |
|
|
.rx_locked ( rx_locked ),
|
474 |
|
|
.rx_channel_data_align ( rx_channel_data_align ),
|
475 |
|
|
.pll_areset ( pll_areset ),
|
476 |
|
|
.rx_reset (rx_reset),
|
477 |
|
|
.rx_cda_reset ( rx_cda_reset )
|
478 |
|
|
);
|
479 |
|
|
|
480 |
|
|
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
|
481 |
|
|
(
|
482 |
|
|
.tx_in (tbi_tx_d_flip),
|
483 |
|
|
.tx_inclock (ref_clk),
|
484 |
|
|
.pll_areset ( reset ),
|
485 |
|
|
.tx_out (txp)
|
486 |
|
|
);
|
487 |
|
|
|
488 |
|
|
end
|
489 |
|
|
endgenerate
|
490 |
|
|
|
491 |
|
|
endmodule
|
492 |
|
|
|