OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_multi_mac.v] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 jefflieu 
// -------------------------------------------------------------------------
2 
// -------------------------------------------------------------------------
3 
//
4 
// Revision Control Information
5 
//
6 
// $RCSfile: altera_tse_multi_mac.v,v $
7 
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac.v,v $
8 
//
9 
// $Revision: #1 $
10 
// $Date: 2011/11/10 $
11 
// Check in by : $Author: max $
12 
// Author      : Arul Paniandi
13 
//
14 
// Project     : Triple Speed Ethernet - 10/100/1000 MAC
15 
//
16 
// Description :
17 
//
18 
// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
19 
// interfaces, mdio module and register space (statistic, control and
20 
// management)
21 
 
22 
//
23 
// ALTERA Confidential and Proprietary
24 
// Copyright 2006 (c) Altera Corporation
25 
// All rights reserved
26 
//
27 
// -------------------------------------------------------------------------
28 
// -------------------------------------------------------------------------
29 
 
30 
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
31 
module altera_tse_multi_mac
32 
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
33 
#(
34 
 
35 
parameter USE_SYNC_RESET        = 0,                    //  Use Synchronized Reset Inputs
36 
parameter RESET_LEVEL           = 1'b 1 ,               //  Reset Active Level
37 
parameter ENABLE_GMII_LOOPBACK  = 1,                    //  GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
38 
parameter ENABLE_HD_LOGIC       = 1,                    //  HD_LOGIC_ENA : Enable Half Duplex Logic
39 
parameter ENABLE_SUP_ADDR       = 1,                    //  SUP_ADDR_ENA : Enable Supplemental Addresses
40 
parameter ENA_HASH              = 1,                    //  ENA_HASH Enable Hash Table
41 
parameter STAT_CNT_ENA          = 1,                    //  STAT_CNT_ENA Enable Statistic Counters
42 
parameter MDIO_CLK_DIV          = 40 ,                  //  Host Clock Division - MDC Generation
43 
parameter CORE_VERSION          = 16'h3,                //  ALTERA Core Version
44 
parameter CUST_VERSION          = 1 ,                   //  Customer Core Version
45 
parameter REDUCED_INTERFACE_ENA = 0,                    //  Enable the RGMII Interface
46 
parameter ENABLE_MDIO           = 1,                    //  Enable the MDIO Interface
47 
parameter ENABLE_MAGIC_DETECT   = 1,                    //  Enable magic packet detection
48 
parameter CRC32DWIDTH           = 4'b 1000,             //  input data width (informal, not for change)
49 
parameter CRC32GENDELAY         = 3'b 110,              //  when the data from the generator is valid
50 
parameter CRC32CHECK16BIT       = 1'b 0,                //  1 compare two times 16 bit of the CRC (adds one pipeline step)
51 
parameter CRC32S1L2_EXTERN      = 1'b0,                 //  false: merge enable
52 
parameter ENABLE_SHIFT16        = 0,                    //  Enable byte stuffing at packet header
53 
parameter ENABLE_MAC_FLOW_CTRL  = 1'b1,                 //  Option to enable flow control
54 
parameter ENABLE_MAC_TXADDR_SET = 1'b1,                 //  Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
55 
parameter ENABLE_MAC_RX_VLAN    = 1'b1,                 //  Option to enable VLAN tagged Ethernet frames on MAC RX data path
56 
parameter ENABLE_MAC_TX_VLAN    = 1'b1,                 //  Option to enable VLAN tagged Ethernet frames on MAC TX data path
57 
 
58 
parameter ENABLE_CLK_SHARING    = 0,                    //  Option to share clock for multiple channels (Clocks are rate-matched).
59 
parameter ENABLE_REG_SHARING    = 1,                    //  Option to share register space. Uses certain hard-coded values from input.
60 
parameter ENABLE_EXTENDED_STAT_REG = 0,                 //  Enable a few extended statistic registers
61 
parameter MAX_CHANNELS          = 1,                    //  The number of channels in Multi-TSE component
62 
parameter ENABLE_PKT_CLASS      = 1,                    //  Enable Packet Classification Av-ST Interface
63 
parameter ENABLE_RX_FIFO_STATUS = 1,                    //  Enable Receive FIFO Almost Full status interface
64 
parameter CHANNEL_WIDTH         = 1,                    //  The width of the channel interface
65 
parameter SYNCHRONIZER_DEPTH    = 3,                    //  Number of synchronizer
66 
 
67 
 
68 
// Internal parameters
69 
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
70 
                       (MAX_CHANNELS > 8)? 12 :
71 
                       (MAX_CHANNELS > 4)? 11 :
72 
                       (MAX_CHANNELS > 2)? 10 :
73 
                       (MAX_CHANNELS > 1)? 9 : 8
74 
 
75 
)
76 
 
77 
 
78 
 
79 
(
80 
 
81 
        // RESET / MAC REG IF / MDIO
82 
        input wire   reset,                      //  Asynchronous Reset - clk Domain
83 
        input wire   clk,                        //  25MHz Host Interface Clock
84 
        input wire   read,                       //  Register Read Strobe
85 
        input wire   write,                      //  Register Write Strobe
86 
        input wire   [ADDR_WIDTH-1:0] address,   //  Register Address
87 
        input wire   [31:0] writedata,           //  Write Data for Host Bus
88 
        output wire  [31:0] readdata,            //  Read Data to Host Bus
89 
        output wire  waitrequest,                //  Interface Busy
90 
        output wire  mdc,                        //  2.5MHz Inteface
91 
        input wire   mdio_in,                    //  MDIO Input
92 
        output wire  mdio_out,                   //  MDIO Output
93 
        output wire  mdio_oen,                   //  MDIO Output Enable
94 
 
95 
        // SHARED CLK SIGNALS
96 
        input wire   rx_clk,                     //  Receive Clock
97 
        input wire   tx_clk,                     //  Transmit Clock
98 
    output wire  mac_rx_clk,                 //  Av-ST Receive Clock
99 
        output wire  mac_tx_clk,                 //  Av-ST Transmit Clock
100 
 
101 
    // SHARED RX STATUS
102 
    input wire   rx_afull_clk,                             //  Almost full clock
103 
        input wire   [1:0] rx_afull_data,                      //  Almost full data
104 
        input wire   rx_afull_valid,                           //  Almost full valid
105 
        input wire   [CHANNEL_WIDTH-1:0] rx_afull_channel,     //  Almost full channel
106 
 
107 
 
108 
    // CHANNEL 0
109 
 
110 
        // GMII / MII / RGMII SIGNALS
111 
        input wire   m_rx_crs_0,               //  Carrier Sense
112 
        input wire   m_rx_col_0,               //  Collition
113 
        input wire   rx_clk_0,                 //  Receive Clock
114 
        input wire   tx_clk_0,                 //  Transmit Clock
115 
        input wire   [7:0] gm_rx_d_0,          //  GMII Receive Data
116 
        input wire   gm_rx_dv_0,               //  GMII Receive Frame Enable
117 
        input wire   gm_rx_err_0,              //  GMII Receive Frame Error
118 
        output wire  [7:0] gm_tx_d_0,          //  GMII Transmit Data
119 
        output wire  gm_tx_en_0,               //  GMII Transmit Frame Enable
120 
        output wire  gm_tx_err_0,              //  GMII Transmit Frame Error
121 
        input wire   [3:0] m_rx_d_0,           //  MII Receive Data
122 
        input wire   m_rx_en_0,                //  MII Receive Frame Enable
123 
        input wire   m_rx_err_0,               //  MII Receive Drame Error
124 
        output wire  [3:0] m_tx_d_0,           //  MII Transmit Data
125 
        output wire  m_tx_en_0,                //  MII Transmit Frame Enable
126 
        output wire  m_tx_err_0,               //  MII Transmit Frame Error
127 
        output wire  tx_control_0,
128 
        output wire  [3:0] rgmii_out_0,
129 
        input wire   [3:0] rgmii_in_0,
130 
        input wire   rx_control_0,
131 
        output wire  eth_mode_0,               //  Ethernet Mode
132 
        output wire  ena_10_0,                 //  Enable 10Mbps Mode
133 
        input wire   set_1000_0,               //  Gigabit Mode Enable
134 
        input wire   set_10_0,                 //  10Mbps Mode Enable
135 
 
136 
        // AV-ST TX & RX
137 
        output wire  mac_rx_clk_0,             //  Av-ST Receive Clock
138 
        output wire  mac_tx_clk_0,             //  Av-ST Transmit Clock
139 
        output wire  data_rx_sop_0,            //  Start of Packet
140 
        output wire  data_rx_eop_0,            //  End of Packet
141 
        output wire  [7:0] data_rx_data_0,     //  Data from FIFO
142 
        output wire  [4:0] data_rx_error_0,    //  Receive packet error
143 
        output wire  data_rx_valid_0,          //  Data Receive FIFO Valid
144 
        input wire   data_rx_ready_0,          //  Data Receive Ready
145 
        output wire  [4:0] pkt_class_data_0,   //  Frame Type Indication
146 
        output wire  pkt_class_valid_0,        //  Frame Type Indication Valid
147 
        input wire   data_tx_error_0,          //  STATUS FIFO (Tx frame Error from Apps)
148 
        input wire   [7:0] data_tx_data_0,     //  Data from FIFO transmit
149 
        input wire   data_tx_valid_0,          //  Data FIFO transmit Empty
150 
        input wire   data_tx_sop_0,            //  Start of Packet
151 
        input wire   data_tx_eop_0,            //  END of Packet
152 
        output wire  data_tx_ready_0,          //  Data FIFO transmit Read Enable
153 
 
154 
        // STAND_ALONE CONDUITS
155 
        output wire  tx_ff_uflow_0,            //  TX FIFO underflow occured (Synchronous with tx_clk)
156 
        input wire   tx_crc_fwd_0,             //  Forward Current Frame with CRC from Application
157 
        input wire   xoff_gen_0,               //  Xoff Pause frame generate
158 
        input wire   xon_gen_0,                //  Xon Pause frame generate
159 
        input wire   magic_sleep_n_0,          //  Enable Sleep Mode
160 
        output wire  magic_wakeup_0,           //  Wake Up Request
161 
 
162 
 
163 
    // CHANNEL 1
164 
 
165 
        // GMII / MII / RGMII SIGNALS
166 
        input wire   m_rx_crs_1,               //  Carrier Sense
167 
        input wire   m_rx_col_1,               //  Collition
168 
        input wire   rx_clk_1,                 //  Receive Clock
169 
        input wire   tx_clk_1,                 //  Transmit Clock
170 
        input wire   [7:0] gm_rx_d_1,          //  GMII Receive Data
171 
        input wire   gm_rx_dv_1,               //  GMII Receive Frame Enable
172 
        input wire   gm_rx_err_1,              //  GMII Receive Frame Error
173 
        output wire  [7:0] gm_tx_d_1,          //  GMII Transmit Data
174 
        output wire  gm_tx_en_1,               //  GMII Transmit Frame Enable
175 
        output wire  gm_tx_err_1,              //  GMII Transmit Frame Error
176 
        input wire   [3:0] m_rx_d_1,           //  MII Receive Data
177 
        input wire   m_rx_en_1,                //  MII Receive Frame Enable
178 
        input wire   m_rx_err_1,               //  MII Receive Drame Error
179 
        output wire  [3:0] m_tx_d_1,           //  MII Transmit Data
180 
        output wire  m_tx_en_1,                //  MII Transmit Frame Enable
181 
        output wire  m_tx_err_1,               //  MII Transmit Frame Error
182 
        output wire  tx_control_1,
183 
        output wire  [3:0] rgmii_out_1,
184 
        input wire   [3:0] rgmii_in_1,
185 
        input wire   rx_control_1,
186 
        output wire  eth_mode_1,               //  Ethernet Mode
187 
        output wire  ena_10_1,                 //  Enable 10Mbps Mode
188 
        input wire   set_1000_1,               //  Gigabit Mode Enable
189 
        input wire   set_10_1,                 //  10Mbps Mode Enable
190 
 
191 
        // AV-ST TX & RX
192 
        output wire  mac_rx_clk_1,             //  Av-ST Receive Clock
193 
        output wire  mac_tx_clk_1,             //  Av-ST Transmit Clock
194 
        output wire  data_rx_sop_1,            //  Start of Packet
195 
        output wire  data_rx_eop_1,            //  End of Packet
196 
        output wire  [7:0] data_rx_data_1,     //  Data from FIFO
197 
        output wire  [4:0] data_rx_error_1,    //  Receive packet error
198 
        output wire  data_rx_valid_1,          //  Data Receive FIFO Valid
199 
        input wire   data_rx_ready_1,          //  Data Receive Ready
200 
        output wire  [4:0] pkt_class_data_1,   //  Frame Type Indication
201 
        output wire  pkt_class_valid_1,        //  Frame Type Indication Valid
202 
        input wire   data_tx_error_1,          //  STATUS FIFO (Tx frame Error from Apps)
203 
        input wire   [7:0] data_tx_data_1,     //  Data from FIFO transmit
204 
        input wire   data_tx_valid_1,          //  Data FIFO transmit Empty
205 
        input wire   data_tx_sop_1,            //  Start of Packet
206 
        input wire   data_tx_eop_1,            //  END of Packet
207 
        output wire  data_tx_ready_1,          //  Data FIFO transmit Read Enable
208 
 
209 
        // STAND_ALONE CONDUITS
210 
        output wire  tx_ff_uflow_1,            //  TX FIFO underflow occured (Synchronous with tx_clk)
211 
        input wire   tx_crc_fwd_1,             //  Forward Current Frame with CRC from Application
212 
        input wire   xoff_gen_1,               //  Xoff Pause frame generate
213 
        input wire   xon_gen_1,                //  Xon Pause frame generate
214 
        input wire   magic_sleep_n_1,          //  Enable Sleep Mode
215 
        output wire  magic_wakeup_1,           //  Wake Up Request
216 
 
217 
 
218 
    // CHANNEL 2
219 
 
220 
        // GMII / MII / RGMII SIGNALS
221 
        input wire   m_rx_crs_2,               //  Carrier Sense
222 
        input wire   m_rx_col_2,               //  Collition
223 
        input wire   rx_clk_2,                 //  Receive Clock
224 
        input wire   tx_clk_2,                 //  Transmit Clock
225 
        input wire   [7:0] gm_rx_d_2,          //  GMII Receive Data
226 
        input wire   gm_rx_dv_2,               //  GMII Receive Frame Enable
227 
        input wire   gm_rx_err_2,              //  GMII Receive Frame Error
228 
        output wire  [7:0] gm_tx_d_2,          //  GMII Transmit Data
229 
        output wire  gm_tx_en_2,               //  GMII Transmit Frame Enable
230 
        output wire  gm_tx_err_2,              //  GMII Transmit Frame Error
231 
        input wire   [3:0] m_rx_d_2,           //  MII Receive Data
232 
        input wire   m_rx_en_2,                //  MII Receive Frame Enable
233 
        input wire   m_rx_err_2,               //  MII Receive Drame Error
234 
        output wire  [3:0] m_tx_d_2,           //  MII Transmit Data
235 
        output wire  m_tx_en_2,                //  MII Transmit Frame Enable
236 
        output wire  m_tx_err_2,               //  MII Transmit Frame Error
237 
        output wire  tx_control_2,
238 
        output wire  [3:0] rgmii_out_2,
239 
        input wire   [3:0] rgmii_in_2,
240 
        input wire   rx_control_2,
241 
        output wire  eth_mode_2,               //  Ethernet Mode
242 
        output wire  ena_10_2,                 //  Enable 10Mbps Mode
243 
        input wire   set_1000_2,               //  Gigabit Mode Enable
244 
        input wire   set_10_2,                 //  10Mbps Mode Enable
245 
 
246 
        // AV-ST TX & RX
247 
        output wire  mac_rx_clk_2,             //  Av-ST Receive Clock
248 
        output wire  mac_tx_clk_2,             //  Av-ST Transmit Clock
249 
        output wire  data_rx_sop_2,            //  Start of Packet
250 
        output wire  data_rx_eop_2,            //  End of Packet
251 
        output wire  [7:0] data_rx_data_2,     //  Data from FIFO
252 
        output wire  [4:0] data_rx_error_2,    //  Receive packet error
253 
        output wire  data_rx_valid_2,          //  Data Receive FIFO Valid
254 
        input wire   data_rx_ready_2,          //  Data Receive Ready
255 
        output wire  [4:0] pkt_class_data_2,   //  Frame Type Indication
256 
        output wire  pkt_class_valid_2,        //  Frame Type Indication Valid
257 
        input wire   data_tx_error_2,          //  STATUS FIFO (Tx frame Error from Apps)
258 
        input wire   [7:0] data_tx_data_2,     //  Data from FIFO transmit
259 
        input wire   data_tx_valid_2,          //  Data FIFO transmit Empty
260 
        input wire   data_tx_sop_2,            //  Start of Packet
261 
        input wire   data_tx_eop_2,            //  END of Packet
262 
        output wire  data_tx_ready_2,          //  Data FIFO transmit Read Enable
263 
 
264 
        // STAND_ALONE CONDUITS
265 
        output wire  tx_ff_uflow_2,            //  TX FIFO underflow occured (Synchronous with tx_clk)
266 
        input wire   tx_crc_fwd_2,             //  Forward Current Frame with CRC from Application
267 
        input wire   xoff_gen_2,               //  Xoff Pause frame generate
268 
        input wire   xon_gen_2,                //  Xon Pause frame generate
269 
        input wire   magic_sleep_n_2,          //  Enable Sleep Mode
270 
        output wire  magic_wakeup_2,           //  Wake Up Request
271 
 
272 
 
273 
    // CHANNEL 3
274 
 
275 
        // GMII / MII / RGMII SIGNALS
276 
        input wire   m_rx_crs_3,               //  Carrier Sense
277 
        input wire   m_rx_col_3,               //  Collition
278 
        input wire   rx_clk_3,                 //  Receive Clock
279 
        input wire   tx_clk_3,                 //  Transmit Clock
280 
        input wire   [7:0] gm_rx_d_3,          //  GMII Receive Data
281 
        input wire   gm_rx_dv_3,               //  GMII Receive Frame Enable
282 
        input wire   gm_rx_err_3,              //  GMII Receive Frame Error
283 
        output wire  [7:0] gm_tx_d_3,          //  GMII Transmit Data
284 
        output wire  gm_tx_en_3,               //  GMII Transmit Frame Enable
285 
        output wire  gm_tx_err_3,              //  GMII Transmit Frame Error
286 
        input wire   [3:0] m_rx_d_3,           //  MII Receive Data
287 
        input wire   m_rx_en_3,                //  MII Receive Frame Enable
288 
        input wire   m_rx_err_3,               //  MII Receive Drame Error
289 
        output wire  [3:0] m_tx_d_3,           //  MII Transmit Data
290 
        output wire  m_tx_en_3,                //  MII Transmit Frame Enable
291 
        output wire  m_tx_err_3,               //  MII Transmit Frame Error
292 
        output wire  tx_control_3,
293 
        output wire  [3:0] rgmii_out_3,
294 
        input wire   [3:0] rgmii_in_3,
295 
        input wire   rx_control_3,
296 
        output wire  eth_mode_3,               //  Ethernet Mode
297 
        output wire  ena_10_3,                 //  Enable 10Mbps Mode
298 
        input wire   set_1000_3,               //  Gigabit Mode Enable
299 
        input wire   set_10_3,                 //  10Mbps Mode Enable
300 
 
301 
        // AV-ST TX & RX
302 
        output wire  mac_rx_clk_3,             //  Av-ST Receive Clock
303 
        output wire  mac_tx_clk_3,             //  Av-ST Transmit Clock
304 
        output wire  data_rx_sop_3,            //  Start of Packet
305 
        output wire  data_rx_eop_3,            //  End of Packet
306 
        output wire  [7:0] data_rx_data_3,     //  Data from FIFO
307 
        output wire  [4:0] data_rx_error_3,    //  Receive packet error
308 
        output wire  data_rx_valid_3,          //  Data Receive FIFO Valid
309 
        input wire   data_rx_ready_3,          //  Data Receive Ready
310 
        output wire  [4:0] pkt_class_data_3,   //  Frame Type Indication
311 
        output wire  pkt_class_valid_3,        //  Frame Type Indication Valid
312 
        input wire   data_tx_error_3,          //  STATUS FIFO (Tx frame Error from Apps)
313 
        input wire   [7:0] data_tx_data_3,     //  Data from FIFO transmit
314 
        input wire   data_tx_valid_3,          //  Data FIFO transmit Empty
315 
        input wire   data_tx_sop_3,            //  Start of Packet
316 
        input wire   data_tx_eop_3,            //  END of Packet
317 
        output wire  data_tx_ready_3,          //  Data FIFO transmit Read Enable
318 
 
319 
        // STAND_ALONE CONDUITS
320 
        output wire  tx_ff_uflow_3,            //  TX FIFO underflow occured (Synchronous with tx_clk)
321 
        input wire   tx_crc_fwd_3,             //  Forward Current Frame with CRC from Application
322 
        input wire   xoff_gen_3,               //  Xoff Pause frame generate
323 
        input wire   xon_gen_3,                //  Xon Pause frame generate
324 
        input wire   magic_sleep_n_3,          //  Enable Sleep Mode
325 
        output wire  magic_wakeup_3,           //  Wake Up Request
326 
 
327 
 
328 
    // CHANNEL 4
329 
 
330 
        // GMII / MII / RGMII SIGNALS
331 
        input wire   m_rx_crs_4,               //  Carrier Sense
332 
        input wire   m_rx_col_4,               //  Collition
333 
        input wire   rx_clk_4,                 //  Receive Clock
334 
        input wire   tx_clk_4,                 //  Transmit Clock
335 
        input wire   [7:0] gm_rx_d_4,          //  GMII Receive Data
336 
        input wire   gm_rx_dv_4,               //  GMII Receive Frame Enable
337 
        input wire   gm_rx_err_4,              //  GMII Receive Frame Error
338 
        output wire  [7:0] gm_tx_d_4,          //  GMII Transmit Data
339 
        output wire  gm_tx_en_4,               //  GMII Transmit Frame Enable
340 
        output wire  gm_tx_err_4,              //  GMII Transmit Frame Error
341 
        input wire   [3:0] m_rx_d_4,           //  MII Receive Data
342 
        input wire   m_rx_en_4,                //  MII Receive Frame Enable
343 
        input wire   m_rx_err_4,               //  MII Receive Drame Error
344 
        output wire  [3:0] m_tx_d_4,           //  MII Transmit Data
345 
        output wire  m_tx_en_4,                //  MII Transmit Frame Enable
346 
        output wire  m_tx_err_4,               //  MII Transmit Frame Error
347 
        output wire  tx_control_4,
348 
        output wire  [3:0] rgmii_out_4,
349 
        input wire   [3:0] rgmii_in_4,
350 
        input wire   rx_control_4,
351 
        output wire  eth_mode_4,               //  Ethernet Mode
352 
        output wire  ena_10_4,                 //  Enable 10Mbps Mode
353 
        input wire   set_1000_4,               //  Gigabit Mode Enable
354 
        input wire   set_10_4,                 //  10Mbps Mode Enable
355 
 
356 
        // AV-ST TX & RX
357 
        output wire  mac_rx_clk_4,             //  Av-ST Receive Clock
358 
        output wire  mac_tx_clk_4,             //  Av-ST Transmit Clock
359 
        output wire  data_rx_sop_4,            //  Start of Packet
360 
        output wire  data_rx_eop_4,            //  End of Packet
361 
        output wire  [7:0] data_rx_data_4,     //  Data from FIFO
362 
        output wire  [4:0] data_rx_error_4,    //  Receive packet error
363 
        output wire  data_rx_valid_4,          //  Data Receive FIFO Valid
364 
        input wire   data_rx_ready_4,          //  Data Receive Ready
365 
        output wire  [4:0] pkt_class_data_4,   //  Frame Type Indication
366 
        output wire  pkt_class_valid_4,        //  Frame Type Indication Valid
367 
        input wire   data_tx_error_4,          //  STATUS FIFO (Tx frame Error from Apps)
368 
        input wire   [7:0] data_tx_data_4,     //  Data from FIFO transmit
369 
        input wire   data_tx_valid_4,          //  Data FIFO transmit Empty
370 
        input wire   data_tx_sop_4,            //  Start of Packet
371 
        input wire   data_tx_eop_4,            //  END of Packet
372 
        output wire  data_tx_ready_4,          //  Data FIFO transmit Read Enable
373 
 
374 
        // STAND_ALONE CONDUITS
375 
        output wire  tx_ff_uflow_4,            //  TX FIFO underflow occured (Synchronous with tx_clk)
376 
        input wire   tx_crc_fwd_4,             //  Forward Current Frame with CRC from Application
377 
        input wire   xoff_gen_4,               //  Xoff Pause frame generate
378 
        input wire   xon_gen_4,                //  Xon Pause frame generate
379 
        input wire   magic_sleep_n_4,          //  Enable Sleep Mode
380 
        output wire  magic_wakeup_4,           //  Wake Up Request
381 
 
382 
 
383 
    // CHANNEL 5
384 
 
385 
        // GMII / MII / RGMII SIGNALS
386 
        input wire   m_rx_crs_5,               //  Carrier Sense
387 
        input wire   m_rx_col_5,               //  Collition
388 
        input wire   rx_clk_5,                 //  Receive Clock
389 
        input wire   tx_clk_5,                 //  Transmit Clock
390 
        input wire   [7:0] gm_rx_d_5,          //  GMII Receive Data
391 
        input wire   gm_rx_dv_5,               //  GMII Receive Frame Enable
392 
        input wire   gm_rx_err_5,              //  GMII Receive Frame Error
393 
        output wire  [7:0] gm_tx_d_5,          //  GMII Transmit Data
394 
        output wire  gm_tx_en_5,               //  GMII Transmit Frame Enable
395 
        output wire  gm_tx_err_5,              //  GMII Transmit Frame Error
396 
        input wire   [3:0] m_rx_d_5,           //  MII Receive Data
397 
        input wire   m_rx_en_5,                //  MII Receive Frame Enable
398 
        input wire   m_rx_err_5,               //  MII Receive Drame Error
399 
        output wire  [3:0] m_tx_d_5,           //  MII Transmit Data
400 
        output wire  m_tx_en_5,                //  MII Transmit Frame Enable
401 
        output wire  m_tx_err_5,               //  MII Transmit Frame Error
402 
        output wire  tx_control_5,
403 
        output wire  [3:0] rgmii_out_5,
404 
        input wire   [3:0] rgmii_in_5,
405 
        input wire   rx_control_5,
406 
        output wire  eth_mode_5,               //  Ethernet Mode
407 
        output wire  ena_10_5,                 //  Enable 10Mbps Mode
408 
        input wire   set_1000_5,               //  Gigabit Mode Enable
409 
        input wire   set_10_5,                 //  10Mbps Mode Enable
410 
 
411 
        // AV-ST TX & RX
412 
        output wire  mac_rx_clk_5,             //  Av-ST Receive Clock
413 
        output wire  mac_tx_clk_5,             //  Av-ST Transmit Clock
414 
        output wire  data_rx_sop_5,            //  Start of Packet
415 
        output wire  data_rx_eop_5,            //  End of Packet
416 
        output wire  [7:0] data_rx_data_5,     //  Data from FIFO
417 
        output wire  [4:0] data_rx_error_5,    //  Receive packet error
418 
        output wire  data_rx_valid_5,          //  Data Receive FIFO Valid
419 
        input wire   data_rx_ready_5,          //  Data Receive Ready
420 
        output wire  [4:0] pkt_class_data_5,   //  Frame Type Indication
421 
        output wire  pkt_class_valid_5,        //  Frame Type Indication Valid
422 
        input wire   data_tx_error_5,          //  STATUS FIFO (Tx frame Error from Apps)
423 
        input wire   [7:0] data_tx_data_5,     //  Data from FIFO transmit
424 
        input wire   data_tx_valid_5,          //  Data FIFO transmit Empty
425 
        input wire   data_tx_sop_5,            //  Start of Packet
426 
        input wire   data_tx_eop_5,            //  END of Packet
427 
        output wire  data_tx_ready_5,          //  Data FIFO transmit Read Enable
428 
 
429 
        // STAND_ALONE CONDUITS
430 
        output wire  tx_ff_uflow_5,            //  TX FIFO underflow occured (Synchronous with tx_clk)
431 
        input wire   tx_crc_fwd_5,             //  Forward Current Frame with CRC from Application
432 
        input wire   xoff_gen_5,               //  Xoff Pause frame generate
433 
        input wire   xon_gen_5,                //  Xon Pause frame generate
434 
        input wire   magic_sleep_n_5,          //  Enable Sleep Mode
435 
        output wire  magic_wakeup_5,           //  Wake Up Request
436 
 
437 
 
438 
    // CHANNEL 6
439 
 
440 
        // GMII / MII / RGMII SIGNALS
441 
        input wire   m_rx_crs_6,               //  Carrier Sense
442 
        input wire   m_rx_col_6,               //  Collition
443 
        input wire   rx_clk_6,                 //  Receive Clock
444 
        input wire   tx_clk_6,                 //  Transmit Clock
445 
        input wire   [7:0] gm_rx_d_6,          //  GMII Receive Data
446 
        input wire   gm_rx_dv_6,               //  GMII Receive Frame Enable
447 
        input wire   gm_rx_err_6,              //  GMII Receive Frame Error
448 
        output wire  [7:0] gm_tx_d_6,          //  GMII Transmit Data
449 
        output wire  gm_tx_en_6,               //  GMII Transmit Frame Enable
450 
        output wire  gm_tx_err_6,              //  GMII Transmit Frame Error
451 
        input wire   [3:0] m_rx_d_6,           //  MII Receive Data
452 
        input wire   m_rx_en_6,                //  MII Receive Frame Enable
453 
        input wire   m_rx_err_6,               //  MII Receive Drame Error
454 
        output wire  [3:0] m_tx_d_6,           //  MII Transmit Data
455 
        output wire  m_tx_en_6,                //  MII Transmit Frame Enable
456 
        output wire  m_tx_err_6,               //  MII Transmit Frame Error
457 
        output wire  tx_control_6,
458 
        output wire  [3:0] rgmii_out_6,
459 
        input wire   [3:0] rgmii_in_6,
460 
        input wire   rx_control_6,
461 
        output wire  eth_mode_6,               //  Ethernet Mode
462 
        output wire  ena_10_6,                 //  Enable 10Mbps Mode
463 
        input wire   set_1000_6,               //  Gigabit Mode Enable
464 
        input wire   set_10_6,                 //  10Mbps Mode Enable
465 
 
466 
        // AV-ST TX & RX
467 
        output wire  mac_rx_clk_6,             //  Av-ST Receive Clock
468 
        output wire  mac_tx_clk_6,             //  Av-ST Transmit Clock
469 
        output wire  data_rx_sop_6,            //  Start of Packet
470 
        output wire  data_rx_eop_6,            //  End of Packet
471 
        output wire  [7:0] data_rx_data_6,     //  Data from FIFO
472 
        output wire  [4:0] data_rx_error_6,    //  Receive packet error
473 
        output wire  data_rx_valid_6,          //  Data Receive FIFO Valid
474 
        input wire   data_rx_ready_6,          //  Data Receive Ready
475 
        output wire  [4:0] pkt_class_data_6,   //  Frame Type Indication
476 
        output wire  pkt_class_valid_6,        //  Frame Type Indication Valid
477 
        input wire   data_tx_error_6,          //  STATUS FIFO (Tx frame Error from Apps)
478 
        input wire   [7:0] data_tx_data_6,     //  Data from FIFO transmit
479 
        input wire   data_tx_valid_6,          //  Data FIFO transmit Empty
480 
        input wire   data_tx_sop_6,            //  Start of Packet
481 
        input wire   data_tx_eop_6,            //  END of Packet
482 
        output wire  data_tx_ready_6,          //  Data FIFO transmit Read Enable
483 
 
484 
        // STAND_ALONE CONDUITS
485 
        output wire  tx_ff_uflow_6,            //  TX FIFO underflow occured (Synchronous with tx_clk)
486 
        input wire   tx_crc_fwd_6,             //  Forward Current Frame with CRC from Application
487 
        input wire   xoff_gen_6,               //  Xoff Pause frame generate
488 
        input wire   xon_gen_6,                //  Xon Pause frame generate
489 
        input wire   magic_sleep_n_6,          //  Enable Sleep Mode
490 
        output wire  magic_wakeup_6,           //  Wake Up Request
491 
 
492 
 
493 
    // CHANNEL 7
494 
 
495 
        // GMII / MII / RGMII SIGNALS
496 
        input wire   m_rx_crs_7,               //  Carrier Sense
497 
        input wire   m_rx_col_7,               //  Collition
498 
        input wire   rx_clk_7,                 //  Receive Clock
499 
        input wire   tx_clk_7,                 //  Transmit Clock
500 
        input wire   [7:0] gm_rx_d_7,          //  GMII Receive Data
501 
        input wire   gm_rx_dv_7,               //  GMII Receive Frame Enable
502 
        input wire   gm_rx_err_7,              //  GMII Receive Frame Error
503 
        output wire  [7:0] gm_tx_d_7,          //  GMII Transmit Data
504 
        output wire  gm_tx_en_7,               //  GMII Transmit Frame Enable
505 
        output wire  gm_tx_err_7,              //  GMII Transmit Frame Error
506 
        input wire   [3:0] m_rx_d_7,           //  MII Receive Data
507 
        input wire   m_rx_en_7,                //  MII Receive Frame Enable
508 
        input wire   m_rx_err_7,               //  MII Receive Drame Error
509 
        output wire  [3:0] m_tx_d_7,           //  MII Transmit Data
510 
        output wire  m_tx_en_7,                //  MII Transmit Frame Enable
511 
        output wire  m_tx_err_7,               //  MII Transmit Frame Error
512 
        output wire  tx_control_7,
513 
        output wire  [3:0] rgmii_out_7,
514 
        input wire   [3:0] rgmii_in_7,
515 
        input wire   rx_control_7,
516 
        output wire  eth_mode_7,               //  Ethernet Mode
517 
        output wire  ena_10_7,                 //  Enable 10Mbps Mode
518 
        input wire   set_1000_7,               //  Gigabit Mode Enable
519 
        input wire   set_10_7,                 //  10Mbps Mode Enable
520 
 
521 
        // AV-ST TX & RX
522 
        output wire  mac_rx_clk_7,             //  Av-ST Receive Clock
523 
        output wire  mac_tx_clk_7,             //  Av-ST Transmit Clock
524 
        output wire  data_rx_sop_7,            //  Start of Packet
525 
        output wire  data_rx_eop_7,            //  End of Packet
526 
        output wire  [7:0] data_rx_data_7,     //  Data from FIFO
527 
        output wire  [4:0] data_rx_error_7,    //  Receive packet error
528 
        output wire  data_rx_valid_7,          //  Data Receive FIFO Valid
529 
        input wire   data_rx_ready_7,          //  Data Receive Ready
530 
        output wire  [4:0] pkt_class_data_7,   //  Frame Type Indication
531 
        output wire  pkt_class_valid_7,        //  Frame Type Indication Valid
532 
        input wire   data_tx_error_7,          //  STATUS FIFO (Tx frame Error from Apps)
533 
        input wire   [7:0] data_tx_data_7,     //  Data from FIFO transmit
534 
        input wire   data_tx_valid_7,          //  Data FIFO transmit Empty
535 
        input wire   data_tx_sop_7,            //  Start of Packet
536 
        input wire   data_tx_eop_7,            //  END of Packet
537 
        output wire  data_tx_ready_7,          //  Data FIFO transmit Read Enable
538 
 
539 
        // STAND_ALONE CONDUITS
540 
        output wire  tx_ff_uflow_7,            //  TX FIFO underflow occured (Synchronous with tx_clk)
541 
        input wire   tx_crc_fwd_7,             //  Forward Current Frame with CRC from Application
542 
        input wire   xoff_gen_7,               //  Xoff Pause frame generate
543 
        input wire   xon_gen_7,                //  Xon Pause frame generate
544 
        input wire   magic_sleep_n_7,          //  Enable Sleep Mode
545 
        output wire  magic_wakeup_7,           //  Wake Up Request
546 
 
547 
 
548 
    // CHANNEL 8
549 
 
550 
        // GMII / MII / RGMII SIGNALS
551 
        input wire   m_rx_crs_8,               //  Carrier Sense
552 
        input wire   m_rx_col_8,               //  Collition
553 
        input wire   rx_clk_8,                 //  Receive Clock
554 
        input wire   tx_clk_8,                 //  Transmit Clock
555 
        input wire   [7:0] gm_rx_d_8,          //  GMII Receive Data
556 
        input wire   gm_rx_dv_8,               //  GMII Receive Frame Enable
557 
        input wire   gm_rx_err_8,              //  GMII Receive Frame Error
558 
        output wire  [7:0] gm_tx_d_8,          //  GMII Transmit Data
559 
        output wire  gm_tx_en_8,               //  GMII Transmit Frame Enable
560 
        output wire  gm_tx_err_8,              //  GMII Transmit Frame Error
561 
        input wire   [3:0] m_rx_d_8,           //  MII Receive Data
562 
        input wire   m_rx_en_8,                //  MII Receive Frame Enable
563 
        input wire   m_rx_err_8,               //  MII Receive Drame Error
564 
        output wire  [3:0] m_tx_d_8,           //  MII Transmit Data
565 
        output wire  m_tx_en_8,                //  MII Transmit Frame Enable
566 
        output wire  m_tx_err_8,               //  MII Transmit Frame Error
567 
        output wire  tx_control_8,
568 
        output wire  [3:0] rgmii_out_8,
569 
        input wire   [3:0] rgmii_in_8,
570 
        input wire   rx_control_8,
571 
        output wire  eth_mode_8,               //  Ethernet Mode
572 
        output wire  ena_10_8,                 //  Enable 10Mbps Mode
573 
        input wire   set_1000_8,               //  Gigabit Mode Enable
574 
        input wire   set_10_8,                 //  10Mbps Mode Enable
575 
 
576 
        // AV-ST TX & RX
577 
        output wire  mac_rx_clk_8,             //  Av-ST Receive Clock
578 
        output wire  mac_tx_clk_8,             //  Av-ST Transmit Clock
579 
        output wire  data_rx_sop_8,            //  Start of Packet
580 
        output wire  data_rx_eop_8,            //  End of Packet
581 
        output wire  [7:0] data_rx_data_8,     //  Data from FIFO
582 
        output wire  [4:0] data_rx_error_8,    //  Receive packet error
583 
        output wire  data_rx_valid_8,          //  Data Receive FIFO Valid
584 
        input wire   data_rx_ready_8,          //  Data Receive Ready
585 
        output wire  [4:0] pkt_class_data_8,   //  Frame Type Indication
586 
        output wire  pkt_class_valid_8,        //  Frame Type Indication Valid
587 
        input wire   data_tx_error_8,          //  STATUS FIFO (Tx frame Error from Apps)
588 
        input wire   [7:0] data_tx_data_8,     //  Data from FIFO transmit
589 
        input wire   data_tx_valid_8,          //  Data FIFO transmit Empty
590 
        input wire   data_tx_sop_8,            //  Start of Packet
591 
        input wire   data_tx_eop_8,            //  END of Packet
592 
        output wire  data_tx_ready_8,          //  Data FIFO transmit Read Enable
593 
 
594 
        // STAND_ALONE CONDUITS
595 
        output wire  tx_ff_uflow_8,            //  TX FIFO underflow occured (Synchronous with tx_clk)
596 
        input wire   tx_crc_fwd_8,             //  Forward Current Frame with CRC from Application
597 
        input wire   xoff_gen_8,               //  Xoff Pause frame generate
598 
        input wire   xon_gen_8,                //  Xon Pause frame generate
599 
        input wire   magic_sleep_n_8,          //  Enable Sleep Mode
600 
        output wire  magic_wakeup_8,           //  Wake Up Request
601 
 
602 
 
603 
    // CHANNEL 9
604 
 
605 
        // GMII / MII / RGMII SIGNALS
606 
        input wire   m_rx_crs_9,               //  Carrier Sense
607 
        input wire   m_rx_col_9,               //  Collition
608 
        input wire   rx_clk_9,                 //  Receive Clock
609 
        input wire   tx_clk_9,                 //  Transmit Clock
610 
        input wire   [7:0] gm_rx_d_9,          //  GMII Receive Data
611 
        input wire   gm_rx_dv_9,               //  GMII Receive Frame Enable
612 
        input wire   gm_rx_err_9,              //  GMII Receive Frame Error
613 
        output wire  [7:0] gm_tx_d_9,          //  GMII Transmit Data
614 
        output wire  gm_tx_en_9,               //  GMII Transmit Frame Enable
615 
        output wire  gm_tx_err_9,              //  GMII Transmit Frame Error
616 
        input wire   [3:0] m_rx_d_9,           //  MII Receive Data
617 
        input wire   m_rx_en_9,                //  MII Receive Frame Enable
618 
        input wire   m_rx_err_9,               //  MII Receive Drame Error
619 
        output wire  [3:0] m_tx_d_9,           //  MII Transmit Data
620 
        output wire  m_tx_en_9,                //  MII Transmit Frame Enable
621 
        output wire  m_tx_err_9,               //  MII Transmit Frame Error
622 
        output wire  tx_control_9,
623 
        output wire  [3:0] rgmii_out_9,
624 
        input wire   [3:0] rgmii_in_9,
625 
        input wire   rx_control_9,
626 
        output wire  eth_mode_9,               //  Ethernet Mode
627 
        output wire  ena_10_9,                 //  Enable 10Mbps Mode
628 
        input wire   set_1000_9,               //  Gigabit Mode Enable
629 
        input wire   set_10_9,                 //  10Mbps Mode Enable
630 
 
631 
        // AV-ST TX & RX
632 
        output wire  mac_rx_clk_9,             //  Av-ST Receive Clock
633 
        output wire  mac_tx_clk_9,             //  Av-ST Transmit Clock
634 
        output wire  data_rx_sop_9,            //  Start of Packet
635 
        output wire  data_rx_eop_9,            //  End of Packet
636 
        output wire  [7:0] data_rx_data_9,     //  Data from FIFO
637 
        output wire  [4:0] data_rx_error_9,    //  Receive packet error
638 
        output wire  data_rx_valid_9,          //  Data Receive FIFO Valid
639 
        input wire   data_rx_ready_9,          //  Data Receive Ready
640 
        output wire  [4:0] pkt_class_data_9,   //  Frame Type Indication
641 
        output wire  pkt_class_valid_9,        //  Frame Type Indication Valid
642 
        input wire   data_tx_error_9,          //  STATUS FIFO (Tx frame Error from Apps)
643 
        input wire   [7:0] data_tx_data_9,     //  Data from FIFO transmit
644 
        input wire   data_tx_valid_9,          //  Data FIFO transmit Empty
645 
        input wire   data_tx_sop_9,            //  Start of Packet
646 
        input wire   data_tx_eop_9,            //  END of Packet
647 
        output wire  data_tx_ready_9,          //  Data FIFO transmit Read Enable
648 
 
649 
        // STAND_ALONE CONDUITS
650 
        output wire  tx_ff_uflow_9,            //  TX FIFO underflow occured (Synchronous with tx_clk)
651 
        input wire   tx_crc_fwd_9,             //  Forward Current Frame with CRC from Application
652 
        input wire   xoff_gen_9,               //  Xoff Pause frame generate
653 
        input wire   xon_gen_9,                //  Xon Pause frame generate
654 
        input wire   magic_sleep_n_9,          //  Enable Sleep Mode
655 
        output wire  magic_wakeup_9,           //  Wake Up Request
656 
 
657 
 
658 
    // CHANNEL 10
659 
 
660 
        // GMII / MII / RGMII SIGNALS
661 
        input wire   m_rx_crs_10,               //  Carrier Sense
662 
        input wire   m_rx_col_10,               //  Collition
663 
        input wire   rx_clk_10,                 //  Receive Clock
664 
        input wire   tx_clk_10,                 //  Transmit Clock
665 
        input wire   [7:0] gm_rx_d_10,          //  GMII Receive Data
666 
        input wire   gm_rx_dv_10,               //  GMII Receive Frame Enable
667 
        input wire   gm_rx_err_10,              //  GMII Receive Frame Error
668 
        output wire  [7:0] gm_tx_d_10,          //  GMII Transmit Data
669 
        output wire  gm_tx_en_10,               //  GMII Transmit Frame Enable
670 
        output wire  gm_tx_err_10,              //  GMII Transmit Frame Error
671 
        input wire   [3:0] m_rx_d_10,           //  MII Receive Data
672 
        input wire   m_rx_en_10,                //  MII Receive Frame Enable
673 
        input wire   m_rx_err_10,               //  MII Receive Drame Error
674 
        output wire  [3:0] m_tx_d_10,           //  MII Transmit Data
675 
        output wire  m_tx_en_10,                //  MII Transmit Frame Enable
676 
        output wire  m_tx_err_10,               //  MII Transmit Frame Error
677 
        output wire  tx_control_10,
678 
        output wire  [3:0] rgmii_out_10,
679 
        input wire   [3:0] rgmii_in_10,
680 
        input wire   rx_control_10,
681 
        output wire  eth_mode_10,               //  Ethernet Mode
682 
        output wire  ena_10_10,                 //  Enable 10Mbps Mode
683 
        input wire   set_1000_10,               //  Gigabit Mode Enable
684 
        input wire   set_10_10,                 //  10Mbps Mode Enable
685 
 
686 
        // AV-ST TX & RX
687 
        output wire  mac_rx_clk_10,             //  Av-ST Receive Clock
688 
        output wire  mac_tx_clk_10,             //  Av-ST Transmit Clock
689 
        output wire  data_rx_sop_10,            //  Start of Packet
690 
        output wire  data_rx_eop_10,            //  End of Packet
691 
        output wire  [7:0] data_rx_data_10,     //  Data from FIFO
692 
        output wire  [4:0] data_rx_error_10,    //  Receive packet error
693 
        output wire  data_rx_valid_10,          //  Data Receive FIFO Valid
694 
        input wire   data_rx_ready_10,          //  Data Receive Ready
695 
        output wire  [4:0] pkt_class_data_10,   //  Frame Type Indication
696 
        output wire  pkt_class_valid_10,        //  Frame Type Indication Valid
697 
        input wire   data_tx_error_10,          //  STATUS FIFO (Tx frame Error from Apps)
698 
        input wire   [7:0] data_tx_data_10,     //  Data from FIFO transmit
699 
        input wire   data_tx_valid_10,          //  Data FIFO transmit Empty
700 
        input wire   data_tx_sop_10,            //  Start of Packet
701 
        input wire   data_tx_eop_10,            //  END of Packet
702 
        output wire  data_tx_ready_10,          //  Data FIFO transmit Read Enable
703 
 
704 
        // STAND_ALONE CONDUITS
705 
        output wire  tx_ff_uflow_10,            //  TX FIFO underflow occured (Synchronous with tx_clk)
706 
        input wire   tx_crc_fwd_10,             //  Forward Current Frame with CRC from Application
707 
        input wire   xoff_gen_10,               //  Xoff Pause frame generate
708 
        input wire   xon_gen_10,                //  Xon Pause frame generate
709 
        input wire   magic_sleep_n_10,          //  Enable Sleep Mode
710 
        output wire  magic_wakeup_10,           //  Wake Up Request
711 
 
712 
 
713 
    // CHANNEL 11
714 
 
715 
        // GMII / MII / RGMII SIGNALS
716 
        input wire   m_rx_crs_11,               //  Carrier Sense
717 
        input wire   m_rx_col_11,               //  Collition
718 
        input wire   rx_clk_11,                 //  Receive Clock
719 
        input wire   tx_clk_11,                 //  Transmit Clock
720 
        input wire   [7:0] gm_rx_d_11,          //  GMII Receive Data
721 
        input wire   gm_rx_dv_11,               //  GMII Receive Frame Enable
722 
        input wire   gm_rx_err_11,              //  GMII Receive Frame Error
723 
        output wire  [7:0] gm_tx_d_11,          //  GMII Transmit Data
724 
        output wire  gm_tx_en_11,               //  GMII Transmit Frame Enable
725 
        output wire  gm_tx_err_11,              //  GMII Transmit Frame Error
726 
        input wire   [3:0] m_rx_d_11,           //  MII Receive Data
727 
        input wire   m_rx_en_11,                //  MII Receive Frame Enable
728 
        input wire   m_rx_err_11,               //  MII Receive Drame Error
729 
        output wire  [3:0] m_tx_d_11,           //  MII Transmit Data
730 
        output wire  m_tx_en_11,                //  MII Transmit Frame Enable
731 
        output wire  m_tx_err_11,               //  MII Transmit Frame Error
732 
        output wire  tx_control_11,
733 
        output wire  [3:0] rgmii_out_11,
734 
        input wire   [3:0] rgmii_in_11,
735 
        input wire   rx_control_11,
736 
        output wire  eth_mode_11,               //  Ethernet Mode
737 
        output wire  ena_10_11,                 //  Enable 10Mbps Mode
738 
        input wire   set_1000_11,               //  Gigabit Mode Enable
739 
        input wire   set_10_11,                 //  10Mbps Mode Enable
740 
 
741 
        // AV-ST TX & RX
742 
        output wire  mac_rx_clk_11,             //  Av-ST Receive Clock
743 
        output wire  mac_tx_clk_11,             //  Av-ST Transmit Clock
744 
        output wire  data_rx_sop_11,            //  Start of Packet
745 
        output wire  data_rx_eop_11,            //  End of Packet
746 
        output wire  [7:0] data_rx_data_11,     //  Data from FIFO
747 
        output wire  [4:0] data_rx_error_11,    //  Receive packet error
748 
        output wire  data_rx_valid_11,          //  Data Receive FIFO Valid
749 
        input wire   data_rx_ready_11,          //  Data Receive Ready
750 
        output wire  [4:0] pkt_class_data_11,   //  Frame Type Indication
751 
        output wire  pkt_class_valid_11,        //  Frame Type Indication Valid
752 
        input wire   data_tx_error_11,          //  STATUS FIFO (Tx frame Error from Apps)
753 
        input wire   [7:0] data_tx_data_11,     //  Data from FIFO transmit
754 
        input wire   data_tx_valid_11,          //  Data FIFO transmit Empty
755 
        input wire   data_tx_sop_11,            //  Start of Packet
756 
        input wire   data_tx_eop_11,            //  END of Packet
757 
        output wire  data_tx_ready_11,          //  Data FIFO transmit Read Enable
758 
 
759 
        // STAND_ALONE CONDUITS
760 
        output wire  tx_ff_uflow_11,            //  TX FIFO underflow occured (Synchronous with tx_clk)
761 
        input wire   tx_crc_fwd_11,             //  Forward Current Frame with CRC from Application
762 
        input wire   xoff_gen_11,               //  Xoff Pause frame generate
763 
        input wire   xon_gen_11,                //  Xon Pause frame generate
764 
        input wire   magic_sleep_n_11,          //  Enable Sleep Mode
765 
        output wire  magic_wakeup_11,           //  Wake Up Request
766 
 
767 
 
768 
    // CHANNEL 12
769 
 
770 
        // GMII / MII / RGMII SIGNALS
771 
        input wire   m_rx_crs_12,               //  Carrier Sense
772 
        input wire   m_rx_col_12,               //  Collition
773 
        input wire   rx_clk_12,                 //  Receive Clock
774 
        input wire   tx_clk_12,                 //  Transmit Clock
775 
        input wire   [7:0] gm_rx_d_12,          //  GMII Receive Data
776 
        input wire   gm_rx_dv_12,               //  GMII Receive Frame Enable
777 
        input wire   gm_rx_err_12,              //  GMII Receive Frame Error
778 
        output wire  [7:0] gm_tx_d_12,          //  GMII Transmit Data
779 
        output wire  gm_tx_en_12,               //  GMII Transmit Frame Enable
780 
        output wire  gm_tx_err_12,              //  GMII Transmit Frame Error
781 
        input wire   [3:0] m_rx_d_12,           //  MII Receive Data
782 
        input wire   m_rx_en_12,                //  MII Receive Frame Enable
783 
        input wire   m_rx_err_12,               //  MII Receive Drame Error
784 
        output wire  [3:0] m_tx_d_12,           //  MII Transmit Data
785 
        output wire  m_tx_en_12,                //  MII Transmit Frame Enable
786 
        output wire  m_tx_err_12,               //  MII Transmit Frame Error
787 
        output wire  tx_control_12,
788 
        output wire  [3:0] rgmii_out_12,
789 
        input wire   [3:0] rgmii_in_12,
790 
        input wire   rx_control_12,
791 
        output wire  eth_mode_12,               //  Ethernet Mode
792 
        output wire  ena_10_12,                 //  Enable 10Mbps Mode
793 
        input wire   set_1000_12,               //  Gigabit Mode Enable
794 
        input wire   set_10_12,                 //  10Mbps Mode Enable
795 
 
796 
        // AV-ST TX & RX
797 
        output wire  mac_rx_clk_12,             //  Av-ST Receive Clock
798 
        output wire  mac_tx_clk_12,             //  Av-ST Transmit Clock
799 
        output wire  data_rx_sop_12,            //  Start of Packet
800 
        output wire  data_rx_eop_12,            //  End of Packet
801 
        output wire  [7:0] data_rx_data_12,     //  Data from FIFO
802 
        output wire  [4:0] data_rx_error_12,    //  Receive packet error
803 
        output wire  data_rx_valid_12,          //  Data Receive FIFO Valid
804 
        input wire   data_rx_ready_12,          //  Data Receive Ready
805 
        output wire  [4:0] pkt_class_data_12,   //  Frame Type Indication
806 
        output wire  pkt_class_valid_12,        //  Frame Type Indication Valid
807 
        input wire   data_tx_error_12,          //  STATUS FIFO (Tx frame Error from Apps)
808 
        input wire   [7:0] data_tx_data_12,     //  Data from FIFO transmit
809 
        input wire   data_tx_valid_12,          //  Data FIFO transmit Empty
810 
        input wire   data_tx_sop_12,            //  Start of Packet
811 
        input wire   data_tx_eop_12,            //  END of Packet
812 
        output wire  data_tx_ready_12,          //  Data FIFO transmit Read Enable
813 
 
814 
        // STAND_ALONE CONDUITS
815 
        output wire  tx_ff_uflow_12,            //  TX FIFO underflow occured (Synchronous with tx_clk)
816 
        input wire   tx_crc_fwd_12,             //  Forward Current Frame with CRC from Application
817 
        input wire   xoff_gen_12,               //  Xoff Pause frame generate
818 
        input wire   xon_gen_12,                //  Xon Pause frame generate
819 
        input wire   magic_sleep_n_12,          //  Enable Sleep Mode
820 
        output wire  magic_wakeup_12,           //  Wake Up Request
821 
 
822 
 
823 
    // CHANNEL 13
824 
 
825 
        // GMII / MII / RGMII SIGNALS
826 
        input wire   m_rx_crs_13,               //  Carrier Sense
827 
        input wire   m_rx_col_13,               //  Collition
828 
        input wire   rx_clk_13,                 //  Receive Clock
829 
        input wire   tx_clk_13,                 //  Transmit Clock
830 
        input wire   [7:0] gm_rx_d_13,          //  GMII Receive Data
831 
        input wire   gm_rx_dv_13,               //  GMII Receive Frame Enable
832 
        input wire   gm_rx_err_13,              //  GMII Receive Frame Error
833 
        output wire  [7:0] gm_tx_d_13,          //  GMII Transmit Data
834 
        output wire  gm_tx_en_13,               //  GMII Transmit Frame Enable
835 
        output wire  gm_tx_err_13,              //  GMII Transmit Frame Error
836 
        input wire   [3:0] m_rx_d_13,           //  MII Receive Data
837 
        input wire   m_rx_en_13,                //  MII Receive Frame Enable
838 
        input wire   m_rx_err_13,               //  MII Receive Drame Error
839 
        output wire  [3:0] m_tx_d_13,           //  MII Transmit Data
840 
        output wire  m_tx_en_13,                //  MII Transmit Frame Enable
841 
        output wire  m_tx_err_13,               //  MII Transmit Frame Error
842 
        output wire  tx_control_13,
843 
        output wire  [3:0] rgmii_out_13,
844 
        input wire   [3:0] rgmii_in_13,
845 
        input wire   rx_control_13,
846 
        output wire  eth_mode_13,               //  Ethernet Mode
847 
        output wire  ena_10_13,                 //  Enable 10Mbps Mode
848 
        input wire   set_1000_13,               //  Gigabit Mode Enable
849 
        input wire   set_10_13,                 //  10Mbps Mode Enable
850 
 
851 
        // AV-ST TX & RX
852 
        output wire  mac_rx_clk_13,             //  Av-ST Receive Clock
853 
        output wire  mac_tx_clk_13,             //  Av-ST Transmit Clock
854 
        output wire  data_rx_sop_13,            //  Start of Packet
855 
        output wire  data_rx_eop_13,            //  End of Packet
856 
        output wire  [7:0] data_rx_data_13,     //  Data from FIFO
857 
        output wire  [4:0] data_rx_error_13,    //  Receive packet error
858 
        output wire  data_rx_valid_13,          //  Data Receive FIFO Valid
859 
        input wire   data_rx_ready_13,          //  Data Receive Ready
860 
        output wire  [4:0] pkt_class_data_13,   //  Frame Type Indication
861 
        output wire  pkt_class_valid_13,        //  Frame Type Indication Valid
862 
        input wire   data_tx_error_13,          //  STATUS FIFO (Tx frame Error from Apps)
863 
        input wire   [7:0] data_tx_data_13,     //  Data from FIFO transmit
864 
        input wire   data_tx_valid_13,          //  Data FIFO transmit Empty
865 
        input wire   data_tx_sop_13,            //  Start of Packet
866 
        input wire   data_tx_eop_13,            //  END of Packet
867 
        output wire  data_tx_ready_13,          //  Data FIFO transmit Read Enable
868 
 
869 
        // STAND_ALONE CONDUITS
870 
        output wire  tx_ff_uflow_13,            //  TX FIFO underflow occured (Synchronous with tx_clk)
871 
        input wire   tx_crc_fwd_13,             //  Forward Current Frame with CRC from Application
872 
        input wire   xoff_gen_13,               //  Xoff Pause frame generate
873 
        input wire   xon_gen_13,                //  Xon Pause frame generate
874 
        input wire   magic_sleep_n_13,          //  Enable Sleep Mode
875 
        output wire  magic_wakeup_13,           //  Wake Up Request
876 
 
877 
 
878 
    // CHANNEL 14
879 
 
880 
        // GMII / MII / RGMII SIGNALS
881 
        input wire   m_rx_crs_14,               //  Carrier Sense
882 
        input wire   m_rx_col_14,               //  Collition
883 
        input wire   rx_clk_14,                 //  Receive Clock
884 
        input wire   tx_clk_14,                 //  Transmit Clock
885 
        input wire   [7:0] gm_rx_d_14,          //  GMII Receive Data
886 
        input wire   gm_rx_dv_14,               //  GMII Receive Frame Enable
887 
        input wire   gm_rx_err_14,              //  GMII Receive Frame Error
888 
        output wire  [7:0] gm_tx_d_14,          //  GMII Transmit Data
889 
        output wire  gm_tx_en_14,               //  GMII Transmit Frame Enable
890 
        output wire  gm_tx_err_14,              //  GMII Transmit Frame Error
891 
        input wire   [3:0] m_rx_d_14,           //  MII Receive Data
892 
        input wire   m_rx_en_14,                //  MII Receive Frame Enable
893 
        input wire   m_rx_err_14,               //  MII Receive Drame Error
894 
        output wire  [3:0] m_tx_d_14,           //  MII Transmit Data
895 
        output wire  m_tx_en_14,                //  MII Transmit Frame Enable
896 
        output wire  m_tx_err_14,               //  MII Transmit Frame Error
897 
        output wire  tx_control_14,
898 
        output wire  [3:0] rgmii_out_14,
899 
        input wire   [3:0] rgmii_in_14,
900 
        input wire   rx_control_14,
901 
        output wire  eth_mode_14,               //  Ethernet Mode
902 
        output wire  ena_10_14,                 //  Enable 10Mbps Mode
903 
        input wire   set_1000_14,               //  Gigabit Mode Enable
904 
        input wire   set_10_14,                 //  10Mbps Mode Enable
905 
 
906 
        // AV-ST TX & RX
907 
        output wire  mac_rx_clk_14,             //  Av-ST Receive Clock
908 
        output wire  mac_tx_clk_14,             //  Av-ST Transmit Clock
909 
        output wire  data_rx_sop_14,            //  Start of Packet
910 
        output wire  data_rx_eop_14,            //  End of Packet
911 
        output wire  [7:0] data_rx_data_14,     //  Data from FIFO
912 
        output wire  [4:0] data_rx_error_14,    //  Receive packet error
913 
        output wire  data_rx_valid_14,          //  Data Receive FIFO Valid
914 
        input wire   data_rx_ready_14,          //  Data Receive Ready
915 
        output wire  [4:0] pkt_class_data_14,   //  Frame Type Indication
916 
        output wire  pkt_class_valid_14,        //  Frame Type Indication Valid
917 
        input wire   data_tx_error_14,          //  STATUS FIFO (Tx frame Error from Apps)
918 
        input wire   [7:0] data_tx_data_14,     //  Data from FIFO transmit
919 
        input wire   data_tx_valid_14,          //  Data FIFO transmit Empty
920 
        input wire   data_tx_sop_14,            //  Start of Packet
921 
        input wire   data_tx_eop_14,            //  END of Packet
922 
        output wire  data_tx_ready_14,          //  Data FIFO transmit Read Enable
923 
 
924 
        // STAND_ALONE CONDUITS
925 
        output wire  tx_ff_uflow_14,            //  TX FIFO underflow occured (Synchronous with tx_clk)
926 
        input wire   tx_crc_fwd_14,             //  Forward Current Frame with CRC from Application
927 
        input wire   xoff_gen_14,               //  Xoff Pause frame generate
928 
        input wire   xon_gen_14,                //  Xon Pause frame generate
929 
        input wire   magic_sleep_n_14,          //  Enable Sleep Mode
930 
        output wire  magic_wakeup_14,           //  Wake Up Request
931 
 
932 
 
933 
    // CHANNEL 15
934 
 
935 
        // GMII / MII / RGMII SIGNALS
936 
        input wire   m_rx_crs_15,               //  Carrier Sense
937 
        input wire   m_rx_col_15,               //  Collition
938 
        input wire   rx_clk_15,                 //  Receive Clock
939 
        input wire   tx_clk_15,                 //  Transmit Clock
940 
        input wire   [7:0] gm_rx_d_15,          //  GMII Receive Data
941 
        input wire   gm_rx_dv_15,               //  GMII Receive Frame Enable
942 
        input wire   gm_rx_err_15,              //  GMII Receive Frame Error
943 
        output wire  [7:0] gm_tx_d_15,          //  GMII Transmit Data
944 
        output wire  gm_tx_en_15,               //  GMII Transmit Frame Enable
945 
        output wire  gm_tx_err_15,              //  GMII Transmit Frame Error
946 
        input wire   [3:0] m_rx_d_15,           //  MII Receive Data
947 
        input wire   m_rx_en_15,                //  MII Receive Frame Enable
948 
        input wire   m_rx_err_15,               //  MII Receive Drame Error
949 
        output wire  [3:0] m_tx_d_15,           //  MII Transmit Data
950 
        output wire  m_tx_en_15,                //  MII Transmit Frame Enable
951 
        output wire  m_tx_err_15,               //  MII Transmit Frame Error
952 
        output wire  tx_control_15,
953 
        output wire  [3:0] rgmii_out_15,
954 
        input wire   [3:0] rgmii_in_15,
955 
        input wire   rx_control_15,
956 
        output wire  eth_mode_15,               //  Ethernet Mode
957 
        output wire  ena_10_15,                 //  Enable 10Mbps Mode
958 
        input wire   set_1000_15,               //  Gigabit Mode Enable
959 
        input wire   set_10_15,                 //  10Mbps Mode Enable
960 
 
961 
        // AV-ST TX & RX
962 
        output wire  mac_rx_clk_15,             //  Av-ST Receive Clock
963 
        output wire  mac_tx_clk_15,             //  Av-ST Transmit Clock
964 
        output wire  data_rx_sop_15,            //  Start of Packet
965 
        output wire  data_rx_eop_15,            //  End of Packet
966 
        output wire  [7:0] data_rx_data_15,     //  Data from FIFO
967 
        output wire  [4:0] data_rx_error_15,    //  Receive packet error
968 
        output wire  data_rx_valid_15,          //  Data Receive FIFO Valid
969 
        input wire   data_rx_ready_15,          //  Data Receive Ready
970 
        output wire  [4:0] pkt_class_data_15,   //  Frame Type Indication
971 
        output wire  pkt_class_valid_15,        //  Frame Type Indication Valid
972 
        input wire   data_tx_error_15,          //  STATUS FIFO (Tx frame Error from Apps)
973 
        input wire   [7:0] data_tx_data_15,     //  Data from FIFO transmit
974 
        input wire   data_tx_valid_15,          //  Data FIFO transmit Empty
975 
        input wire   data_tx_sop_15,            //  Start of Packet
976 
        input wire   data_tx_eop_15,            //  END of Packet
977 
        output wire  data_tx_ready_15,          //  Data FIFO transmit Read Enable
978 
 
979 
        // STAND_ALONE CONDUITS
980 
        output wire  tx_ff_uflow_15,            //  TX FIFO underflow occured (Synchronous with tx_clk)
981 
        input wire   tx_crc_fwd_15,             //  Forward Current Frame with CRC from Application
982 
        input wire   xoff_gen_15,               //  Xoff Pause frame generate
983 
        input wire   xon_gen_15,                //  Xon Pause frame generate
984 
        input wire   magic_sleep_n_15,          //  Enable Sleep Mode
985 
        output wire  magic_wakeup_15,           //  Wake Up Request
986 
 
987 
 
988 
    // CHANNEL 16
989 
 
990 
        // GMII / MII / RGMII SIGNALS
991 
        input wire   m_rx_crs_16,               //  Carrier Sense
992 
        input wire   m_rx_col_16,               //  Collition
993 
        input wire   rx_clk_16,                 //  Receive Clock
994 
        input wire   tx_clk_16,                 //  Transmit Clock
995 
        input wire   [7:0] gm_rx_d_16,          //  GMII Receive Data
996 
        input wire   gm_rx_dv_16,               //  GMII Receive Frame Enable
997 
        input wire   gm_rx_err_16,              //  GMII Receive Frame Error
998 
        output wire  [7:0] gm_tx_d_16,          //  GMII Transmit Data
999 
        output wire  gm_tx_en_16,               //  GMII Transmit Frame Enable
1000 
        output wire  gm_tx_err_16,              //  GMII Transmit Frame Error
1001 
        input wire   [3:0] m_rx_d_16,           //  MII Receive Data
1002 
        input wire   m_rx_en_16,                //  MII Receive Frame Enable
1003 
        input wire   m_rx_err_16,               //  MII Receive Drame Error
1004 
        output wire  [3:0] m_tx_d_16,           //  MII Transmit Data
1005 
        output wire  m_tx_en_16,                //  MII Transmit Frame Enable
1006 
        output wire  m_tx_err_16,               //  MII Transmit Frame Error
1007 
        output wire  tx_control_16,
1008 
        output wire  [3:0] rgmii_out_16,
1009 
        input wire   [3:0] rgmii_in_16,
1010 
        input wire   rx_control_16,
1011 
        output wire  eth_mode_16,               //  Ethernet Mode
1012 
        output wire  ena_10_16,                 //  Enable 10Mbps Mode
1013 
        input wire   set_1000_16,               //  Gigabit Mode Enable
1014 
        input wire   set_10_16,                 //  10Mbps Mode Enable
1015 
 
1016 
        // AV-ST TX & RX
1017 
        output wire  mac_rx_clk_16,             //  Av-ST Receive Clock
1018 
        output wire  mac_tx_clk_16,             //  Av-ST Transmit Clock
1019 
        output wire  data_rx_sop_16,            //  Start of Packet
1020 
        output wire  data_rx_eop_16,            //  End of Packet
1021 
        output wire  [7:0] data_rx_data_16,     //  Data from FIFO
1022 
        output wire  [4:0] data_rx_error_16,    //  Receive packet error
1023 
        output wire  data_rx_valid_16,          //  Data Receive FIFO Valid
1024 
        input wire   data_rx_ready_16,          //  Data Receive Ready
1025 
        output wire  [4:0] pkt_class_data_16,   //  Frame Type Indication
1026 
        output wire  pkt_class_valid_16,        //  Frame Type Indication Valid
1027 
        input wire   data_tx_error_16,          //  STATUS FIFO (Tx frame Error from Apps)
1028 
        input wire   [7:0] data_tx_data_16,     //  Data from FIFO transmit
1029 
        input wire   data_tx_valid_16,          //  Data FIFO transmit Empty
1030 
        input wire   data_tx_sop_16,            //  Start of Packet
1031 
        input wire   data_tx_eop_16,            //  END of Packet
1032 
        output wire  data_tx_ready_16,          //  Data FIFO transmit Read Enable
1033 
 
1034 
        // STAND_ALONE CONDUITS
1035 
        output wire  tx_ff_uflow_16,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1036 
        input wire   tx_crc_fwd_16,             //  Forward Current Frame with CRC from Application
1037 
        input wire   xoff_gen_16,               //  Xoff Pause frame generate
1038 
        input wire   xon_gen_16,                //  Xon Pause frame generate
1039 
        input wire   magic_sleep_n_16,          //  Enable Sleep Mode
1040 
        output wire  magic_wakeup_16,           //  Wake Up Request
1041 
 
1042 
 
1043 
    // CHANNEL 17
1044 
 
1045 
        // GMII / MII / RGMII SIGNALS
1046 
        input wire   m_rx_crs_17,               //  Carrier Sense
1047 
        input wire   m_rx_col_17,               //  Collition
1048 
        input wire   rx_clk_17,                 //  Receive Clock
1049 
        input wire   tx_clk_17,                 //  Transmit Clock
1050 
        input wire   [7:0] gm_rx_d_17,          //  GMII Receive Data
1051 
        input wire   gm_rx_dv_17,               //  GMII Receive Frame Enable
1052 
        input wire   gm_rx_err_17,              //  GMII Receive Frame Error
1053 
        output wire  [7:0] gm_tx_d_17,          //  GMII Transmit Data
1054 
        output wire  gm_tx_en_17,               //  GMII Transmit Frame Enable
1055 
        output wire  gm_tx_err_17,              //  GMII Transmit Frame Error
1056 
        input wire   [3:0] m_rx_d_17,           //  MII Receive Data
1057 
        input wire   m_rx_en_17,                //  MII Receive Frame Enable
1058 
        input wire   m_rx_err_17,               //  MII Receive Drame Error
1059 
        output wire  [3:0] m_tx_d_17,           //  MII Transmit Data
1060 
        output wire  m_tx_en_17,                //  MII Transmit Frame Enable
1061 
        output wire  m_tx_err_17,               //  MII Transmit Frame Error
1062 
        output wire  tx_control_17,
1063 
        output wire  [3:0] rgmii_out_17,
1064 
        input wire   [3:0] rgmii_in_17,
1065 
        input wire   rx_control_17,
1066 
        output wire  eth_mode_17,               //  Ethernet Mode
1067 
        output wire  ena_10_17,                 //  Enable 10Mbps Mode
1068 
        input wire   set_1000_17,               //  Gigabit Mode Enable
1069 
        input wire   set_10_17,                 //  10Mbps Mode Enable
1070 
 
1071 
        // AV-ST TX & RX
1072 
        output wire  mac_rx_clk_17,             //  Av-ST Receive Clock
1073 
        output wire  mac_tx_clk_17,             //  Av-ST Transmit Clock
1074 
        output wire  data_rx_sop_17,            //  Start of Packet
1075 
        output wire  data_rx_eop_17,            //  End of Packet
1076 
        output wire  [7:0] data_rx_data_17,     //  Data from FIFO
1077 
        output wire  [4:0] data_rx_error_17,    //  Receive packet error
1078 
        output wire  data_rx_valid_17,          //  Data Receive FIFO Valid
1079 
        input wire   data_rx_ready_17,          //  Data Receive Ready
1080 
        output wire  [4:0] pkt_class_data_17,   //  Frame Type Indication
1081 
        output wire  pkt_class_valid_17,        //  Frame Type Indication Valid
1082 
        input wire   data_tx_error_17,          //  STATUS FIFO (Tx frame Error from Apps)
1083 
        input wire   [7:0] data_tx_data_17,     //  Data from FIFO transmit
1084 
        input wire   data_tx_valid_17,          //  Data FIFO transmit Empty
1085 
        input wire   data_tx_sop_17,            //  Start of Packet
1086 
        input wire   data_tx_eop_17,            //  END of Packet
1087 
        output wire  data_tx_ready_17,          //  Data FIFO transmit Read Enable
1088 
 
1089 
        // STAND_ALONE CONDUITS
1090 
        output wire  tx_ff_uflow_17,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1091 
        input wire   tx_crc_fwd_17,             //  Forward Current Frame with CRC from Application
1092 
        input wire   xoff_gen_17,               //  Xoff Pause frame generate
1093 
        input wire   xon_gen_17,                //  Xon Pause frame generate
1094 
        input wire   magic_sleep_n_17,          //  Enable Sleep Mode
1095 
        output wire  magic_wakeup_17,           //  Wake Up Request
1096 
 
1097 
 
1098 
    // CHANNEL 18
1099 
 
1100 
        // GMII / MII / RGMII SIGNALS
1101 
        input wire   m_rx_crs_18,               //  Carrier Sense
1102 
        input wire   m_rx_col_18,               //  Collition
1103 
        input wire   rx_clk_18,                 //  Receive Clock
1104 
        input wire   tx_clk_18,                 //  Transmit Clock
1105 
        input wire   [7:0] gm_rx_d_18,          //  GMII Receive Data
1106 
        input wire   gm_rx_dv_18,               //  GMII Receive Frame Enable
1107 
        input wire   gm_rx_err_18,              //  GMII Receive Frame Error
1108 
        output wire  [7:0] gm_tx_d_18,          //  GMII Transmit Data
1109 
        output wire  gm_tx_en_18,               //  GMII Transmit Frame Enable
1110 
        output wire  gm_tx_err_18,              //  GMII Transmit Frame Error
1111 
        input wire   [3:0] m_rx_d_18,           //  MII Receive Data
1112 
        input wire   m_rx_en_18,                //  MII Receive Frame Enable
1113 
        input wire   m_rx_err_18,               //  MII Receive Drame Error
1114 
        output wire  [3:0] m_tx_d_18,           //  MII Transmit Data
1115 
        output wire  m_tx_en_18,                //  MII Transmit Frame Enable
1116 
        output wire  m_tx_err_18,               //  MII Transmit Frame Error
1117 
        output wire  tx_control_18,
1118 
        output wire  [3:0] rgmii_out_18,
1119 
        input wire   [3:0] rgmii_in_18,
1120 
        input wire   rx_control_18,
1121 
        output wire  eth_mode_18,               //  Ethernet Mode
1122 
        output wire  ena_10_18,                 //  Enable 10Mbps Mode
1123 
        input wire   set_1000_18,               //  Gigabit Mode Enable
1124 
        input wire   set_10_18,                 //  10Mbps Mode Enable
1125 
 
1126 
        // AV-ST TX & RX
1127 
        output wire  mac_rx_clk_18,             //  Av-ST Receive Clock
1128 
        output wire  mac_tx_clk_18,             //  Av-ST Transmit Clock
1129 
        output wire  data_rx_sop_18,            //  Start of Packet
1130 
        output wire  data_rx_eop_18,            //  End of Packet
1131 
        output wire  [7:0] data_rx_data_18,     //  Data from FIFO
1132 
        output wire  [4:0] data_rx_error_18,    //  Receive packet error
1133 
        output wire  data_rx_valid_18,          //  Data Receive FIFO Valid
1134 
        input wire   data_rx_ready_18,          //  Data Receive Ready
1135 
        output wire  [4:0] pkt_class_data_18,   //  Frame Type Indication
1136 
        output wire  pkt_class_valid_18,        //  Frame Type Indication Valid
1137 
        input wire   data_tx_error_18,          //  STATUS FIFO (Tx frame Error from Apps)
1138 
        input wire   [7:0] data_tx_data_18,     //  Data from FIFO transmit
1139 
        input wire   data_tx_valid_18,          //  Data FIFO transmit Empty
1140 
        input wire   data_tx_sop_18,            //  Start of Packet
1141 
        input wire   data_tx_eop_18,            //  END of Packet
1142 
        output wire  data_tx_ready_18,          //  Data FIFO transmit Read Enable
1143 
 
1144 
        // STAND_ALONE CONDUITS
1145 
        output wire  tx_ff_uflow_18,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1146 
        input wire   tx_crc_fwd_18,             //  Forward Current Frame with CRC from Application
1147 
        input wire   xoff_gen_18,               //  Xoff Pause frame generate
1148 
        input wire   xon_gen_18,                //  Xon Pause frame generate
1149 
        input wire   magic_sleep_n_18,          //  Enable Sleep Mode
1150 
        output wire  magic_wakeup_18,           //  Wake Up Request
1151 
 
1152 
 
1153 
    // CHANNEL 19
1154 
 
1155 
        // GMII / MII / RGMII SIGNALS
1156 
        input wire   m_rx_crs_19,               //  Carrier Sense
1157 
        input wire   m_rx_col_19,               //  Collition
1158 
        input wire   rx_clk_19,                 //  Receive Clock
1159 
        input wire   tx_clk_19,                 //  Transmit Clock
1160 
        input wire   [7:0] gm_rx_d_19,          //  GMII Receive Data
1161 
        input wire   gm_rx_dv_19,               //  GMII Receive Frame Enable
1162 
        input wire   gm_rx_err_19,              //  GMII Receive Frame Error
1163 
        output wire  [7:0] gm_tx_d_19,          //  GMII Transmit Data
1164 
        output wire  gm_tx_en_19,               //  GMII Transmit Frame Enable
1165 
        output wire  gm_tx_err_19,              //  GMII Transmit Frame Error
1166 
        input wire   [3:0] m_rx_d_19,           //  MII Receive Data
1167 
        input wire   m_rx_en_19,                //  MII Receive Frame Enable
1168 
        input wire   m_rx_err_19,               //  MII Receive Drame Error
1169 
        output wire  [3:0] m_tx_d_19,           //  MII Transmit Data
1170 
        output wire  m_tx_en_19,                //  MII Transmit Frame Enable
1171 
        output wire  m_tx_err_19,               //  MII Transmit Frame Error
1172 
        output wire  tx_control_19,
1173 
        output wire  [3:0] rgmii_out_19,
1174 
        input wire   [3:0] rgmii_in_19,
1175 
        input wire   rx_control_19,
1176 
        output wire  eth_mode_19,               //  Ethernet Mode
1177 
        output wire  ena_10_19,                 //  Enable 10Mbps Mode
1178 
        input wire   set_1000_19,               //  Gigabit Mode Enable
1179 
        input wire   set_10_19,                 //  10Mbps Mode Enable
1180 
 
1181 
        // AV-ST TX & RX
1182 
        output wire  mac_rx_clk_19,             //  Av-ST Receive Clock
1183 
        output wire  mac_tx_clk_19,             //  Av-ST Transmit Clock
1184 
        output wire  data_rx_sop_19,            //  Start of Packet
1185 
        output wire  data_rx_eop_19,            //  End of Packet
1186 
        output wire  [7:0] data_rx_data_19,     //  Data from FIFO
1187 
        output wire  [4:0] data_rx_error_19,    //  Receive packet error
1188 
        output wire  data_rx_valid_19,          //  Data Receive FIFO Valid
1189 
        input wire   data_rx_ready_19,          //  Data Receive Ready
1190 
        output wire  [4:0] pkt_class_data_19,   //  Frame Type Indication
1191 
        output wire  pkt_class_valid_19,        //  Frame Type Indication Valid
1192 
        input wire   data_tx_error_19,          //  STATUS FIFO (Tx frame Error from Apps)
1193 
        input wire   [7:0] data_tx_data_19,     //  Data from FIFO transmit
1194 
        input wire   data_tx_valid_19,          //  Data FIFO transmit Empty
1195 
        input wire   data_tx_sop_19,            //  Start of Packet
1196 
        input wire   data_tx_eop_19,            //  END of Packet
1197 
        output wire  data_tx_ready_19,          //  Data FIFO transmit Read Enable
1198 
 
1199 
        // STAND_ALONE CONDUITS
1200 
        output wire  tx_ff_uflow_19,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1201 
        input wire   tx_crc_fwd_19,             //  Forward Current Frame with CRC from Application
1202 
        input wire   xoff_gen_19,               //  Xoff Pause frame generate
1203 
        input wire   xon_gen_19,                //  Xon Pause frame generate
1204 
        input wire   magic_sleep_n_19,          //  Enable Sleep Mode
1205 
        output wire  magic_wakeup_19,           //  Wake Up Request
1206 
 
1207 
 
1208 
    // CHANNEL 20
1209 
 
1210 
        // GMII / MII / RGMII SIGNALS
1211 
        input wire   m_rx_crs_20,               //  Carrier Sense
1212 
        input wire   m_rx_col_20,               //  Collition
1213 
        input wire   rx_clk_20,                 //  Receive Clock
1214 
        input wire   tx_clk_20,                 //  Transmit Clock
1215 
        input wire   [7:0] gm_rx_d_20,          //  GMII Receive Data
1216 
        input wire   gm_rx_dv_20,               //  GMII Receive Frame Enable
1217 
        input wire   gm_rx_err_20,              //  GMII Receive Frame Error
1218 
        output wire  [7:0] gm_tx_d_20,          //  GMII Transmit Data
1219 
        output wire  gm_tx_en_20,               //  GMII Transmit Frame Enable
1220 
        output wire  gm_tx_err_20,              //  GMII Transmit Frame Error
1221 
        input wire   [3:0] m_rx_d_20,           //  MII Receive Data
1222 
        input wire   m_rx_en_20,                //  MII Receive Frame Enable
1223 
        input wire   m_rx_err_20,               //  MII Receive Drame Error
1224 
        output wire  [3:0] m_tx_d_20,           //  MII Transmit Data
1225 
        output wire  m_tx_en_20,                //  MII Transmit Frame Enable
1226 
        output wire  m_tx_err_20,               //  MII Transmit Frame Error
1227 
        output wire  tx_control_20,
1228 
        output wire  [3:0] rgmii_out_20,
1229 
        input wire   [3:0] rgmii_in_20,
1230 
        input wire   rx_control_20,
1231 
        output wire  eth_mode_20,               //  Ethernet Mode
1232 
        output wire  ena_10_20,                 //  Enable 10Mbps Mode
1233 
        input wire   set_1000_20,               //  Gigabit Mode Enable
1234 
        input wire   set_10_20,                 //  10Mbps Mode Enable
1235 
 
1236 
        // AV-ST TX & RX
1237 
        output wire  mac_rx_clk_20,             //  Av-ST Receive Clock
1238 
        output wire  mac_tx_clk_20,             //  Av-ST Transmit Clock
1239 
        output wire  data_rx_sop_20,            //  Start of Packet
1240 
        output wire  data_rx_eop_20,            //  End of Packet
1241 
        output wire  [7:0] data_rx_data_20,     //  Data from FIFO
1242 
        output wire  [4:0] data_rx_error_20,    //  Receive packet error
1243 
        output wire  data_rx_valid_20,          //  Data Receive FIFO Valid
1244 
        input wire   data_rx_ready_20,          //  Data Receive Ready
1245 
        output wire  [4:0] pkt_class_data_20,   //  Frame Type Indication
1246 
        output wire  pkt_class_valid_20,        //  Frame Type Indication Valid
1247 
        input wire   data_tx_error_20,          //  STATUS FIFO (Tx frame Error from Apps)
1248 
        input wire   [7:0] data_tx_data_20,     //  Data from FIFO transmit
1249 
        input wire   data_tx_valid_20,          //  Data FIFO transmit Empty
1250 
        input wire   data_tx_sop_20,            //  Start of Packet
1251 
        input wire   data_tx_eop_20,            //  END of Packet
1252 
        output wire  data_tx_ready_20,          //  Data FIFO transmit Read Enable
1253 
 
1254 
        // STAND_ALONE CONDUITS
1255 
        output wire  tx_ff_uflow_20,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1256 
        input wire   tx_crc_fwd_20,             //  Forward Current Frame with CRC from Application
1257 
        input wire   xoff_gen_20,               //  Xoff Pause frame generate
1258 
        input wire   xon_gen_20,                //  Xon Pause frame generate
1259 
        input wire   magic_sleep_n_20,          //  Enable Sleep Mode
1260 
        output wire  magic_wakeup_20,           //  Wake Up Request
1261 
 
1262 
 
1263 
    // CHANNEL 21
1264 
 
1265 
        // GMII / MII / RGMII SIGNALS
1266 
        input wire   m_rx_crs_21,               //  Carrier Sense
1267 
        input wire   m_rx_col_21,               //  Collition
1268 
        input wire   rx_clk_21,                 //  Receive Clock
1269 
        input wire   tx_clk_21,                 //  Transmit Clock
1270 
        input wire   [7:0] gm_rx_d_21,          //  GMII Receive Data
1271 
        input wire   gm_rx_dv_21,               //  GMII Receive Frame Enable
1272 
        input wire   gm_rx_err_21,              //  GMII Receive Frame Error
1273 
        output wire  [7:0] gm_tx_d_21,          //  GMII Transmit Data
1274 
        output wire  gm_tx_en_21,               //  GMII Transmit Frame Enable
1275 
        output wire  gm_tx_err_21,              //  GMII Transmit Frame Error
1276 
        input wire   [3:0] m_rx_d_21,           //  MII Receive Data
1277 
        input wire   m_rx_en_21,                //  MII Receive Frame Enable
1278 
        input wire   m_rx_err_21,               //  MII Receive Drame Error
1279 
        output wire  [3:0] m_tx_d_21,           //  MII Transmit Data
1280 
        output wire  m_tx_en_21,                //  MII Transmit Frame Enable
1281 
        output wire  m_tx_err_21,               //  MII Transmit Frame Error
1282 
        output wire  tx_control_21,
1283 
        output wire  [3:0] rgmii_out_21,
1284 
        input wire   [3:0] rgmii_in_21,
1285 
        input wire   rx_control_21,
1286 
        output wire  eth_mode_21,               //  Ethernet Mode
1287 
        output wire  ena_10_21,                 //  Enable 10Mbps Mode
1288 
        input wire   set_1000_21,               //  Gigabit Mode Enable
1289 
        input wire   set_10_21,                 //  10Mbps Mode Enable
1290 
 
1291 
        // AV-ST TX & RX
1292 
        output wire  mac_rx_clk_21,             //  Av-ST Receive Clock
1293 
        output wire  mac_tx_clk_21,             //  Av-ST Transmit Clock
1294 
        output wire  data_rx_sop_21,            //  Start of Packet
1295 
        output wire  data_rx_eop_21,            //  End of Packet
1296 
        output wire  [7:0] data_rx_data_21,     //  Data from FIFO
1297 
        output wire  [4:0] data_rx_error_21,    //  Receive packet error
1298 
        output wire  data_rx_valid_21,          //  Data Receive FIFO Valid
1299 
        input wire   data_rx_ready_21,          //  Data Receive Ready
1300 
        output wire  [4:0] pkt_class_data_21,   //  Frame Type Indication
1301 
        output wire  pkt_class_valid_21,        //  Frame Type Indication Valid
1302 
        input wire   data_tx_error_21,          //  STATUS FIFO (Tx frame Error from Apps)
1303 
        input wire   [7:0] data_tx_data_21,     //  Data from FIFO transmit
1304 
        input wire   data_tx_valid_21,          //  Data FIFO transmit Empty
1305 
        input wire   data_tx_sop_21,            //  Start of Packet
1306 
        input wire   data_tx_eop_21,            //  END of Packet
1307 
        output wire  data_tx_ready_21,          //  Data FIFO transmit Read Enable
1308 
 
1309 
        // STAND_ALONE CONDUITS
1310 
        output wire  tx_ff_uflow_21,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1311 
        input wire   tx_crc_fwd_21,             //  Forward Current Frame with CRC from Application
1312 
        input wire   xoff_gen_21,               //  Xoff Pause frame generate
1313 
        input wire   xon_gen_21,                //  Xon Pause frame generate
1314 
        input wire   magic_sleep_n_21,          //  Enable Sleep Mode
1315 
        output wire  magic_wakeup_21,           //  Wake Up Request
1316 
 
1317 
 
1318 
    // CHANNEL 22
1319 
 
1320 
        // GMII / MII / RGMII SIGNALS
1321 
        input wire   m_rx_crs_22,               //  Carrier Sense
1322 
        input wire   m_rx_col_22,               //  Collition
1323 
        input wire   rx_clk_22,                 //  Receive Clock
1324 
        input wire   tx_clk_22,                 //  Transmit Clock
1325 
        input wire   [7:0] gm_rx_d_22,          //  GMII Receive Data
1326 
        input wire   gm_rx_dv_22,               //  GMII Receive Frame Enable
1327 
        input wire   gm_rx_err_22,              //  GMII Receive Frame Error
1328 
        output wire  [7:0] gm_tx_d_22,          //  GMII Transmit Data
1329 
        output wire  gm_tx_en_22,               //  GMII Transmit Frame Enable
1330 
        output wire  gm_tx_err_22,              //  GMII Transmit Frame Error
1331 
        input wire   [3:0] m_rx_d_22,           //  MII Receive Data
1332 
        input wire   m_rx_en_22,                //  MII Receive Frame Enable
1333 
        input wire   m_rx_err_22,               //  MII Receive Drame Error
1334 
        output wire  [3:0] m_tx_d_22,           //  MII Transmit Data
1335 
        output wire  m_tx_en_22,                //  MII Transmit Frame Enable
1336 
        output wire  m_tx_err_22,               //  MII Transmit Frame Error
1337 
        output wire  tx_control_22,
1338 
        output wire  [3:0] rgmii_out_22,
1339 
        input wire   [3:0] rgmii_in_22,
1340 
        input wire   rx_control_22,
1341 
        output wire  eth_mode_22,               //  Ethernet Mode
1342 
        output wire  ena_10_22,                 //  Enable 10Mbps Mode
1343 
        input wire   set_1000_22,               //  Gigabit Mode Enable
1344 
        input wire   set_10_22,                 //  10Mbps Mode Enable
1345 
 
1346 
        // AV-ST TX & RX
1347 
        output wire  mac_rx_clk_22,             //  Av-ST Receive Clock
1348 
        output wire  mac_tx_clk_22,             //  Av-ST Transmit Clock
1349 
        output wire  data_rx_sop_22,            //  Start of Packet
1350 
        output wire  data_rx_eop_22,            //  End of Packet
1351 
        output wire  [7:0] data_rx_data_22,     //  Data from FIFO
1352 
        output wire  [4:0] data_rx_error_22,    //  Receive packet error
1353 
        output wire  data_rx_valid_22,          //  Data Receive FIFO Valid
1354 
        input wire   data_rx_ready_22,          //  Data Receive Ready
1355 
        output wire  [4:0] pkt_class_data_22,   //  Frame Type Indication
1356 
        output wire  pkt_class_valid_22,        //  Frame Type Indication Valid
1357 
        input wire   data_tx_error_22,          //  STATUS FIFO (Tx frame Error from Apps)
1358 
        input wire   [7:0] data_tx_data_22,     //  Data from FIFO transmit
1359 
        input wire   data_tx_valid_22,          //  Data FIFO transmit Empty
1360 
        input wire   data_tx_sop_22,            //  Start of Packet
1361 
        input wire   data_tx_eop_22,            //  END of Packet
1362 
        output wire  data_tx_ready_22,          //  Data FIFO transmit Read Enable
1363 
 
1364 
        // STAND_ALONE CONDUITS
1365 
        output wire  tx_ff_uflow_22,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1366 
        input wire   tx_crc_fwd_22,             //  Forward Current Frame with CRC from Application
1367 
        input wire   xoff_gen_22,               //  Xoff Pause frame generate
1368 
        input wire   xon_gen_22,                //  Xon Pause frame generate
1369 
        input wire   magic_sleep_n_22,          //  Enable Sleep Mode
1370 
        output wire  magic_wakeup_22,           //  Wake Up Request
1371 
 
1372 
 
1373 
    // CHANNEL 23
1374 
 
1375 
        // GMII / MII / RGMII SIGNALS
1376 
        input wire   m_rx_crs_23,               //  Carrier Sense
1377 
        input wire   m_rx_col_23,               //  Collition
1378 
        input wire   rx_clk_23,                 //  Receive Clock
1379 
        input wire   tx_clk_23,                 //  Transmit Clock
1380 
        input wire   [7:0] gm_rx_d_23,          //  GMII Receive Data
1381 
        input wire   gm_rx_dv_23,               //  GMII Receive Frame Enable
1382 
        input wire   gm_rx_err_23,              //  GMII Receive Frame Error
1383 
        output wire  [7:0] gm_tx_d_23,          //  GMII Transmit Data
1384 
        output wire  gm_tx_en_23,               //  GMII Transmit Frame Enable
1385 
        output wire  gm_tx_err_23,              //  GMII Transmit Frame Error
1386 
        input wire   [3:0] m_rx_d_23,           //  MII Receive Data
1387 
        input wire   m_rx_en_23,                //  MII Receive Frame Enable
1388 
        input wire   m_rx_err_23,               //  MII Receive Drame Error
1389 
        output wire  [3:0] m_tx_d_23,           //  MII Transmit Data
1390 
        output wire  m_tx_en_23,                //  MII Transmit Frame Enable
1391 
        output wire  m_tx_err_23,               //  MII Transmit Frame Error
1392 
        output wire  tx_control_23,
1393 
        output wire  [3:0] rgmii_out_23,
1394 
        input wire   [3:0] rgmii_in_23,
1395 
        input wire   rx_control_23,
1396 
        output wire  eth_mode_23,               //  Ethernet Mode
1397 
        output wire  ena_10_23,                 //  Enable 10Mbps Mode
1398 
        input wire   set_1000_23,               //  Gigabit Mode Enable
1399 
        input wire   set_10_23,                 //  10Mbps Mode Enable
1400 
 
1401 
        // AV-ST TX & RX
1402 
        output wire  mac_rx_clk_23,             //  Av-ST Receive Clock
1403 
        output wire  mac_tx_clk_23,             //  Av-ST Transmit Clock
1404 
        output wire  data_rx_sop_23,            //  Start of Packet
1405 
        output wire  data_rx_eop_23,            //  End of Packet
1406 
        output wire  [7:0] data_rx_data_23,     //  Data from FIFO
1407 
        output wire  [4:0] data_rx_error_23,    //  Receive packet error
1408 
        output wire  data_rx_valid_23,          //  Data Receive FIFO Valid
1409 
        input wire   data_rx_ready_23,          //  Data Receive Ready
1410 
        output wire  [4:0] pkt_class_data_23,   //  Frame Type Indication
1411 
        output wire  pkt_class_valid_23,        //  Frame Type Indication Valid
1412 
        input wire   data_tx_error_23,          //  STATUS FIFO (Tx frame Error from Apps)
1413 
        input wire   [7:0] data_tx_data_23,     //  Data from FIFO transmit
1414 
        input wire   data_tx_valid_23,          //  Data FIFO transmit Empty
1415 
        input wire   data_tx_sop_23,            //  Start of Packet
1416 
        input wire   data_tx_eop_23,            //  END of Packet
1417 
        output wire  data_tx_ready_23,          //  Data FIFO transmit Read Enable
1418 
 
1419 
        // STAND_ALONE CONDUITS
1420 
        output wire  tx_ff_uflow_23,            //  TX FIFO underflow occured (Synchronous with tx_clk)
1421 
        input wire   tx_crc_fwd_23,             //  Forward Current Frame with CRC from Application
1422 
        input wire   xoff_gen_23,               //  Xoff Pause frame generate
1423 
        input wire   xon_gen_23,                //  Xon Pause frame generate
1424 
        input wire   magic_sleep_n_23,          //  Enable Sleep Mode
1425 
        output wire  magic_wakeup_23);          //  Wake Up Request
1426 
 
1427 
 
1428 
 
1429 
 
1430 
        altera_tse_top_multi_mac U_TOP_MULTI_MAC(
1431 
 
1432 
                .reset(reset),                            //INPUT  : ASYNCHRONOUS RESET - clk DOMAIN
1433 
                .clk(clk),                                //INPUT  : CLOCK
1434 
                .read(read),                              //INPUT  : REGISTER READ TRANSACTION
1435 
                .write(write),                            //INPUT  : REGISTER WRITE TRANSACTION
1436 
                .address(address),                        //INPUT  : REGISTER ADDRESS
1437 
                .writedata(writedata),                    //INPUT  : REGISTER WRITE DATA
1438 
                .readdata(readdata),                      //OUTPUT : REGISTER READ DATA
1439 
                .waitrequest(waitrequest),                //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
1440 
                .mdc(mdc),                                //OUTPUT : MDIO Clock
1441 
                .mdio_out(mdio_out),                      //OUTPUT : Outgoing MDIO DATA
1442 
                .mdio_in(mdio_in),                        //INPUT  : Incoming MDIO DATA
1443 
                .mdio_oen(mdio_oen),                      //OUTPUT : MDIO Output Enable
1444 
                .rx_clk(rx_clk),                          //INPUT  : MAC RX CLK
1445 
                .tx_clk(tx_clk),                          //INPUT  : MAC TX CLK
1446 
                .mac_rx_clk(mac_rx_clk),                  //OUTPUT : Av-ST Rx Clock
1447 
            .mac_tx_clk(mac_tx_clk),                  //OUTPUT : Av-ST Tx Clock
1448 
            .rx_afull_clk(rx_afull_clk),              //INPUT  : AFull Status Clock
1449 
                .rx_afull_data(rx_afull_data),            //INPUT  : AFull Status Data
1450 
                .rx_afull_valid(rx_afull_valid),          //INPUT  : AFull Status Valid
1451 
                .rx_afull_channel(rx_afull_channel),      //INPUT  : AFull Status Channel
1452 
 
1453 
             // Channel 0
1454 
 
1455 
                .rx_clk_0(rx_clk_0),                      //INPUT  : MAC RX CLK
1456 
                .tx_clk_0(tx_clk_0),                      //INPUT  : MAC TX CLK
1457 
                .gm_rx_d_0(gm_rx_d_0),                    //INPUT  : GMII RX DATA
1458 
                .gm_rx_dv_0(gm_rx_dv_0),                  //INPUT  : GMII RX VALID INDICATION
1459 
                .gm_rx_err_0(gm_rx_err_0),                //INPUT  : GMII RX ERROR INDICATION
1460 
                .gm_tx_d_0(gm_tx_d_0),                    //OUTPUT : GMII TX DATA
1461 
                .gm_tx_en_0(gm_tx_en_0),                  //OUTPUT : GMII TX VALID INDICATION
1462 
                .gm_tx_err_0(gm_tx_err_0),                //OUTPUT : GMII TX ERROR INDICATION
1463 
                .m_rx_crs_0(m_rx_crs_0),                  //INPUT  : MII RX CARRIER SENSE
1464 
                .m_rx_col_0(m_rx_col_0),                  //INPUT  : MII RX COLLISION
1465 
                .m_rx_d_0(m_rx_d_0),                      //INPUT  : MII RX DATA
1466 
                .m_rx_en_0(m_rx_en_0),                    //INPUT  : MII RX VALID INDICATION
1467 
                .m_rx_err_0(m_rx_err_0),                  //INPUT  : MII RX ERROR INDICATION
1468 
                .m_tx_d_0(m_tx_d_0),                      //OUTPUT : MII TX DATA
1469 
                .m_tx_en_0(m_tx_en_0),                    //OUTPUT : MII TX VALID INDICATION
1470 
                .m_tx_err_0(m_tx_err_0),                  //OUTPUT : MII TX ERROR INDICATION
1471 
                .rx_control_0(rx_control_0),              //INPUT  : RGMII RX CONTROL INDICATION
1472 
                .rgmii_in_0(rgmii_in_0),                  //INPUT  : RGMII RX DATA INDICATION
1473 
                .tx_control_0(tx_control_0),              //OUTPUT : RGMII TX CONTROL INDICATION
1474 
                .rgmii_out_0(rgmii_out_0),                //OUTPUT : RGMII TX DATA INDICATION
1475 
                .eth_mode_0(eth_mode_0),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1476 
                .ena_10_0(ena_10_0),                      //OUTPUT : SPEED 10 MBPS INDICATION
1477 
                .set_10_0(set_10_0),                      //INPUT  : SPEED 10 MBPS
1478 
                .set_1000_0(set_1000_0),                  //INPUT  : SPEED 1000 MBPS
1479 
                .mac_rx_clk_0(mac_rx_clk_0),              //OUTPUT : Av-ST Rx Clock
1480 
            .mac_tx_clk_0(mac_tx_clk_0),              //OUTPUT : Av-ST Tx Clock
1481 
                .data_rx_sop_0(data_rx_sop_0),            //OUTPUT : Start of Packet
1482 
                .data_rx_eop_0(data_rx_eop_0),            //OUTPUT : End of Packet
1483 
                .data_rx_data_0(data_rx_data_0),          //OUTPUT : Data from FIFO
1484 
                .data_rx_error_0(data_rx_error_0),        //OUTPUT : Receive packet error
1485 
                .data_rx_valid_0(data_rx_valid_0),        //OUTPUT : Data Receive FIFO Valid
1486 
                .data_rx_ready_0(data_rx_ready_0),        //OUTPUT : Data Receive Ready
1487 
                .pkt_class_data_0(pkt_class_data_0),      //OUTPUT : Frame Type Indication
1488 
                .pkt_class_valid_0(pkt_class_valid_0),    //OUTPUT : Frame Type Indication Valid
1489 
                .data_tx_error_0(data_tx_error_0),        //INPUT  : Status
1490 
                .data_tx_data_0(data_tx_data_0),          //INPUT  : Data from FIFO transmit
1491 
                .data_tx_valid_0(data_tx_valid_0),        //INPUT  : Data FIFO transmit Empty
1492 
                .data_tx_sop_0(data_tx_sop_0),            //INPUT  : Start of Packet
1493 
                .data_tx_eop_0(data_tx_eop_0),            //INPUT  : End of Packet
1494 
                .data_tx_ready_0(data_tx_ready_0),        //OUTPUT : Data FIFO transmit Read Enable
1495 
                .tx_ff_uflow_0(tx_ff_uflow_0),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1496 
                .tx_crc_fwd_0(tx_crc_fwd_0),              //INPUT  : Forward Current Frame with CRC from Application
1497 
                .xoff_gen_0(xoff_gen_0),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1498 
                .xon_gen_0(xon_gen_0),                    //INPUT  : XON PAUSE FRAME GENERATE
1499 
                .magic_sleep_n_0(magic_sleep_n_0),        //INPUT  : MAC SLEEP MODE CONTROL
1500 
                .magic_wakeup_0(magic_wakeup_0),          //OUTPUT : MAC WAKE-UP INDICATION
1501 
 
1502 
             // Channel 1
1503 
 
1504 
                .rx_clk_1(rx_clk_1),                      //INPUT  : MAC RX CLK
1505 
                .tx_clk_1(tx_clk_1),                      //INPUT  : MAC TX CLK
1506 
                .gm_rx_d_1(gm_rx_d_1),                    //INPUT  : GMII RX DATA
1507 
                .gm_rx_dv_1(gm_rx_dv_1),                  //INPUT  : GMII RX VALID INDICATION
1508 
                .gm_rx_err_1(gm_rx_err_1),                //INPUT  : GMII RX ERROR INDICATION
1509 
                .gm_tx_d_1(gm_tx_d_1),                    //OUTPUT : GMII TX DATA
1510 
                .gm_tx_en_1(gm_tx_en_1),                  //OUTPUT : GMII TX VALID INDICATION
1511 
                .gm_tx_err_1(gm_tx_err_1),                //OUTPUT : GMII TX ERROR INDICATION
1512 
                .m_rx_crs_1(m_rx_crs_1),                  //INPUT  : MII RX CARRIER SENSE
1513 
                .m_rx_col_1(m_rx_col_1),                  //INPUT  : MII RX COLLISION
1514 
                .m_rx_d_1(m_rx_d_1),                      //INPUT  : MII RX DATA
1515 
                .m_rx_en_1(m_rx_en_1),                    //INPUT  : MII RX VALID INDICATION
1516 
                .m_rx_err_1(m_rx_err_1),                  //INPUT  : MII RX ERROR INDICATION
1517 
                .m_tx_d_1(m_tx_d_1),                      //OUTPUT : MII TX DATA
1518 
                .m_tx_en_1(m_tx_en_1),                    //OUTPUT : MII TX VALID INDICATION
1519 
                .m_tx_err_1(m_tx_err_1),                  //OUTPUT : MII TX ERROR INDICATION
1520 
                .rx_control_1(rx_control_1),              //INPUT  : RGMII RX CONTROL INDICATION
1521 
                .rgmii_in_1(rgmii_in_1),                  //INPUT  : RGMII RX DATA INDICATION
1522 
                .tx_control_1(tx_control_1),              //OUTPUT : RGMII TX CONTROL INDICATION
1523 
                .rgmii_out_1(rgmii_out_1),                //OUTPUT : RGMII TX DATA INDICATION
1524 
                .eth_mode_1(eth_mode_1),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1525 
                .ena_10_1(ena_10_1),                      //OUTPUT : SPEED 10 MBPS INDICATION
1526 
                .set_10_1(set_10_1),                      //INPUT  : SPEED 10 MBPS
1527 
                .set_1000_1(set_1000_1),                  //INPUT  : SPEED 1000 MBPS
1528 
                .mac_rx_clk_1(mac_rx_clk_1),              //OUTPUT : Av-ST Rx Clock
1529 
            .mac_tx_clk_1(mac_tx_clk_1),              //OUTPUT : Av-ST Tx Clock
1530 
                .data_rx_sop_1(data_rx_sop_1),            //OUTPUT : Start of Packet
1531 
                .data_rx_eop_1(data_rx_eop_1),            //OUTPUT : End of Packet
1532 
                .data_rx_data_1(data_rx_data_1),          //OUTPUT : Data from FIFO
1533 
                .data_rx_error_1(data_rx_error_1),        //OUTPUT : Receive packet error
1534 
                .data_rx_valid_1(data_rx_valid_1),        //OUTPUT : Data Receive FIFO Valid
1535 
                .data_rx_ready_1(data_rx_ready_1),        //OUTPUT : Data Receive Ready
1536 
                .pkt_class_data_1(pkt_class_data_1),      //OUTPUT : Frame Type Indication
1537 
                .pkt_class_valid_1(pkt_class_valid_1),    //OUTPUT : Frame Type Indication Valid
1538 
                .data_tx_error_1(data_tx_error_1),        //INPUT  : Status
1539 
                .data_tx_data_1(data_tx_data_1),          //INPUT  : Data from FIFO transmit
1540 
                .data_tx_valid_1(data_tx_valid_1),        //INPUT  : Data FIFO transmit Empty
1541 
                .data_tx_sop_1(data_tx_sop_1),            //INPUT  : Start of Packet
1542 
                .data_tx_eop_1(data_tx_eop_1),            //INPUT  : End of Packet
1543 
                .data_tx_ready_1(data_tx_ready_1),        //OUTPUT : Data FIFO transmit Read Enable
1544 
                .tx_ff_uflow_1(tx_ff_uflow_1),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1545 
                .tx_crc_fwd_1(tx_crc_fwd_1),              //INPUT  : Forward Current Frame with CRC from Application
1546 
                .xoff_gen_1(xoff_gen_1),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1547 
                .xon_gen_1(xon_gen_1),                    //INPUT  : XON PAUSE FRAME GENERATE
1548 
                .magic_sleep_n_1(magic_sleep_n_1),        //INPUT  : MAC SLEEP MODE CONTROL
1549 
                .magic_wakeup_1(magic_wakeup_1),          //OUTPUT : MAC WAKE-UP INDICATION
1550 
 
1551 
             // Channel 2
1552 
 
1553 
                .rx_clk_2(rx_clk_2),                      //INPUT  : MAC RX CLK
1554 
                .tx_clk_2(tx_clk_2),                      //INPUT  : MAC TX CLK
1555 
                .gm_rx_d_2(gm_rx_d_2),                    //INPUT  : GMII RX DATA
1556 
                .gm_rx_dv_2(gm_rx_dv_2),                  //INPUT  : GMII RX VALID INDICATION
1557 
                .gm_rx_err_2(gm_rx_err_2),                //INPUT  : GMII RX ERROR INDICATION
1558 
                .gm_tx_d_2(gm_tx_d_2),                    //OUTPUT : GMII TX DATA
1559 
                .gm_tx_en_2(gm_tx_en_2),                  //OUTPUT : GMII TX VALID INDICATION
1560 
                .gm_tx_err_2(gm_tx_err_2),                //OUTPUT : GMII TX ERROR INDICATION
1561 
                .m_rx_crs_2(m_rx_crs_2),                  //INPUT  : MII RX CARRIER SENSE
1562 
                .m_rx_col_2(m_rx_col_2),                  //INPUT  : MII RX COLLISION
1563 
                .m_rx_d_2(m_rx_d_2),                      //INPUT  : MII RX DATA
1564 
                .m_rx_en_2(m_rx_en_2),                    //INPUT  : MII RX VALID INDICATION
1565 
                .m_rx_err_2(m_rx_err_2),                  //INPUT  : MII RX ERROR INDICATION
1566 
                .m_tx_d_2(m_tx_d_2),                      //OUTPUT : MII TX DATA
1567 
                .m_tx_en_2(m_tx_en_2),                    //OUTPUT : MII TX VALID INDICATION
1568 
                .m_tx_err_2(m_tx_err_2),                  //OUTPUT : MII TX ERROR INDICATION
1569 
                .rx_control_2(rx_control_2),              //INPUT  : RGMII RX CONTROL INDICATION
1570 
                .rgmii_in_2(rgmii_in_2),                  //INPUT  : RGMII RX DATA INDICATION
1571 
                .tx_control_2(tx_control_2),              //OUTPUT : RGMII TX CONTROL INDICATION
1572 
                .rgmii_out_2(rgmii_out_2),                //OUTPUT : RGMII TX DATA INDICATION
1573 
                .eth_mode_2(eth_mode_2),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1574 
                .ena_10_2(ena_10_2),                      //OUTPUT : SPEED 10 MBPS INDICATION
1575 
                .set_10_2(set_10_2),                      //INPUT  : SPEED 10 MBPS
1576 
                .set_1000_2(set_1000_2),                  //INPUT  : SPEED 1000 MBPS
1577 
                .mac_rx_clk_2(mac_rx_clk_2),              //OUTPUT : Av-ST Rx Clock
1578 
            .mac_tx_clk_2(mac_tx_clk_2),              //OUTPUT : Av-ST Tx Clock
1579 
                .data_rx_sop_2(data_rx_sop_2),            //OUTPUT : Start of Packet
1580 
                .data_rx_eop_2(data_rx_eop_2),            //OUTPUT : End of Packet
1581 
                .data_rx_data_2(data_rx_data_2),          //OUTPUT : Data from FIFO
1582 
                .data_rx_error_2(data_rx_error_2),        //OUTPUT : Receive packet error
1583 
                .data_rx_valid_2(data_rx_valid_2),        //OUTPUT : Data Receive FIFO Valid
1584 
                .data_rx_ready_2(data_rx_ready_2),        //OUTPUT : Data Receive Ready
1585 
                .pkt_class_data_2(pkt_class_data_2),      //OUTPUT : Frame Type Indication
1586 
                .pkt_class_valid_2(pkt_class_valid_2),    //OUTPUT : Frame Type Indication Valid
1587 
                .data_tx_error_2(data_tx_error_2),        //INPUT  : Status
1588 
                .data_tx_data_2(data_tx_data_2),          //INPUT  : Data from FIFO transmit
1589 
                .data_tx_valid_2(data_tx_valid_2),        //INPUT  : Data FIFO transmit Empty
1590 
                .data_tx_sop_2(data_tx_sop_2),            //INPUT  : Start of Packet
1591 
                .data_tx_eop_2(data_tx_eop_2),            //INPUT  : End of Packet
1592 
                .data_tx_ready_2(data_tx_ready_2),        //OUTPUT : Data FIFO transmit Read Enable
1593 
                .tx_ff_uflow_2(tx_ff_uflow_2),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1594 
                .tx_crc_fwd_2(tx_crc_fwd_2),              //INPUT  : Forward Current Frame with CRC from Application
1595 
                .xoff_gen_2(xoff_gen_2),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1596 
                .xon_gen_2(xon_gen_2),                    //INPUT  : XON PAUSE FRAME GENERATE
1597 
                .magic_sleep_n_2(magic_sleep_n_2),        //INPUT  : MAC SLEEP MODE CONTROL
1598 
                .magic_wakeup_2(magic_wakeup_2),          //OUTPUT : MAC WAKE-UP INDICATION
1599 
 
1600 
             // Channel 3
1601 
 
1602 
                .rx_clk_3(rx_clk_3),                      //INPUT  : MAC RX CLK
1603 
                .tx_clk_3(tx_clk_3),                      //INPUT  : MAC TX CLK
1604 
                .gm_rx_d_3(gm_rx_d_3),                    //INPUT  : GMII RX DATA
1605 
                .gm_rx_dv_3(gm_rx_dv_3),                  //INPUT  : GMII RX VALID INDICATION
1606 
                .gm_rx_err_3(gm_rx_err_3),                //INPUT  : GMII RX ERROR INDICATION
1607 
                .gm_tx_d_3(gm_tx_d_3),                    //OUTPUT : GMII TX DATA
1608 
                .gm_tx_en_3(gm_tx_en_3),                  //OUTPUT : GMII TX VALID INDICATION
1609 
                .gm_tx_err_3(gm_tx_err_3),                //OUTPUT : GMII TX ERROR INDICATION
1610 
                .m_rx_crs_3(m_rx_crs_3),                  //INPUT  : MII RX CARRIER SENSE
1611 
                .m_rx_col_3(m_rx_col_3),                  //INPUT  : MII RX COLLISION
1612 
                .m_rx_d_3(m_rx_d_3),                      //INPUT  : MII RX DATA
1613 
                .m_rx_en_3(m_rx_en_3),                    //INPUT  : MII RX VALID INDICATION
1614 
                .m_rx_err_3(m_rx_err_3),                  //INPUT  : MII RX ERROR INDICATION
1615 
                .m_tx_d_3(m_tx_d_3),                      //OUTPUT : MII TX DATA
1616 
                .m_tx_en_3(m_tx_en_3),                    //OUTPUT : MII TX VALID INDICATION
1617 
                .m_tx_err_3(m_tx_err_3),                  //OUTPUT : MII TX ERROR INDICATION
1618 
                .rx_control_3(rx_control_3),              //INPUT  : RGMII RX CONTROL INDICATION
1619 
                .rgmii_in_3(rgmii_in_3),                  //INPUT  : RGMII RX DATA INDICATION
1620 
                .tx_control_3(tx_control_3),              //OUTPUT : RGMII TX CONTROL INDICATION
1621 
                .rgmii_out_3(rgmii_out_3),                //OUTPUT : RGMII TX DATA INDICATION
1622 
                .eth_mode_3(eth_mode_3),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1623 
                .ena_10_3(ena_10_3),                      //OUTPUT : SPEED 10 MBPS INDICATION
1624 
                .set_10_3(set_10_3),                      //INPUT  : SPEED 10 MBPS
1625 
                .set_1000_3(set_1000_3),                  //INPUT  : SPEED 1000 MBPS
1626 
                .mac_rx_clk_3(mac_rx_clk_3),              //OUTPUT : Av-ST Rx Clock
1627 
            .mac_tx_clk_3(mac_tx_clk_3),              //OUTPUT : Av-ST Tx Clock
1628 
                .data_rx_sop_3(data_rx_sop_3),            //OUTPUT : Start of Packet
1629 
                .data_rx_eop_3(data_rx_eop_3),            //OUTPUT : End of Packet
1630 
                .data_rx_data_3(data_rx_data_3),          //OUTPUT : Data from FIFO
1631 
                .data_rx_error_3(data_rx_error_3),        //OUTPUT : Receive packet error
1632 
                .data_rx_valid_3(data_rx_valid_3),        //OUTPUT : Data Receive FIFO Valid
1633 
                .data_rx_ready_3(data_rx_ready_3),        //OUTPUT : Data Receive Ready
1634 
                .pkt_class_data_3(pkt_class_data_3),      //OUTPUT : Frame Type Indication
1635 
                .pkt_class_valid_3(pkt_class_valid_3),    //OUTPUT : Frame Type Indication Valid
1636 
                .data_tx_error_3(data_tx_error_3),        //INPUT  : Status
1637 
                .data_tx_data_3(data_tx_data_3),          //INPUT  : Data from FIFO transmit
1638 
                .data_tx_valid_3(data_tx_valid_3),        //INPUT  : Data FIFO transmit Empty
1639 
                .data_tx_sop_3(data_tx_sop_3),            //INPUT  : Start of Packet
1640 
                .data_tx_eop_3(data_tx_eop_3),            //INPUT  : End of Packet
1641 
                .data_tx_ready_3(data_tx_ready_3),        //OUTPUT : Data FIFO transmit Read Enable
1642 
                .tx_ff_uflow_3(tx_ff_uflow_3),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1643 
                .tx_crc_fwd_3(tx_crc_fwd_3),              //INPUT  : Forward Current Frame with CRC from Application
1644 
                .xoff_gen_3(xoff_gen_3),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1645 
                .xon_gen_3(xon_gen_3),                    //INPUT  : XON PAUSE FRAME GENERATE
1646 
                .magic_sleep_n_3(magic_sleep_n_3),        //INPUT  : MAC SLEEP MODE CONTROL
1647 
                .magic_wakeup_3(magic_wakeup_3),          //OUTPUT : MAC WAKE-UP INDICATION
1648 
 
1649 
             // Channel 4
1650 
 
1651 
                .rx_clk_4(rx_clk_4),                      //INPUT  : MAC RX CLK
1652 
                .tx_clk_4(tx_clk_4),                      //INPUT  : MAC TX CLK
1653 
                .gm_rx_d_4(gm_rx_d_4),                    //INPUT  : GMII RX DATA
1654 
                .gm_rx_dv_4(gm_rx_dv_4),                  //INPUT  : GMII RX VALID INDICATION
1655 
                .gm_rx_err_4(gm_rx_err_4),                //INPUT  : GMII RX ERROR INDICATION
1656 
                .gm_tx_d_4(gm_tx_d_4),                    //OUTPUT : GMII TX DATA
1657 
                .gm_tx_en_4(gm_tx_en_4),                  //OUTPUT : GMII TX VALID INDICATION
1658 
                .gm_tx_err_4(gm_tx_err_4),                //OUTPUT : GMII TX ERROR INDICATION
1659 
                .m_rx_crs_4(m_rx_crs_4),                  //INPUT  : MII RX CARRIER SENSE
1660 
                .m_rx_col_4(m_rx_col_4),                  //INPUT  : MII RX COLLISION
1661 
                .m_rx_d_4(m_rx_d_4),                      //INPUT  : MII RX DATA
1662 
                .m_rx_en_4(m_rx_en_4),                    //INPUT  : MII RX VALID INDICATION
1663 
                .m_rx_err_4(m_rx_err_4),                  //INPUT  : MII RX ERROR INDICATION
1664 
                .m_tx_d_4(m_tx_d_4),                      //OUTPUT : MII TX DATA
1665 
                .m_tx_en_4(m_tx_en_4),                    //OUTPUT : MII TX VALID INDICATION
1666 
                .m_tx_err_4(m_tx_err_4),                  //OUTPUT : MII TX ERROR INDICATION
1667 
                .rx_control_4(rx_control_4),              //INPUT  : RGMII RX CONTROL INDICATION
1668 
                .rgmii_in_4(rgmii_in_4),                  //INPUT  : RGMII RX DATA INDICATION
1669 
                .tx_control_4(tx_control_4),              //OUTPUT : RGMII TX CONTROL INDICATION
1670 
                .rgmii_out_4(rgmii_out_4),                //OUTPUT : RGMII TX DATA INDICATION
1671 
                .eth_mode_4(eth_mode_4),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1672 
                .ena_10_4(ena_10_4),                      //OUTPUT : SPEED 10 MBPS INDICATION
1673 
                .set_10_4(set_10_4),                      //INPUT  : SPEED 10 MBPS
1674 
                .set_1000_4(set_1000_4),                  //INPUT  : SPEED 1000 MBPS
1675 
                .mac_rx_clk_4(mac_rx_clk_4),              //OUTPUT : Av-ST Rx Clock
1676 
            .mac_tx_clk_4(mac_tx_clk_4),              //OUTPUT : Av-ST Tx Clock
1677 
                .data_rx_sop_4(data_rx_sop_4),            //OUTPUT : Start of Packet
1678 
                .data_rx_eop_4(data_rx_eop_4),            //OUTPUT : End of Packet
1679 
                .data_rx_data_4(data_rx_data_4),          //OUTPUT : Data from FIFO
1680 
                .data_rx_error_4(data_rx_error_4),        //OUTPUT : Receive packet error
1681 
                .data_rx_valid_4(data_rx_valid_4),        //OUTPUT : Data Receive FIFO Valid
1682 
                .data_rx_ready_4(data_rx_ready_4),        //OUTPUT : Data Receive Ready
1683 
                .pkt_class_data_4(pkt_class_data_4),      //OUTPUT : Frame Type Indication
1684 
                .pkt_class_valid_4(pkt_class_valid_4),    //OUTPUT : Frame Type Indication Valid
1685 
                .data_tx_error_4(data_tx_error_4),        //INPUT  : Status
1686 
                .data_tx_data_4(data_tx_data_4),          //INPUT  : Data from FIFO transmit
1687 
                .data_tx_valid_4(data_tx_valid_4),        //INPUT  : Data FIFO transmit Empty
1688 
                .data_tx_sop_4(data_tx_sop_4),            //INPUT  : Start of Packet
1689 
                .data_tx_eop_4(data_tx_eop_4),            //INPUT  : End of Packet
1690 
                .data_tx_ready_4(data_tx_ready_4),        //OUTPUT : Data FIFO transmit Read Enable
1691 
                .tx_ff_uflow_4(tx_ff_uflow_4),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1692 
                .tx_crc_fwd_4(tx_crc_fwd_4),              //INPUT  : Forward Current Frame with CRC from Application
1693 
                .xoff_gen_4(xoff_gen_4),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1694 
                .xon_gen_4(xon_gen_4),                    //INPUT  : XON PAUSE FRAME GENERATE
1695 
                .magic_sleep_n_4(magic_sleep_n_4),        //INPUT  : MAC SLEEP MODE CONTROL
1696 
                .magic_wakeup_4(magic_wakeup_4),          //OUTPUT : MAC WAKE-UP INDICATION
1697 
 
1698 
             // Channel 5
1699 
 
1700 
                .rx_clk_5(rx_clk_5),                      //INPUT  : MAC RX CLK
1701 
                .tx_clk_5(tx_clk_5),                      //INPUT  : MAC TX CLK
1702 
                .gm_rx_d_5(gm_rx_d_5),                    //INPUT  : GMII RX DATA
1703 
                .gm_rx_dv_5(gm_rx_dv_5),                  //INPUT  : GMII RX VALID INDICATION
1704 
                .gm_rx_err_5(gm_rx_err_5),                //INPUT  : GMII RX ERROR INDICATION
1705 
                .gm_tx_d_5(gm_tx_d_5),                    //OUTPUT : GMII TX DATA
1706 
                .gm_tx_en_5(gm_tx_en_5),                  //OUTPUT : GMII TX VALID INDICATION
1707 
                .gm_tx_err_5(gm_tx_err_5),                //OUTPUT : GMII TX ERROR INDICATION
1708 
                .m_rx_crs_5(m_rx_crs_5),                  //INPUT  : MII RX CARRIER SENSE
1709 
                .m_rx_col_5(m_rx_col_5),                  //INPUT  : MII RX COLLISION
1710 
                .m_rx_d_5(m_rx_d_5),                      //INPUT  : MII RX DATA
1711 
                .m_rx_en_5(m_rx_en_5),                    //INPUT  : MII RX VALID INDICATION
1712 
                .m_rx_err_5(m_rx_err_5),                  //INPUT  : MII RX ERROR INDICATION
1713 
                .m_tx_d_5(m_tx_d_5),                      //OUTPUT : MII TX DATA
1714 
                .m_tx_en_5(m_tx_en_5),                    //OUTPUT : MII TX VALID INDICATION
1715 
                .m_tx_err_5(m_tx_err_5),                  //OUTPUT : MII TX ERROR INDICATION
1716 
                .rx_control_5(rx_control_5),              //INPUT  : RGMII RX CONTROL INDICATION
1717 
                .rgmii_in_5(rgmii_in_5),                  //INPUT  : RGMII RX DATA INDICATION
1718 
                .tx_control_5(tx_control_5),              //OUTPUT : RGMII TX CONTROL INDICATION
1719 
                .rgmii_out_5(rgmii_out_5),                //OUTPUT : RGMII TX DATA INDICATION
1720 
                .eth_mode_5(eth_mode_5),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1721 
                .ena_10_5(ena_10_5),                      //OUTPUT : SPEED 10 MBPS INDICATION
1722 
                .set_10_5(set_10_5),                      //INPUT  : SPEED 10 MBPS
1723 
                .set_1000_5(set_1000_5),                  //INPUT  : SPEED 1000 MBPS
1724 
                .mac_rx_clk_5(mac_rx_clk_5),              //OUTPUT : Av-ST Rx Clock
1725 
            .mac_tx_clk_5(mac_tx_clk_5),              //OUTPUT : Av-ST Tx Clock
1726 
                .data_rx_sop_5(data_rx_sop_5),            //OUTPUT : Start of Packet
1727 
                .data_rx_eop_5(data_rx_eop_5),            //OUTPUT : End of Packet
1728 
                .data_rx_data_5(data_rx_data_5),          //OUTPUT : Data from FIFO
1729 
                .data_rx_error_5(data_rx_error_5),        //OUTPUT : Receive packet error
1730 
                .data_rx_valid_5(data_rx_valid_5),        //OUTPUT : Data Receive FIFO Valid
1731 
                .data_rx_ready_5(data_rx_ready_5),        //OUTPUT : Data Receive Ready
1732 
                .pkt_class_data_5(pkt_class_data_5),      //OUTPUT : Frame Type Indication
1733 
                .pkt_class_valid_5(pkt_class_valid_5),    //OUTPUT : Frame Type Indication Valid
1734 
                .data_tx_error_5(data_tx_error_5),        //INPUT  : Status
1735 
                .data_tx_data_5(data_tx_data_5),          //INPUT  : Data from FIFO transmit
1736 
                .data_tx_valid_5(data_tx_valid_5),        //INPUT  : Data FIFO transmit Empty
1737 
                .data_tx_sop_5(data_tx_sop_5),            //INPUT  : Start of Packet
1738 
                .data_tx_eop_5(data_tx_eop_5),            //INPUT  : End of Packet
1739 
                .data_tx_ready_5(data_tx_ready_5),        //OUTPUT : Data FIFO transmit Read Enable
1740 
                .tx_ff_uflow_5(tx_ff_uflow_5),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1741 
                .tx_crc_fwd_5(tx_crc_fwd_5),              //INPUT  : Forward Current Frame with CRC from Application
1742 
                .xoff_gen_5(xoff_gen_5),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1743 
                .xon_gen_5(xon_gen_5),                    //INPUT  : XON PAUSE FRAME GENERATE
1744 
                .magic_sleep_n_5(magic_sleep_n_5),        //INPUT  : MAC SLEEP MODE CONTROL
1745 
                .magic_wakeup_5(magic_wakeup_5),          //OUTPUT : MAC WAKE-UP INDICATION
1746 
 
1747 
             // Channel 6
1748 
 
1749 
                .rx_clk_6(rx_clk_6),                      //INPUT  : MAC RX CLK
1750 
                .tx_clk_6(tx_clk_6),                      //INPUT  : MAC TX CLK
1751 
                .gm_rx_d_6(gm_rx_d_6),                    //INPUT  : GMII RX DATA
1752 
                .gm_rx_dv_6(gm_rx_dv_6),                  //INPUT  : GMII RX VALID INDICATION
1753 
                .gm_rx_err_6(gm_rx_err_6),                //INPUT  : GMII RX ERROR INDICATION
1754 
                .gm_tx_d_6(gm_tx_d_6),                    //OUTPUT : GMII TX DATA
1755 
                .gm_tx_en_6(gm_tx_en_6),                  //OUTPUT : GMII TX VALID INDICATION
1756 
                .gm_tx_err_6(gm_tx_err_6),                //OUTPUT : GMII TX ERROR INDICATION
1757 
                .m_rx_crs_6(m_rx_crs_6),                  //INPUT  : MII RX CARRIER SENSE
1758 
                .m_rx_col_6(m_rx_col_6),                  //INPUT  : MII RX COLLISION
1759 
                .m_rx_d_6(m_rx_d_6),                      //INPUT  : MII RX DATA
1760 
                .m_rx_en_6(m_rx_en_6),                    //INPUT  : MII RX VALID INDICATION
1761 
                .m_rx_err_6(m_rx_err_6),                  //INPUT  : MII RX ERROR INDICATION
1762 
                .m_tx_d_6(m_tx_d_6),                      //OUTPUT : MII TX DATA
1763 
                .m_tx_en_6(m_tx_en_6),                    //OUTPUT : MII TX VALID INDICATION
1764 
                .m_tx_err_6(m_tx_err_6),                  //OUTPUT : MII TX ERROR INDICATION
1765 
                .rx_control_6(rx_control_6),              //INPUT  : RGMII RX CONTROL INDICATION
1766 
                .rgmii_in_6(rgmii_in_6),                  //INPUT  : RGMII RX DATA INDICATION
1767 
                .tx_control_6(tx_control_6),              //OUTPUT : RGMII TX CONTROL INDICATION
1768 
                .rgmii_out_6(rgmii_out_6),                //OUTPUT : RGMII TX DATA INDICATION
1769 
                .eth_mode_6(eth_mode_6),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1770 
                .ena_10_6(ena_10_6),                      //OUTPUT : SPEED 10 MBPS INDICATION
1771 
                .set_10_6(set_10_6),                      //INPUT  : SPEED 10 MBPS
1772 
                .set_1000_6(set_1000_6),                  //INPUT  : SPEED 1000 MBPS
1773 
                .mac_rx_clk_6(mac_rx_clk_6),              //OUTPUT : Av-ST Rx Clock
1774 
            .mac_tx_clk_6(mac_tx_clk_6),              //OUTPUT : Av-ST Tx Clock
1775 
                .data_rx_sop_6(data_rx_sop_6),            //OUTPUT : Start of Packet
1776 
                .data_rx_eop_6(data_rx_eop_6),            //OUTPUT : End of Packet
1777 
                .data_rx_data_6(data_rx_data_6),          //OUTPUT : Data from FIFO
1778 
                .data_rx_error_6(data_rx_error_6),        //OUTPUT : Receive packet error
1779 
                .data_rx_valid_6(data_rx_valid_6),        //OUTPUT : Data Receive FIFO Valid
1780 
                .data_rx_ready_6(data_rx_ready_6),        //OUTPUT : Data Receive Ready
1781 
                .pkt_class_data_6(pkt_class_data_6),      //OUTPUT : Frame Type Indication
1782 
                .pkt_class_valid_6(pkt_class_valid_6),    //OUTPUT : Frame Type Indication Valid
1783 
                .data_tx_error_6(data_tx_error_6),        //INPUT  : Status
1784 
                .data_tx_data_6(data_tx_data_6),          //INPUT  : Data from FIFO transmit
1785 
                .data_tx_valid_6(data_tx_valid_6),        //INPUT  : Data FIFO transmit Empty
1786 
                .data_tx_sop_6(data_tx_sop_6),            //INPUT  : Start of Packet
1787 
                .data_tx_eop_6(data_tx_eop_6),            //INPUT  : End of Packet
1788 
                .data_tx_ready_6(data_tx_ready_6),        //OUTPUT : Data FIFO transmit Read Enable
1789 
                .tx_ff_uflow_6(tx_ff_uflow_6),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1790 
                .tx_crc_fwd_6(tx_crc_fwd_6),              //INPUT  : Forward Current Frame with CRC from Application
1791 
                .xoff_gen_6(xoff_gen_6),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1792 
                .xon_gen_6(xon_gen_6),                    //INPUT  : XON PAUSE FRAME GENERATE
1793 
                .magic_sleep_n_6(magic_sleep_n_6),        //INPUT  : MAC SLEEP MODE CONTROL
1794 
                .magic_wakeup_6(magic_wakeup_6),          //OUTPUT : MAC WAKE-UP INDICATION
1795 
 
1796 
             // Channel 7
1797 
 
1798 
                .rx_clk_7(rx_clk_7),                      //INPUT  : MAC RX CLK
1799 
                .tx_clk_7(tx_clk_7),                      //INPUT  : MAC TX CLK
1800 
                .gm_rx_d_7(gm_rx_d_7),                    //INPUT  : GMII RX DATA
1801 
                .gm_rx_dv_7(gm_rx_dv_7),                  //INPUT  : GMII RX VALID INDICATION
1802 
                .gm_rx_err_7(gm_rx_err_7),                //INPUT  : GMII RX ERROR INDICATION
1803 
                .gm_tx_d_7(gm_tx_d_7),                    //OUTPUT : GMII TX DATA
1804 
                .gm_tx_en_7(gm_tx_en_7),                  //OUTPUT : GMII TX VALID INDICATION
1805 
                .gm_tx_err_7(gm_tx_err_7),                //OUTPUT : GMII TX ERROR INDICATION
1806 
                .m_rx_crs_7(m_rx_crs_7),                  //INPUT  : MII RX CARRIER SENSE
1807 
                .m_rx_col_7(m_rx_col_7),                  //INPUT  : MII RX COLLISION
1808 
                .m_rx_d_7(m_rx_d_7),                      //INPUT  : MII RX DATA
1809 
                .m_rx_en_7(m_rx_en_7),                    //INPUT  : MII RX VALID INDICATION
1810 
                .m_rx_err_7(m_rx_err_7),                  //INPUT  : MII RX ERROR INDICATION
1811 
                .m_tx_d_7(m_tx_d_7),                      //OUTPUT : MII TX DATA
1812 
                .m_tx_en_7(m_tx_en_7),                    //OUTPUT : MII TX VALID INDICATION
1813 
                .m_tx_err_7(m_tx_err_7),                  //OUTPUT : MII TX ERROR INDICATION
1814 
                .rx_control_7(rx_control_7),              //INPUT  : RGMII RX CONTROL INDICATION
1815 
                .rgmii_in_7(rgmii_in_7),                  //INPUT  : RGMII RX DATA INDICATION
1816 
                .tx_control_7(tx_control_7),              //OUTPUT : RGMII TX CONTROL INDICATION
1817 
                .rgmii_out_7(rgmii_out_7),                //OUTPUT : RGMII TX DATA INDICATION
1818 
                .eth_mode_7(eth_mode_7),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1819 
                .ena_10_7(ena_10_7),                      //OUTPUT : SPEED 10 MBPS INDICATION
1820 
                .set_10_7(set_10_7),                      //INPUT  : SPEED 10 MBPS
1821 
                .set_1000_7(set_1000_7),                  //INPUT  : SPEED 1000 MBPS
1822 
                .mac_rx_clk_7(mac_rx_clk_7),              //OUTPUT : Av-ST Rx Clock
1823 
            .mac_tx_clk_7(mac_tx_clk_7),              //OUTPUT : Av-ST Tx Clock
1824 
                .data_rx_sop_7(data_rx_sop_7),            //OUTPUT : Start of Packet
1825 
                .data_rx_eop_7(data_rx_eop_7),            //OUTPUT : End of Packet
1826 
                .data_rx_data_7(data_rx_data_7),          //OUTPUT : Data from FIFO
1827 
                .data_rx_error_7(data_rx_error_7),        //OUTPUT : Receive packet error
1828 
                .data_rx_valid_7(data_rx_valid_7),        //OUTPUT : Data Receive FIFO Valid
1829 
                .data_rx_ready_7(data_rx_ready_7),        //OUTPUT : Data Receive Ready
1830 
                .pkt_class_data_7(pkt_class_data_7),      //OUTPUT : Frame Type Indication
1831 
                .pkt_class_valid_7(pkt_class_valid_7),    //OUTPUT : Frame Type Indication Valid
1832 
                .data_tx_error_7(data_tx_error_7),        //INPUT  : Status
1833 
                .data_tx_data_7(data_tx_data_7),          //INPUT  : Data from FIFO transmit
1834 
                .data_tx_valid_7(data_tx_valid_7),        //INPUT  : Data FIFO transmit Empty
1835 
                .data_tx_sop_7(data_tx_sop_7),            //INPUT  : Start of Packet
1836 
                .data_tx_eop_7(data_tx_eop_7),            //INPUT  : End of Packet
1837 
                .data_tx_ready_7(data_tx_ready_7),        //OUTPUT : Data FIFO transmit Read Enable
1838 
                .tx_ff_uflow_7(tx_ff_uflow_7),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1839 
                .tx_crc_fwd_7(tx_crc_fwd_7),              //INPUT  : Forward Current Frame with CRC from Application
1840 
                .xoff_gen_7(xoff_gen_7),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1841 
                .xon_gen_7(xon_gen_7),                    //INPUT  : XON PAUSE FRAME GENERATE
1842 
                .magic_sleep_n_7(magic_sleep_n_7),        //INPUT  : MAC SLEEP MODE CONTROL
1843 
                .magic_wakeup_7(magic_wakeup_7),          //OUTPUT : MAC WAKE-UP INDICATION
1844 
 
1845 
             // Channel 8
1846 
 
1847 
                .rx_clk_8(rx_clk_8),                      //INPUT  : MAC RX CLK
1848 
                .tx_clk_8(tx_clk_8),                      //INPUT  : MAC TX CLK
1849 
                .gm_rx_d_8(gm_rx_d_8),                    //INPUT  : GMII RX DATA
1850 
                .gm_rx_dv_8(gm_rx_dv_8),                  //INPUT  : GMII RX VALID INDICATION
1851 
                .gm_rx_err_8(gm_rx_err_8),                //INPUT  : GMII RX ERROR INDICATION
1852 
                .gm_tx_d_8(gm_tx_d_8),                    //OUTPUT : GMII TX DATA
1853 
                .gm_tx_en_8(gm_tx_en_8),                  //OUTPUT : GMII TX VALID INDICATION
1854 
                .gm_tx_err_8(gm_tx_err_8),                //OUTPUT : GMII TX ERROR INDICATION
1855 
                .m_rx_crs_8(m_rx_crs_8),                  //INPUT  : MII RX CARRIER SENSE
1856 
                .m_rx_col_8(m_rx_col_8),                  //INPUT  : MII RX COLLISION
1857 
                .m_rx_d_8(m_rx_d_8),                      //INPUT  : MII RX DATA
1858 
                .m_rx_en_8(m_rx_en_8),                    //INPUT  : MII RX VALID INDICATION
1859 
                .m_rx_err_8(m_rx_err_8),                  //INPUT  : MII RX ERROR INDICATION
1860 
                .m_tx_d_8(m_tx_d_8),                      //OUTPUT : MII TX DATA
1861 
                .m_tx_en_8(m_tx_en_8),                    //OUTPUT : MII TX VALID INDICATION
1862 
                .m_tx_err_8(m_tx_err_8),                  //OUTPUT : MII TX ERROR INDICATION
1863 
                .rx_control_8(rx_control_8),              //INPUT  : RGMII RX CONTROL INDICATION
1864 
                .rgmii_in_8(rgmii_in_8),                  //INPUT  : RGMII RX DATA INDICATION
1865 
                .tx_control_8(tx_control_8),              //OUTPUT : RGMII TX CONTROL INDICATION
1866 
                .rgmii_out_8(rgmii_out_8),                //OUTPUT : RGMII TX DATA INDICATION
1867 
                .eth_mode_8(eth_mode_8),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1868 
                .ena_10_8(ena_10_8),                      //OUTPUT : SPEED 10 MBPS INDICATION
1869 
                .set_10_8(set_10_8),                      //INPUT  : SPEED 10 MBPS
1870 
                .set_1000_8(set_1000_8),                  //INPUT  : SPEED 1000 MBPS
1871 
                .mac_rx_clk_8(mac_rx_clk_8),              //OUTPUT : Av-ST Rx Clock
1872 
            .mac_tx_clk_8(mac_tx_clk_8),              //OUTPUT : Av-ST Tx Clock
1873 
                .data_rx_sop_8(data_rx_sop_8),            //OUTPUT : Start of Packet
1874 
                .data_rx_eop_8(data_rx_eop_8),            //OUTPUT : End of Packet
1875 
                .data_rx_data_8(data_rx_data_8),          //OUTPUT : Data from FIFO
1876 
                .data_rx_error_8(data_rx_error_8),        //OUTPUT : Receive packet error
1877 
                .data_rx_valid_8(data_rx_valid_8),        //OUTPUT : Data Receive FIFO Valid
1878 
                .data_rx_ready_8(data_rx_ready_8),        //OUTPUT : Data Receive Ready
1879 
                .pkt_class_data_8(pkt_class_data_8),      //OUTPUT : Frame Type Indication
1880 
                .pkt_class_valid_8(pkt_class_valid_8),    //OUTPUT : Frame Type Indication Valid
1881 
                .data_tx_error_8(data_tx_error_8),        //INPUT  : Status
1882 
                .data_tx_data_8(data_tx_data_8),          //INPUT  : Data from FIFO transmit
1883 
                .data_tx_valid_8(data_tx_valid_8),        //INPUT  : Data FIFO transmit Empty
1884 
                .data_tx_sop_8(data_tx_sop_8),            //INPUT  : Start of Packet
1885 
                .data_tx_eop_8(data_tx_eop_8),            //INPUT  : End of Packet
1886 
                .data_tx_ready_8(data_tx_ready_8),        //OUTPUT : Data FIFO transmit Read Enable
1887 
                .tx_ff_uflow_8(tx_ff_uflow_8),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1888 
                .tx_crc_fwd_8(tx_crc_fwd_8),              //INPUT  : Forward Current Frame with CRC from Application
1889 
                .xoff_gen_8(xoff_gen_8),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1890 
                .xon_gen_8(xon_gen_8),                    //INPUT  : XON PAUSE FRAME GENERATE
1891 
                .magic_sleep_n_8(magic_sleep_n_8),        //INPUT  : MAC SLEEP MODE CONTROL
1892 
                .magic_wakeup_8(magic_wakeup_8),          //OUTPUT : MAC WAKE-UP INDICATION
1893 
 
1894 
             // Channel 9
1895 
 
1896 
                .rx_clk_9(rx_clk_9),                      //INPUT  : MAC RX CLK
1897 
                .tx_clk_9(tx_clk_9),                      //INPUT  : MAC TX CLK
1898 
                .gm_rx_d_9(gm_rx_d_9),                    //INPUT  : GMII RX DATA
1899 
                .gm_rx_dv_9(gm_rx_dv_9),                  //INPUT  : GMII RX VALID INDICATION
1900 
                .gm_rx_err_9(gm_rx_err_9),                //INPUT  : GMII RX ERROR INDICATION
1901 
                .gm_tx_d_9(gm_tx_d_9),                    //OUTPUT : GMII TX DATA
1902 
                .gm_tx_en_9(gm_tx_en_9),                  //OUTPUT : GMII TX VALID INDICATION
1903 
                .gm_tx_err_9(gm_tx_err_9),                //OUTPUT : GMII TX ERROR INDICATION
1904 
                .m_rx_crs_9(m_rx_crs_9),                  //INPUT  : MII RX CARRIER SENSE
1905 
                .m_rx_col_9(m_rx_col_9),                  //INPUT  : MII RX COLLISION
1906 
                .m_rx_d_9(m_rx_d_9),                      //INPUT  : MII RX DATA
1907 
                .m_rx_en_9(m_rx_en_9),                    //INPUT  : MII RX VALID INDICATION
1908 
                .m_rx_err_9(m_rx_err_9),                  //INPUT  : MII RX ERROR INDICATION
1909 
                .m_tx_d_9(m_tx_d_9),                      //OUTPUT : MII TX DATA
1910 
                .m_tx_en_9(m_tx_en_9),                    //OUTPUT : MII TX VALID INDICATION
1911 
                .m_tx_err_9(m_tx_err_9),                  //OUTPUT : MII TX ERROR INDICATION
1912 
                .rx_control_9(rx_control_9),              //INPUT  : RGMII RX CONTROL INDICATION
1913 
                .rgmii_in_9(rgmii_in_9),                  //INPUT  : RGMII RX DATA INDICATION
1914 
                .tx_control_9(tx_control_9),              //OUTPUT : RGMII TX CONTROL INDICATION
1915 
                .rgmii_out_9(rgmii_out_9),                //OUTPUT : RGMII TX DATA INDICATION
1916 
                .eth_mode_9(eth_mode_9),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1917 
                .ena_10_9(ena_10_9),                      //OUTPUT : SPEED 10 MBPS INDICATION
1918 
                .set_10_9(set_10_9),                      //INPUT  : SPEED 10 MBPS
1919 
                .set_1000_9(set_1000_9),                  //INPUT  : SPEED 1000 MBPS
1920 
                .mac_rx_clk_9(mac_rx_clk_9),              //OUTPUT : Av-ST Rx Clock
1921 
            .mac_tx_clk_9(mac_tx_clk_9),              //OUTPUT : Av-ST Tx Clock
1922 
                .data_rx_sop_9(data_rx_sop_9),            //OUTPUT : Start of Packet
1923 
                .data_rx_eop_9(data_rx_eop_9),            //OUTPUT : End of Packet
1924 
                .data_rx_data_9(data_rx_data_9),          //OUTPUT : Data from FIFO
1925 
                .data_rx_error_9(data_rx_error_9),        //OUTPUT : Receive packet error
1926 
                .data_rx_valid_9(data_rx_valid_9),        //OUTPUT : Data Receive FIFO Valid
1927 
                .data_rx_ready_9(data_rx_ready_9),        //OUTPUT : Data Receive Ready
1928 
                .pkt_class_data_9(pkt_class_data_9),      //OUTPUT : Frame Type Indication
1929 
                .pkt_class_valid_9(pkt_class_valid_9),    //OUTPUT : Frame Type Indication Valid
1930 
                .data_tx_error_9(data_tx_error_9),        //INPUT  : Status
1931 
                .data_tx_data_9(data_tx_data_9),          //INPUT  : Data from FIFO transmit
1932 
                .data_tx_valid_9(data_tx_valid_9),        //INPUT  : Data FIFO transmit Empty
1933 
                .data_tx_sop_9(data_tx_sop_9),            //INPUT  : Start of Packet
1934 
                .data_tx_eop_9(data_tx_eop_9),            //INPUT  : End of Packet
1935 
                .data_tx_ready_9(data_tx_ready_9),        //OUTPUT : Data FIFO transmit Read Enable
1936 
                .tx_ff_uflow_9(tx_ff_uflow_9),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1937 
                .tx_crc_fwd_9(tx_crc_fwd_9),              //INPUT  : Forward Current Frame with CRC from Application
1938 
                .xoff_gen_9(xoff_gen_9),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1939 
                .xon_gen_9(xon_gen_9),                    //INPUT  : XON PAUSE FRAME GENERATE
1940 
                .magic_sleep_n_9(magic_sleep_n_9),        //INPUT  : MAC SLEEP MODE CONTROL
1941 
                .magic_wakeup_9(magic_wakeup_9),          //OUTPUT : MAC WAKE-UP INDICATION
1942 
 
1943 
             // Channel 10
1944 
 
1945 
                .rx_clk_10(rx_clk_10),                      //INPUT  : MAC RX CLK
1946 
                .tx_clk_10(tx_clk_10),                      //INPUT  : MAC TX CLK
1947 
                .gm_rx_d_10(gm_rx_d_10),                    //INPUT  : GMII RX DATA
1948 
                .gm_rx_dv_10(gm_rx_dv_10),                  //INPUT  : GMII RX VALID INDICATION
1949 
                .gm_rx_err_10(gm_rx_err_10),                //INPUT  : GMII RX ERROR INDICATION
1950 
                .gm_tx_d_10(gm_tx_d_10),                    //OUTPUT : GMII TX DATA
1951 
                .gm_tx_en_10(gm_tx_en_10),                  //OUTPUT : GMII TX VALID INDICATION
1952 
                .gm_tx_err_10(gm_tx_err_10),                //OUTPUT : GMII TX ERROR INDICATION
1953 
                .m_rx_crs_10(m_rx_crs_10),                  //INPUT  : MII RX CARRIER SENSE
1954 
                .m_rx_col_10(m_rx_col_10),                  //INPUT  : MII RX COLLISION
1955 
                .m_rx_d_10(m_rx_d_10),                      //INPUT  : MII RX DATA
1956 
                .m_rx_en_10(m_rx_en_10),                    //INPUT  : MII RX VALID INDICATION
1957 
                .m_rx_err_10(m_rx_err_10),                  //INPUT  : MII RX ERROR INDICATION
1958 
                .m_tx_d_10(m_tx_d_10),                      //OUTPUT : MII TX DATA
1959 
                .m_tx_en_10(m_tx_en_10),                    //OUTPUT : MII TX VALID INDICATION
1960 
                .m_tx_err_10(m_tx_err_10),                  //OUTPUT : MII TX ERROR INDICATION
1961 
                .rx_control_10(rx_control_10),              //INPUT  : RGMII RX CONTROL INDICATION
1962 
                .rgmii_in_10(rgmii_in_10),                  //INPUT  : RGMII RX DATA INDICATION
1963 
                .tx_control_10(tx_control_10),              //OUTPUT : RGMII TX CONTROL INDICATION
1964 
                .rgmii_out_10(rgmii_out_10),                //OUTPUT : RGMII TX DATA INDICATION
1965 
                .eth_mode_10(eth_mode_10),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
1966 
                .ena_10_10(ena_10_10),                      //OUTPUT : SPEED 10 MBPS INDICATION
1967 
                .set_10_10(set_10_10),                      //INPUT  : SPEED 10 MBPS
1968 
                .set_1000_10(set_1000_10),                  //INPUT  : SPEED 1000 MBPS
1969 
                .mac_rx_clk_10(mac_rx_clk_10),              //OUTPUT : Av-ST Rx Clock
1970 
            .mac_tx_clk_10(mac_tx_clk_10),              //OUTPUT : Av-ST Tx Clock
1971 
                .data_rx_sop_10(data_rx_sop_10),            //OUTPUT : Start of Packet
1972 
                .data_rx_eop_10(data_rx_eop_10),            //OUTPUT : End of Packet
1973 
                .data_rx_data_10(data_rx_data_10),          //OUTPUT : Data from FIFO
1974 
                .data_rx_error_10(data_rx_error_10),        //OUTPUT : Receive packet error
1975 
                .data_rx_valid_10(data_rx_valid_10),        //OUTPUT : Data Receive FIFO Valid
1976 
                .data_rx_ready_10(data_rx_ready_10),        //OUTPUT : Data Receive Ready
1977 
                .pkt_class_data_10(pkt_class_data_10),      //OUTPUT : Frame Type Indication
1978 
                .pkt_class_valid_10(pkt_class_valid_10),    //OUTPUT : Frame Type Indication Valid
1979 
                .data_tx_error_10(data_tx_error_10),        //INPUT  : Status
1980 
                .data_tx_data_10(data_tx_data_10),          //INPUT  : Data from FIFO transmit
1981 
                .data_tx_valid_10(data_tx_valid_10),        //INPUT  : Data FIFO transmit Empty
1982 
                .data_tx_sop_10(data_tx_sop_10),            //INPUT  : Start of Packet
1983 
                .data_tx_eop_10(data_tx_eop_10),            //INPUT  : End of Packet
1984 
                .data_tx_ready_10(data_tx_ready_10),        //OUTPUT : Data FIFO transmit Read Enable
1985 
                .tx_ff_uflow_10(tx_ff_uflow_10),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
1986 
                .tx_crc_fwd_10(tx_crc_fwd_10),              //INPUT  : Forward Current Frame with CRC from Application
1987 
                .xoff_gen_10(xoff_gen_10),                  //INPUT  : XOFF PAUSE FRAME GENERATE
1988 
                .xon_gen_10(xon_gen_10),                    //INPUT  : XON PAUSE FRAME GENERATE
1989 
                .magic_sleep_n_10(magic_sleep_n_10),        //INPUT  : MAC SLEEP MODE CONTROL
1990 
                .magic_wakeup_10(magic_wakeup_10),          //OUTPUT : MAC WAKE-UP INDICATION
1991 
 
1992 
             // Channel 11
1993 
 
1994 
                .rx_clk_11(rx_clk_11),                      //INPUT  : MAC RX CLK
1995 
                .tx_clk_11(tx_clk_11),                      //INPUT  : MAC TX CLK
1996 
                .gm_rx_d_11(gm_rx_d_11),                    //INPUT  : GMII RX DATA
1997 
                .gm_rx_dv_11(gm_rx_dv_11),                  //INPUT  : GMII RX VALID INDICATION
1998 
                .gm_rx_err_11(gm_rx_err_11),                //INPUT  : GMII RX ERROR INDICATION
1999 
                .gm_tx_d_11(gm_tx_d_11),                    //OUTPUT : GMII TX DATA
2000 
                .gm_tx_en_11(gm_tx_en_11),                  //OUTPUT : GMII TX VALID INDICATION
2001 
                .gm_tx_err_11(gm_tx_err_11),                //OUTPUT : GMII TX ERROR INDICATION
2002 
                .m_rx_crs_11(m_rx_crs_11),                  //INPUT  : MII RX CARRIER SENSE
2003 
                .m_rx_col_11(m_rx_col_11),                  //INPUT  : MII RX COLLISION
2004 
                .m_rx_d_11(m_rx_d_11),                      //INPUT  : MII RX DATA
2005 
                .m_rx_en_11(m_rx_en_11),                    //INPUT  : MII RX VALID INDICATION
2006 
                .m_rx_err_11(m_rx_err_11),                  //INPUT  : MII RX ERROR INDICATION
2007 
                .m_tx_d_11(m_tx_d_11),                      //OUTPUT : MII TX DATA
2008 
                .m_tx_en_11(m_tx_en_11),                    //OUTPUT : MII TX VALID INDICATION
2009 
                .m_tx_err_11(m_tx_err_11),                  //OUTPUT : MII TX ERROR INDICATION
2010 
                .rx_control_11(rx_control_11),              //INPUT  : RGMII RX CONTROL INDICATION
2011 
                .rgmii_in_11(rgmii_in_11),                  //INPUT  : RGMII RX DATA INDICATION
2012 
                .tx_control_11(tx_control_11),              //OUTPUT : RGMII TX CONTROL INDICATION
2013 
                .rgmii_out_11(rgmii_out_11),                //OUTPUT : RGMII TX DATA INDICATION
2014 
                .eth_mode_11(eth_mode_11),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2015 
                .ena_10_11(ena_10_11),                      //OUTPUT : SPEED 10 MBPS INDICATION
2016 
                .set_10_11(set_10_11),                      //INPUT  : SPEED 10 MBPS
2017 
                .set_1000_11(set_1000_11),                  //INPUT  : SPEED 1000 MBPS
2018 
                .mac_rx_clk_11(mac_rx_clk_11),              //OUTPUT : Av-ST Rx Clock
2019 
            .mac_tx_clk_11(mac_tx_clk_11),              //OUTPUT : Av-ST Tx Clock
2020 
                .data_rx_sop_11(data_rx_sop_11),            //OUTPUT : Start of Packet
2021 
                .data_rx_eop_11(data_rx_eop_11),            //OUTPUT : End of Packet
2022 
                .data_rx_data_11(data_rx_data_11),          //OUTPUT : Data from FIFO
2023 
                .data_rx_error_11(data_rx_error_11),        //OUTPUT : Receive packet error
2024 
                .data_rx_valid_11(data_rx_valid_11),        //OUTPUT : Data Receive FIFO Valid
2025 
                .data_rx_ready_11(data_rx_ready_11),        //OUTPUT : Data Receive Ready
2026 
                .pkt_class_data_11(pkt_class_data_11),      //OUTPUT : Frame Type Indication
2027 
                .pkt_class_valid_11(pkt_class_valid_11),    //OUTPUT : Frame Type Indication Valid
2028 
                .data_tx_error_11(data_tx_error_11),        //INPUT  : Status
2029 
                .data_tx_data_11(data_tx_data_11),          //INPUT  : Data from FIFO transmit
2030 
                .data_tx_valid_11(data_tx_valid_11),        //INPUT  : Data FIFO transmit Empty
2031 
                .data_tx_sop_11(data_tx_sop_11),            //INPUT  : Start of Packet
2032 
                .data_tx_eop_11(data_tx_eop_11),            //INPUT  : End of Packet
2033 
                .data_tx_ready_11(data_tx_ready_11),        //OUTPUT : Data FIFO transmit Read Enable
2034 
                .tx_ff_uflow_11(tx_ff_uflow_11),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2035 
                .tx_crc_fwd_11(tx_crc_fwd_11),              //INPUT  : Forward Current Frame with CRC from Application
2036 
                .xoff_gen_11(xoff_gen_11),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2037 
                .xon_gen_11(xon_gen_11),                    //INPUT  : XON PAUSE FRAME GENERATE
2038 
                .magic_sleep_n_11(magic_sleep_n_11),        //INPUT  : MAC SLEEP MODE CONTROL
2039 
                .magic_wakeup_11(magic_wakeup_11),          //OUTPUT : MAC WAKE-UP INDICATION
2040 
 
2041 
             // Channel 12
2042 
 
2043 
                .rx_clk_12(rx_clk_12),                      //INPUT  : MAC RX CLK
2044 
                .tx_clk_12(tx_clk_12),                      //INPUT  : MAC TX CLK
2045 
                .gm_rx_d_12(gm_rx_d_12),                    //INPUT  : GMII RX DATA
2046 
                .gm_rx_dv_12(gm_rx_dv_12),                  //INPUT  : GMII RX VALID INDICATION
2047 
                .gm_rx_err_12(gm_rx_err_12),                //INPUT  : GMII RX ERROR INDICATION
2048 
                .gm_tx_d_12(gm_tx_d_12),                    //OUTPUT : GMII TX DATA
2049 
                .gm_tx_en_12(gm_tx_en_12),                  //OUTPUT : GMII TX VALID INDICATION
2050 
                .gm_tx_err_12(gm_tx_err_12),                //OUTPUT : GMII TX ERROR INDICATION
2051 
                .m_rx_crs_12(m_rx_crs_12),                  //INPUT  : MII RX CARRIER SENSE
2052 
                .m_rx_col_12(m_rx_col_12),                  //INPUT  : MII RX COLLISION
2053 
                .m_rx_d_12(m_rx_d_12),                      //INPUT  : MII RX DATA
2054 
                .m_rx_en_12(m_rx_en_12),                    //INPUT  : MII RX VALID INDICATION
2055 
                .m_rx_err_12(m_rx_err_12),                  //INPUT  : MII RX ERROR INDICATION
2056 
                .m_tx_d_12(m_tx_d_12),                      //OUTPUT : MII TX DATA
2057 
                .m_tx_en_12(m_tx_en_12),                    //OUTPUT : MII TX VALID INDICATION
2058 
                .m_tx_err_12(m_tx_err_12),                  //OUTPUT : MII TX ERROR INDICATION
2059 
                .rx_control_12(rx_control_12),              //INPUT  : RGMII RX CONTROL INDICATION
2060 
                .rgmii_in_12(rgmii_in_12),                  //INPUT  : RGMII RX DATA INDICATION
2061 
                .tx_control_12(tx_control_12),              //OUTPUT : RGMII TX CONTROL INDICATION
2062 
                .rgmii_out_12(rgmii_out_12),                //OUTPUT : RGMII TX DATA INDICATION
2063 
                .eth_mode_12(eth_mode_12),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2064 
                .ena_10_12(ena_10_12),                      //OUTPUT : SPEED 10 MBPS INDICATION
2065 
                .set_10_12(set_10_12),                      //INPUT  : SPEED 10 MBPS
2066 
                .set_1000_12(set_1000_12),                  //INPUT  : SPEED 1000 MBPS
2067 
                .mac_rx_clk_12(mac_rx_clk_12),              //OUTPUT : Av-ST Rx Clock
2068 
            .mac_tx_clk_12(mac_tx_clk_12),              //OUTPUT : Av-ST Tx Clock
2069 
                .data_rx_sop_12(data_rx_sop_12),            //OUTPUT : Start of Packet
2070 
                .data_rx_eop_12(data_rx_eop_12),            //OUTPUT : End of Packet
2071 
                .data_rx_data_12(data_rx_data_12),          //OUTPUT : Data from FIFO
2072 
                .data_rx_error_12(data_rx_error_12),        //OUTPUT : Receive packet error
2073 
                .data_rx_valid_12(data_rx_valid_12),        //OUTPUT : Data Receive FIFO Valid
2074 
                .data_rx_ready_12(data_rx_ready_12),        //OUTPUT : Data Receive Ready
2075 
                .pkt_class_data_12(pkt_class_data_12),      //OUTPUT : Frame Type Indication
2076 
                .pkt_class_valid_12(pkt_class_valid_12),    //OUTPUT : Frame Type Indication Valid
2077 
                .data_tx_error_12(data_tx_error_12),        //INPUT  : Status
2078 
                .data_tx_data_12(data_tx_data_12),          //INPUT  : Data from FIFO transmit
2079 
                .data_tx_valid_12(data_tx_valid_12),        //INPUT  : Data FIFO transmit Empty
2080 
                .data_tx_sop_12(data_tx_sop_12),            //INPUT  : Start of Packet
2081 
                .data_tx_eop_12(data_tx_eop_12),            //INPUT  : End of Packet
2082 
                .data_tx_ready_12(data_tx_ready_12),        //OUTPUT : Data FIFO transmit Read Enable
2083 
                .tx_ff_uflow_12(tx_ff_uflow_12),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2084 
                .tx_crc_fwd_12(tx_crc_fwd_12),              //INPUT  : Forward Current Frame with CRC from Application
2085 
                .xoff_gen_12(xoff_gen_12),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2086 
                .xon_gen_12(xon_gen_12),                    //INPUT  : XON PAUSE FRAME GENERATE
2087 
                .magic_sleep_n_12(magic_sleep_n_12),        //INPUT  : MAC SLEEP MODE CONTROL
2088 
                .magic_wakeup_12(magic_wakeup_12),          //OUTPUT : MAC WAKE-UP INDICATION
2089 
 
2090 
             // Channel 13
2091 
 
2092 
                .rx_clk_13(rx_clk_13),                      //INPUT  : MAC RX CLK
2093 
                .tx_clk_13(tx_clk_13),                      //INPUT  : MAC TX CLK
2094 
                .gm_rx_d_13(gm_rx_d_13),                    //INPUT  : GMII RX DATA
2095 
                .gm_rx_dv_13(gm_rx_dv_13),                  //INPUT  : GMII RX VALID INDICATION
2096 
                .gm_rx_err_13(gm_rx_err_13),                //INPUT  : GMII RX ERROR INDICATION
2097 
                .gm_tx_d_13(gm_tx_d_13),                    //OUTPUT : GMII TX DATA
2098 
                .gm_tx_en_13(gm_tx_en_13),                  //OUTPUT : GMII TX VALID INDICATION
2099 
                .gm_tx_err_13(gm_tx_err_13),                //OUTPUT : GMII TX ERROR INDICATION
2100 
                .m_rx_crs_13(m_rx_crs_13),                  //INPUT  : MII RX CARRIER SENSE
2101 
                .m_rx_col_13(m_rx_col_13),                  //INPUT  : MII RX COLLISION
2102 
                .m_rx_d_13(m_rx_d_13),                      //INPUT  : MII RX DATA
2103 
                .m_rx_en_13(m_rx_en_13),                    //INPUT  : MII RX VALID INDICATION
2104 
                .m_rx_err_13(m_rx_err_13),                  //INPUT  : MII RX ERROR INDICATION
2105 
                .m_tx_d_13(m_tx_d_13),                      //OUTPUT : MII TX DATA
2106 
                .m_tx_en_13(m_tx_en_13),                    //OUTPUT : MII TX VALID INDICATION
2107 
                .m_tx_err_13(m_tx_err_13),                  //OUTPUT : MII TX ERROR INDICATION
2108 
                .rx_control_13(rx_control_13),              //INPUT  : RGMII RX CONTROL INDICATION
2109 
                .rgmii_in_13(rgmii_in_13),                  //INPUT  : RGMII RX DATA INDICATION
2110 
                .tx_control_13(tx_control_13),              //OUTPUT : RGMII TX CONTROL INDICATION
2111 
                .rgmii_out_13(rgmii_out_13),                //OUTPUT : RGMII TX DATA INDICATION
2112 
                .eth_mode_13(eth_mode_13),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2113 
                .ena_10_13(ena_10_13),                      //OUTPUT : SPEED 10 MBPS INDICATION
2114 
                .set_10_13(set_10_13),                      //INPUT  : SPEED 10 MBPS
2115 
                .set_1000_13(set_1000_13),                  //INPUT  : SPEED 1000 MBPS
2116 
                .mac_rx_clk_13(mac_rx_clk_13),              //OUTPUT : Av-ST Rx Clock
2117 
            .mac_tx_clk_13(mac_tx_clk_13),              //OUTPUT : Av-ST Tx Clock
2118 
                .data_rx_sop_13(data_rx_sop_13),            //OUTPUT : Start of Packet
2119 
                .data_rx_eop_13(data_rx_eop_13),            //OUTPUT : End of Packet
2120 
                .data_rx_data_13(data_rx_data_13),          //OUTPUT : Data from FIFO
2121 
                .data_rx_error_13(data_rx_error_13),        //OUTPUT : Receive packet error
2122 
                .data_rx_valid_13(data_rx_valid_13),        //OUTPUT : Data Receive FIFO Valid
2123 
                .data_rx_ready_13(data_rx_ready_13),        //OUTPUT : Data Receive Ready
2124 
                .pkt_class_data_13(pkt_class_data_13),      //OUTPUT : Frame Type Indication
2125 
                .pkt_class_valid_13(pkt_class_valid_13),    //OUTPUT : Frame Type Indication Valid
2126 
                .data_tx_error_13(data_tx_error_13),        //INPUT  : Status
2127 
                .data_tx_data_13(data_tx_data_13),          //INPUT  : Data from FIFO transmit
2128 
                .data_tx_valid_13(data_tx_valid_13),        //INPUT  : Data FIFO transmit Empty
2129 
                .data_tx_sop_13(data_tx_sop_13),            //INPUT  : Start of Packet
2130 
                .data_tx_eop_13(data_tx_eop_13),            //INPUT  : End of Packet
2131 
                .data_tx_ready_13(data_tx_ready_13),        //OUTPUT : Data FIFO transmit Read Enable
2132 
                .tx_ff_uflow_13(tx_ff_uflow_13),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2133 
                .tx_crc_fwd_13(tx_crc_fwd_13),              //INPUT  : Forward Current Frame with CRC from Application
2134 
                .xoff_gen_13(xoff_gen_13),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2135 
                .xon_gen_13(xon_gen_13),                    //INPUT  : XON PAUSE FRAME GENERATE
2136 
                .magic_sleep_n_13(magic_sleep_n_13),        //INPUT  : MAC SLEEP MODE CONTROL
2137 
                .magic_wakeup_13(magic_wakeup_13),          //OUTPUT : MAC WAKE-UP INDICATION
2138 
 
2139 
             // Channel 14
2140 
 
2141 
                .rx_clk_14(rx_clk_14),                      //INPUT  : MAC RX CLK
2142 
                .tx_clk_14(tx_clk_14),                      //INPUT  : MAC TX CLK
2143 
                .gm_rx_d_14(gm_rx_d_14),                    //INPUT  : GMII RX DATA
2144 
                .gm_rx_dv_14(gm_rx_dv_14),                  //INPUT  : GMII RX VALID INDICATION
2145 
                .gm_rx_err_14(gm_rx_err_14),                //INPUT  : GMII RX ERROR INDICATION
2146 
                .gm_tx_d_14(gm_tx_d_14),                    //OUTPUT : GMII TX DATA
2147 
                .gm_tx_en_14(gm_tx_en_14),                  //OUTPUT : GMII TX VALID INDICATION
2148 
                .gm_tx_err_14(gm_tx_err_14),                //OUTPUT : GMII TX ERROR INDICATION
2149 
                .m_rx_crs_14(m_rx_crs_14),                  //INPUT  : MII RX CARRIER SENSE
2150 
                .m_rx_col_14(m_rx_col_14),                  //INPUT  : MII RX COLLISION
2151 
                .m_rx_d_14(m_rx_d_14),                      //INPUT  : MII RX DATA
2152 
                .m_rx_en_14(m_rx_en_14),                    //INPUT  : MII RX VALID INDICATION
2153 
                .m_rx_err_14(m_rx_err_14),                  //INPUT  : MII RX ERROR INDICATION
2154 
                .m_tx_d_14(m_tx_d_14),                      //OUTPUT : MII TX DATA
2155 
                .m_tx_en_14(m_tx_en_14),                    //OUTPUT : MII TX VALID INDICATION
2156 
                .m_tx_err_14(m_tx_err_14),                  //OUTPUT : MII TX ERROR INDICATION
2157 
                .rx_control_14(rx_control_14),              //INPUT  : RGMII RX CONTROL INDICATION
2158 
                .rgmii_in_14(rgmii_in_14),                  //INPUT  : RGMII RX DATA INDICATION
2159 
                .tx_control_14(tx_control_14),              //OUTPUT : RGMII TX CONTROL INDICATION
2160 
                .rgmii_out_14(rgmii_out_14),                //OUTPUT : RGMII TX DATA INDICATION
2161 
                .eth_mode_14(eth_mode_14),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2162 
                .ena_10_14(ena_10_14),                      //OUTPUT : SPEED 10 MBPS INDICATION
2163 
                .set_10_14(set_10_14),                      //INPUT  : SPEED 10 MBPS
2164 
                .set_1000_14(set_1000_14),                  //INPUT  : SPEED 1000 MBPS
2165 
                .mac_rx_clk_14(mac_rx_clk_14),              //OUTPUT : Av-ST Rx Clock
2166 
            .mac_tx_clk_14(mac_tx_clk_14),              //OUTPUT : Av-ST Tx Clock
2167 
                .data_rx_sop_14(data_rx_sop_14),            //OUTPUT : Start of Packet
2168 
                .data_rx_eop_14(data_rx_eop_14),            //OUTPUT : End of Packet
2169 
                .data_rx_data_14(data_rx_data_14),          //OUTPUT : Data from FIFO
2170 
                .data_rx_error_14(data_rx_error_14),        //OUTPUT : Receive packet error
2171 
                .data_rx_valid_14(data_rx_valid_14),        //OUTPUT : Data Receive FIFO Valid
2172 
                .data_rx_ready_14(data_rx_ready_14),        //OUTPUT : Data Receive Ready
2173 
                .pkt_class_data_14(pkt_class_data_14),      //OUTPUT : Frame Type Indication
2174 
                .pkt_class_valid_14(pkt_class_valid_14),    //OUTPUT : Frame Type Indication Valid
2175 
                .data_tx_error_14(data_tx_error_14),        //INPUT  : Status
2176 
                .data_tx_data_14(data_tx_data_14),          //INPUT  : Data from FIFO transmit
2177 
                .data_tx_valid_14(data_tx_valid_14),        //INPUT  : Data FIFO transmit Empty
2178 
                .data_tx_sop_14(data_tx_sop_14),            //INPUT  : Start of Packet
2179 
                .data_tx_eop_14(data_tx_eop_14),            //INPUT  : End of Packet
2180 
                .data_tx_ready_14(data_tx_ready_14),        //OUTPUT : Data FIFO transmit Read Enable
2181 
                .tx_ff_uflow_14(tx_ff_uflow_14),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2182 
                .tx_crc_fwd_14(tx_crc_fwd_14),              //INPUT  : Forward Current Frame with CRC from Application
2183 
                .xoff_gen_14(xoff_gen_14),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2184 
                .xon_gen_14(xon_gen_14),                    //INPUT  : XON PAUSE FRAME GENERATE
2185 
                .magic_sleep_n_14(magic_sleep_n_14),        //INPUT  : MAC SLEEP MODE CONTROL
2186 
                .magic_wakeup_14(magic_wakeup_14),          //OUTPUT : MAC WAKE-UP INDICATION
2187 
 
2188 
             // Channel 15
2189 
 
2190 
                .rx_clk_15(rx_clk_15),                      //INPUT  : MAC RX CLK
2191 
                .tx_clk_15(tx_clk_15),                      //INPUT  : MAC TX CLK
2192 
                .gm_rx_d_15(gm_rx_d_15),                    //INPUT  : GMII RX DATA
2193 
                .gm_rx_dv_15(gm_rx_dv_15),                  //INPUT  : GMII RX VALID INDICATION
2194 
                .gm_rx_err_15(gm_rx_err_15),                //INPUT  : GMII RX ERROR INDICATION
2195 
                .gm_tx_d_15(gm_tx_d_15),                    //OUTPUT : GMII TX DATA
2196 
                .gm_tx_en_15(gm_tx_en_15),                  //OUTPUT : GMII TX VALID INDICATION
2197 
                .gm_tx_err_15(gm_tx_err_15),                //OUTPUT : GMII TX ERROR INDICATION
2198 
                .m_rx_crs_15(m_rx_crs_15),                  //INPUT  : MII RX CARRIER SENSE
2199 
                .m_rx_col_15(m_rx_col_15),                  //INPUT  : MII RX COLLISION
2200 
                .m_rx_d_15(m_rx_d_15),                      //INPUT  : MII RX DATA
2201 
                .m_rx_en_15(m_rx_en_15),                    //INPUT  : MII RX VALID INDICATION
2202 
                .m_rx_err_15(m_rx_err_15),                  //INPUT  : MII RX ERROR INDICATION
2203 
                .m_tx_d_15(m_tx_d_15),                      //OUTPUT : MII TX DATA
2204 
                .m_tx_en_15(m_tx_en_15),                    //OUTPUT : MII TX VALID INDICATION
2205 
                .m_tx_err_15(m_tx_err_15),                  //OUTPUT : MII TX ERROR INDICATION
2206 
                .rx_control_15(rx_control_15),              //INPUT  : RGMII RX CONTROL INDICATION
2207 
                .rgmii_in_15(rgmii_in_15),                  //INPUT  : RGMII RX DATA INDICATION
2208 
                .tx_control_15(tx_control_15),              //OUTPUT : RGMII TX CONTROL INDICATION
2209 
                .rgmii_out_15(rgmii_out_15),                //OUTPUT : RGMII TX DATA INDICATION
2210 
                .eth_mode_15(eth_mode_15),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2211 
                .ena_10_15(ena_10_15),                      //OUTPUT : SPEED 10 MBPS INDICATION
2212 
                .set_10_15(set_10_15),                      //INPUT  : SPEED 10 MBPS
2213 
                .set_1000_15(set_1000_15),                  //INPUT  : SPEED 1000 MBPS
2214 
                .mac_rx_clk_15(mac_rx_clk_15),              //OUTPUT : Av-ST Rx Clock
2215 
            .mac_tx_clk_15(mac_tx_clk_15),              //OUTPUT : Av-ST Tx Clock
2216 
                .data_rx_sop_15(data_rx_sop_15),            //OUTPUT : Start of Packet
2217 
                .data_rx_eop_15(data_rx_eop_15),            //OUTPUT : End of Packet
2218 
                .data_rx_data_15(data_rx_data_15),          //OUTPUT : Data from FIFO
2219 
                .data_rx_error_15(data_rx_error_15),        //OUTPUT : Receive packet error
2220 
                .data_rx_valid_15(data_rx_valid_15),        //OUTPUT : Data Receive FIFO Valid
2221 
                .data_rx_ready_15(data_rx_ready_15),        //OUTPUT : Data Receive Ready
2222 
                .pkt_class_data_15(pkt_class_data_15),      //OUTPUT : Frame Type Indication
2223 
                .pkt_class_valid_15(pkt_class_valid_15),    //OUTPUT : Frame Type Indication Valid
2224 
                .data_tx_error_15(data_tx_error_15),        //INPUT  : Status
2225 
                .data_tx_data_15(data_tx_data_15),          //INPUT  : Data from FIFO transmit
2226 
                .data_tx_valid_15(data_tx_valid_15),        //INPUT  : Data FIFO transmit Empty
2227 
                .data_tx_sop_15(data_tx_sop_15),            //INPUT  : Start of Packet
2228 
                .data_tx_eop_15(data_tx_eop_15),            //INPUT  : End of Packet
2229 
                .data_tx_ready_15(data_tx_ready_15),        //OUTPUT : Data FIFO transmit Read Enable
2230 
                .tx_ff_uflow_15(tx_ff_uflow_15),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2231 
                .tx_crc_fwd_15(tx_crc_fwd_15),              //INPUT  : Forward Current Frame with CRC from Application
2232 
                .xoff_gen_15(xoff_gen_15),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2233 
                .xon_gen_15(xon_gen_15),                    //INPUT  : XON PAUSE FRAME GENERATE
2234 
                .magic_sleep_n_15(magic_sleep_n_15),        //INPUT  : MAC SLEEP MODE CONTROL
2235 
                .magic_wakeup_15(magic_wakeup_15),          //OUTPUT : MAC WAKE-UP INDICATION
2236 
 
2237 
             // Channel 16
2238 
 
2239 
                .rx_clk_16(rx_clk_16),                      //INPUT  : MAC RX CLK
2240 
                .tx_clk_16(tx_clk_16),                      //INPUT  : MAC TX CLK
2241 
                .gm_rx_d_16(gm_rx_d_16),                    //INPUT  : GMII RX DATA
2242 
                .gm_rx_dv_16(gm_rx_dv_16),                  //INPUT  : GMII RX VALID INDICATION
2243 
                .gm_rx_err_16(gm_rx_err_16),                //INPUT  : GMII RX ERROR INDICATION
2244 
                .gm_tx_d_16(gm_tx_d_16),                    //OUTPUT : GMII TX DATA
2245 
                .gm_tx_en_16(gm_tx_en_16),                  //OUTPUT : GMII TX VALID INDICATION
2246 
                .gm_tx_err_16(gm_tx_err_16),                //OUTPUT : GMII TX ERROR INDICATION
2247 
                .m_rx_crs_16(m_rx_crs_16),                  //INPUT  : MII RX CARRIER SENSE
2248 
                .m_rx_col_16(m_rx_col_16),                  //INPUT  : MII RX COLLISION
2249 
                .m_rx_d_16(m_rx_d_16),                      //INPUT  : MII RX DATA
2250 
                .m_rx_en_16(m_rx_en_16),                    //INPUT  : MII RX VALID INDICATION
2251 
                .m_rx_err_16(m_rx_err_16),                  //INPUT  : MII RX ERROR INDICATION
2252 
                .m_tx_d_16(m_tx_d_16),                      //OUTPUT : MII TX DATA
2253 
                .m_tx_en_16(m_tx_en_16),                    //OUTPUT : MII TX VALID INDICATION
2254 
                .m_tx_err_16(m_tx_err_16),                  //OUTPUT : MII TX ERROR INDICATION
2255 
                .rx_control_16(rx_control_16),              //INPUT  : RGMII RX CONTROL INDICATION
2256 
                .rgmii_in_16(rgmii_in_16),                  //INPUT  : RGMII RX DATA INDICATION
2257 
                .tx_control_16(tx_control_16),              //OUTPUT : RGMII TX CONTROL INDICATION
2258 
                .rgmii_out_16(rgmii_out_16),                //OUTPUT : RGMII TX DATA INDICATION
2259 
                .eth_mode_16(eth_mode_16),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2260 
                .ena_10_16(ena_10_16),                      //OUTPUT : SPEED 10 MBPS INDICATION
2261 
                .set_10_16(set_10_16),                      //INPUT  : SPEED 10 MBPS
2262 
                .set_1000_16(set_1000_16),                  //INPUT  : SPEED 1000 MBPS
2263 
                .mac_rx_clk_16(mac_rx_clk_16),              //OUTPUT : Av-ST Rx Clock
2264 
            .mac_tx_clk_16(mac_tx_clk_16),              //OUTPUT : Av-ST Tx Clock
2265 
                .data_rx_sop_16(data_rx_sop_16),            //OUTPUT : Start of Packet
2266 
                .data_rx_eop_16(data_rx_eop_16),            //OUTPUT : End of Packet
2267 
                .data_rx_data_16(data_rx_data_16),          //OUTPUT : Data from FIFO
2268 
                .data_rx_error_16(data_rx_error_16),        //OUTPUT : Receive packet error
2269 
                .data_rx_valid_16(data_rx_valid_16),        //OUTPUT : Data Receive FIFO Valid
2270 
                .data_rx_ready_16(data_rx_ready_16),        //OUTPUT : Data Receive Ready
2271 
                .pkt_class_data_16(pkt_class_data_16),      //OUTPUT : Frame Type Indication
2272 
                .pkt_class_valid_16(pkt_class_valid_16),    //OUTPUT : Frame Type Indication Valid
2273 
                .data_tx_error_16(data_tx_error_16),        //INPUT  : Status
2274 
                .data_tx_data_16(data_tx_data_16),          //INPUT  : Data from FIFO transmit
2275 
                .data_tx_valid_16(data_tx_valid_16),        //INPUT  : Data FIFO transmit Empty
2276 
                .data_tx_sop_16(data_tx_sop_16),            //INPUT  : Start of Packet
2277 
                .data_tx_eop_16(data_tx_eop_16),            //INPUT  : End of Packet
2278 
                .data_tx_ready_16(data_tx_ready_16),        //OUTPUT : Data FIFO transmit Read Enable
2279 
                .tx_ff_uflow_16(tx_ff_uflow_16),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2280 
                .tx_crc_fwd_16(tx_crc_fwd_16),              //INPUT  : Forward Current Frame with CRC from Application
2281 
                .xoff_gen_16(xoff_gen_16),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2282 
                .xon_gen_16(xon_gen_16),                    //INPUT  : XON PAUSE FRAME GENERATE
2283 
                .magic_sleep_n_16(magic_sleep_n_16),        //INPUT  : MAC SLEEP MODE CONTROL
2284 
                .magic_wakeup_16(magic_wakeup_16),          //OUTPUT : MAC WAKE-UP INDICATION
2285 
 
2286 
             // Channel 17
2287 
 
2288 
                .rx_clk_17(rx_clk_17),                      //INPUT  : MAC RX CLK
2289 
                .tx_clk_17(tx_clk_17),                      //INPUT  : MAC TX CLK
2290 
                .gm_rx_d_17(gm_rx_d_17),                    //INPUT  : GMII RX DATA
2291 
                .gm_rx_dv_17(gm_rx_dv_17),                  //INPUT  : GMII RX VALID INDICATION
2292 
                .gm_rx_err_17(gm_rx_err_17),                //INPUT  : GMII RX ERROR INDICATION
2293 
                .gm_tx_d_17(gm_tx_d_17),                    //OUTPUT : GMII TX DATA
2294 
                .gm_tx_en_17(gm_tx_en_17),                  //OUTPUT : GMII TX VALID INDICATION
2295 
                .gm_tx_err_17(gm_tx_err_17),                //OUTPUT : GMII TX ERROR INDICATION
2296 
                .m_rx_crs_17(m_rx_crs_17),                  //INPUT  : MII RX CARRIER SENSE
2297 
                .m_rx_col_17(m_rx_col_17),                  //INPUT  : MII RX COLLISION
2298 
                .m_rx_d_17(m_rx_d_17),                      //INPUT  : MII RX DATA
2299 
                .m_rx_en_17(m_rx_en_17),                    //INPUT  : MII RX VALID INDICATION
2300 
                .m_rx_err_17(m_rx_err_17),                  //INPUT  : MII RX ERROR INDICATION
2301 
                .m_tx_d_17(m_tx_d_17),                      //OUTPUT : MII TX DATA
2302 
                .m_tx_en_17(m_tx_en_17),                    //OUTPUT : MII TX VALID INDICATION
2303 
                .m_tx_err_17(m_tx_err_17),                  //OUTPUT : MII TX ERROR INDICATION
2304 
                .rx_control_17(rx_control_17),              //INPUT  : RGMII RX CONTROL INDICATION
2305 
                .rgmii_in_17(rgmii_in_17),                  //INPUT  : RGMII RX DATA INDICATION
2306 
                .tx_control_17(tx_control_17),              //OUTPUT : RGMII TX CONTROL INDICATION
2307 
                .rgmii_out_17(rgmii_out_17),                //OUTPUT : RGMII TX DATA INDICATION
2308 
                .eth_mode_17(eth_mode_17),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2309 
                .ena_10_17(ena_10_17),                      //OUTPUT : SPEED 10 MBPS INDICATION
2310 
                .set_10_17(set_10_17),                      //INPUT  : SPEED 10 MBPS
2311 
                .set_1000_17(set_1000_17),                  //INPUT  : SPEED 1000 MBPS
2312 
                .mac_rx_clk_17(mac_rx_clk_17),              //OUTPUT : Av-ST Rx Clock
2313 
            .mac_tx_clk_17(mac_tx_clk_17),              //OUTPUT : Av-ST Tx Clock
2314 
                .data_rx_sop_17(data_rx_sop_17),            //OUTPUT : Start of Packet
2315 
                .data_rx_eop_17(data_rx_eop_17),            //OUTPUT : End of Packet
2316 
                .data_rx_data_17(data_rx_data_17),          //OUTPUT : Data from FIFO
2317 
                .data_rx_error_17(data_rx_error_17),        //OUTPUT : Receive packet error
2318 
                .data_rx_valid_17(data_rx_valid_17),        //OUTPUT : Data Receive FIFO Valid
2319 
                .data_rx_ready_17(data_rx_ready_17),        //OUTPUT : Data Receive Ready
2320 
                .pkt_class_data_17(pkt_class_data_17),      //OUTPUT : Frame Type Indication
2321 
                .pkt_class_valid_17(pkt_class_valid_17),    //OUTPUT : Frame Type Indication Valid
2322 
                .data_tx_error_17(data_tx_error_17),        //INPUT  : Status
2323 
                .data_tx_data_17(data_tx_data_17),          //INPUT  : Data from FIFO transmit
2324 
                .data_tx_valid_17(data_tx_valid_17),        //INPUT  : Data FIFO transmit Empty
2325 
                .data_tx_sop_17(data_tx_sop_17),            //INPUT  : Start of Packet
2326 
                .data_tx_eop_17(data_tx_eop_17),            //INPUT  : End of Packet
2327 
                .data_tx_ready_17(data_tx_ready_17),        //OUTPUT : Data FIFO transmit Read Enable
2328 
                .tx_ff_uflow_17(tx_ff_uflow_17),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2329 
                .tx_crc_fwd_17(tx_crc_fwd_17),              //INPUT  : Forward Current Frame with CRC from Application
2330 
                .xoff_gen_17(xoff_gen_17),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2331 
                .xon_gen_17(xon_gen_17),                    //INPUT  : XON PAUSE FRAME GENERATE
2332 
                .magic_sleep_n_17(magic_sleep_n_17),        //INPUT  : MAC SLEEP MODE CONTROL
2333 
                .magic_wakeup_17(magic_wakeup_17),          //OUTPUT : MAC WAKE-UP INDICATION
2334 
 
2335 
             // Channel 18
2336 
 
2337 
                .rx_clk_18(rx_clk_18),                      //INPUT  : MAC RX CLK
2338 
                .tx_clk_18(tx_clk_18),                      //INPUT  : MAC TX CLK
2339 
                .gm_rx_d_18(gm_rx_d_18),                    //INPUT  : GMII RX DATA
2340 
                .gm_rx_dv_18(gm_rx_dv_18),                  //INPUT  : GMII RX VALID INDICATION
2341 
                .gm_rx_err_18(gm_rx_err_18),                //INPUT  : GMII RX ERROR INDICATION
2342 
                .gm_tx_d_18(gm_tx_d_18),                    //OUTPUT : GMII TX DATA
2343 
                .gm_tx_en_18(gm_tx_en_18),                  //OUTPUT : GMII TX VALID INDICATION
2344 
                .gm_tx_err_18(gm_tx_err_18),                //OUTPUT : GMII TX ERROR INDICATION
2345 
                .m_rx_crs_18(m_rx_crs_18),                  //INPUT  : MII RX CARRIER SENSE
2346 
                .m_rx_col_18(m_rx_col_18),                  //INPUT  : MII RX COLLISION
2347 
                .m_rx_d_18(m_rx_d_18),                      //INPUT  : MII RX DATA
2348 
                .m_rx_en_18(m_rx_en_18),                    //INPUT  : MII RX VALID INDICATION
2349 
                .m_rx_err_18(m_rx_err_18),                  //INPUT  : MII RX ERROR INDICATION
2350 
                .m_tx_d_18(m_tx_d_18),                      //OUTPUT : MII TX DATA
2351 
                .m_tx_en_18(m_tx_en_18),                    //OUTPUT : MII TX VALID INDICATION
2352 
                .m_tx_err_18(m_tx_err_18),                  //OUTPUT : MII TX ERROR INDICATION
2353 
                .rx_control_18(rx_control_18),              //INPUT  : RGMII RX CONTROL INDICATION
2354 
                .rgmii_in_18(rgmii_in_18),                  //INPUT  : RGMII RX DATA INDICATION
2355 
                .tx_control_18(tx_control_18),              //OUTPUT : RGMII TX CONTROL INDICATION
2356 
                .rgmii_out_18(rgmii_out_18),                //OUTPUT : RGMII TX DATA INDICATION
2357 
                .eth_mode_18(eth_mode_18),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2358 
                .ena_10_18(ena_10_18),                      //OUTPUT : SPEED 10 MBPS INDICATION
2359 
                .set_10_18(set_10_18),                      //INPUT  : SPEED 10 MBPS
2360 
                .set_1000_18(set_1000_18),                  //INPUT  : SPEED 1000 MBPS
2361 
                .mac_rx_clk_18(mac_rx_clk_18),              //OUTPUT : Av-ST Rx Clock
2362 
            .mac_tx_clk_18(mac_tx_clk_18),              //OUTPUT : Av-ST Tx Clock
2363 
                .data_rx_sop_18(data_rx_sop_18),            //OUTPUT : Start of Packet
2364 
                .data_rx_eop_18(data_rx_eop_18),            //OUTPUT : End of Packet
2365 
                .data_rx_data_18(data_rx_data_18),          //OUTPUT : Data from FIFO
2366 
                .data_rx_error_18(data_rx_error_18),        //OUTPUT : Receive packet error
2367 
                .data_rx_valid_18(data_rx_valid_18),        //OUTPUT : Data Receive FIFO Valid
2368 
                .data_rx_ready_18(data_rx_ready_18),        //OUTPUT : Data Receive Ready
2369 
                .pkt_class_data_18(pkt_class_data_18),      //OUTPUT : Frame Type Indication
2370 
                .pkt_class_valid_18(pkt_class_valid_18),    //OUTPUT : Frame Type Indication Valid
2371 
                .data_tx_error_18(data_tx_error_18),        //INPUT  : Status
2372 
                .data_tx_data_18(data_tx_data_18),          //INPUT  : Data from FIFO transmit
2373 
                .data_tx_valid_18(data_tx_valid_18),        //INPUT  : Data FIFO transmit Empty
2374 
                .data_tx_sop_18(data_tx_sop_18),            //INPUT  : Start of Packet
2375 
                .data_tx_eop_18(data_tx_eop_18),            //INPUT  : End of Packet
2376 
                .data_tx_ready_18(data_tx_ready_18),        //OUTPUT : Data FIFO transmit Read Enable
2377 
                .tx_ff_uflow_18(tx_ff_uflow_18),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2378 
                .tx_crc_fwd_18(tx_crc_fwd_18),              //INPUT  : Forward Current Frame with CRC from Application
2379 
                .xoff_gen_18(xoff_gen_18),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2380 
                .xon_gen_18(xon_gen_18),                    //INPUT  : XON PAUSE FRAME GENERATE
2381 
                .magic_sleep_n_18(magic_sleep_n_18),        //INPUT  : MAC SLEEP MODE CONTROL
2382 
                .magic_wakeup_18(magic_wakeup_18),          //OUTPUT : MAC WAKE-UP INDICATION
2383 
 
2384 
             // Channel 19
2385 
 
2386 
                .rx_clk_19(rx_clk_19),                      //INPUT  : MAC RX CLK
2387 
                .tx_clk_19(tx_clk_19),                      //INPUT  : MAC TX CLK
2388 
                .gm_rx_d_19(gm_rx_d_19),                    //INPUT  : GMII RX DATA
2389 
                .gm_rx_dv_19(gm_rx_dv_19),                  //INPUT  : GMII RX VALID INDICATION
2390 
                .gm_rx_err_19(gm_rx_err_19),                //INPUT  : GMII RX ERROR INDICATION
2391 
                .gm_tx_d_19(gm_tx_d_19),                    //OUTPUT : GMII TX DATA
2392 
                .gm_tx_en_19(gm_tx_en_19),                  //OUTPUT : GMII TX VALID INDICATION
2393 
                .gm_tx_err_19(gm_tx_err_19),                //OUTPUT : GMII TX ERROR INDICATION
2394 
                .m_rx_crs_19(m_rx_crs_19),                  //INPUT  : MII RX CARRIER SENSE
2395 
                .m_rx_col_19(m_rx_col_19),                  //INPUT  : MII RX COLLISION
2396 
                .m_rx_d_19(m_rx_d_19),                      //INPUT  : MII RX DATA
2397 
                .m_rx_en_19(m_rx_en_19),                    //INPUT  : MII RX VALID INDICATION
2398 
                .m_rx_err_19(m_rx_err_19),                  //INPUT  : MII RX ERROR INDICATION
2399 
                .m_tx_d_19(m_tx_d_19),                      //OUTPUT : MII TX DATA
2400 
                .m_tx_en_19(m_tx_en_19),                    //OUTPUT : MII TX VALID INDICATION
2401 
                .m_tx_err_19(m_tx_err_19),                  //OUTPUT : MII TX ERROR INDICATION
2402 
                .rx_control_19(rx_control_19),              //INPUT  : RGMII RX CONTROL INDICATION
2403 
                .rgmii_in_19(rgmii_in_19),                  //INPUT  : RGMII RX DATA INDICATION
2404 
                .tx_control_19(tx_control_19),              //OUTPUT : RGMII TX CONTROL INDICATION
2405 
                .rgmii_out_19(rgmii_out_19),                //OUTPUT : RGMII TX DATA INDICATION
2406 
                .eth_mode_19(eth_mode_19),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2407 
                .ena_10_19(ena_10_19),                      //OUTPUT : SPEED 10 MBPS INDICATION
2408 
                .set_10_19(set_10_19),                      //INPUT  : SPEED 10 MBPS
2409 
                .set_1000_19(set_1000_19),                  //INPUT  : SPEED 1000 MBPS
2410 
                .mac_rx_clk_19(mac_rx_clk_19),              //OUTPUT : Av-ST Rx Clock
2411 
            .mac_tx_clk_19(mac_tx_clk_19),              //OUTPUT : Av-ST Tx Clock
2412 
                .data_rx_sop_19(data_rx_sop_19),            //OUTPUT : Start of Packet
2413 
                .data_rx_eop_19(data_rx_eop_19),            //OUTPUT : End of Packet
2414 
                .data_rx_data_19(data_rx_data_19),          //OUTPUT : Data from FIFO
2415 
                .data_rx_error_19(data_rx_error_19),        //OUTPUT : Receive packet error
2416 
                .data_rx_valid_19(data_rx_valid_19),        //OUTPUT : Data Receive FIFO Valid
2417 
                .data_rx_ready_19(data_rx_ready_19),        //OUTPUT : Data Receive Ready
2418 
                .pkt_class_data_19(pkt_class_data_19),      //OUTPUT : Frame Type Indication
2419 
                .pkt_class_valid_19(pkt_class_valid_19),    //OUTPUT : Frame Type Indication Valid
2420 
                .data_tx_error_19(data_tx_error_19),        //INPUT  : Status
2421 
                .data_tx_data_19(data_tx_data_19),          //INPUT  : Data from FIFO transmit
2422 
                .data_tx_valid_19(data_tx_valid_19),        //INPUT  : Data FIFO transmit Empty
2423 
                .data_tx_sop_19(data_tx_sop_19),            //INPUT  : Start of Packet
2424 
                .data_tx_eop_19(data_tx_eop_19),            //INPUT  : End of Packet
2425 
                .data_tx_ready_19(data_tx_ready_19),        //OUTPUT : Data FIFO transmit Read Enable
2426 
                .tx_ff_uflow_19(tx_ff_uflow_19),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2427 
                .tx_crc_fwd_19(tx_crc_fwd_19),              //INPUT  : Forward Current Frame with CRC from Application
2428 
                .xoff_gen_19(xoff_gen_19),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2429 
                .xon_gen_19(xon_gen_19),                    //INPUT  : XON PAUSE FRAME GENERATE
2430 
                .magic_sleep_n_19(magic_sleep_n_19),        //INPUT  : MAC SLEEP MODE CONTROL
2431 
                .magic_wakeup_19(magic_wakeup_19),          //OUTPUT : MAC WAKE-UP INDICATION
2432 
 
2433 
             // Channel 20
2434 
 
2435 
                .rx_clk_20(rx_clk_20),                      //INPUT  : MAC RX CLK
2436 
                .tx_clk_20(tx_clk_20),                      //INPUT  : MAC TX CLK
2437 
                .gm_rx_d_20(gm_rx_d_20),                    //INPUT  : GMII RX DATA
2438 
                .gm_rx_dv_20(gm_rx_dv_20),                  //INPUT  : GMII RX VALID INDICATION
2439 
                .gm_rx_err_20(gm_rx_err_20),                //INPUT  : GMII RX ERROR INDICATION
2440 
                .gm_tx_d_20(gm_tx_d_20),                    //OUTPUT : GMII TX DATA
2441 
                .gm_tx_en_20(gm_tx_en_20),                  //OUTPUT : GMII TX VALID INDICATION
2442 
                .gm_tx_err_20(gm_tx_err_20),                //OUTPUT : GMII TX ERROR INDICATION
2443 
                .m_rx_crs_20(m_rx_crs_20),                  //INPUT  : MII RX CARRIER SENSE
2444 
                .m_rx_col_20(m_rx_col_20),                  //INPUT  : MII RX COLLISION
2445 
                .m_rx_d_20(m_rx_d_20),                      //INPUT  : MII RX DATA
2446 
                .m_rx_en_20(m_rx_en_20),                    //INPUT  : MII RX VALID INDICATION
2447 
                .m_rx_err_20(m_rx_err_20),                  //INPUT  : MII RX ERROR INDICATION
2448 
                .m_tx_d_20(m_tx_d_20),                      //OUTPUT : MII TX DATA
2449 
                .m_tx_en_20(m_tx_en_20),                    //OUTPUT : MII TX VALID INDICATION
2450 
                .m_tx_err_20(m_tx_err_20),                  //OUTPUT : MII TX ERROR INDICATION
2451 
                .rx_control_20(rx_control_20),              //INPUT  : RGMII RX CONTROL INDICATION
2452 
                .rgmii_in_20(rgmii_in_20),                  //INPUT  : RGMII RX DATA INDICATION
2453 
                .tx_control_20(tx_control_20),              //OUTPUT : RGMII TX CONTROL INDICATION
2454 
                .rgmii_out_20(rgmii_out_20),                //OUTPUT : RGMII TX DATA INDICATION
2455 
                .eth_mode_20(eth_mode_20),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2456 
                .ena_10_20(ena_10_20),                      //OUTPUT : SPEED 10 MBPS INDICATION
2457 
                .set_10_20(set_10_20),                      //INPUT  : SPEED 10 MBPS
2458 
                .set_1000_20(set_1000_20),                  //INPUT  : SPEED 1000 MBPS
2459 
                .mac_rx_clk_20(mac_rx_clk_20),              //OUTPUT : Av-ST Rx Clock
2460 
            .mac_tx_clk_20(mac_tx_clk_20),              //OUTPUT : Av-ST Tx Clock
2461 
                .data_rx_sop_20(data_rx_sop_20),            //OUTPUT : Start of Packet
2462 
                .data_rx_eop_20(data_rx_eop_20),            //OUTPUT : End of Packet
2463 
                .data_rx_data_20(data_rx_data_20),          //OUTPUT : Data from FIFO
2464 
                .data_rx_error_20(data_rx_error_20),        //OUTPUT : Receive packet error
2465 
                .data_rx_valid_20(data_rx_valid_20),        //OUTPUT : Data Receive FIFO Valid
2466 
                .data_rx_ready_20(data_rx_ready_20),        //OUTPUT : Data Receive Ready
2467 
                .pkt_class_data_20(pkt_class_data_20),      //OUTPUT : Frame Type Indication
2468 
                .pkt_class_valid_20(pkt_class_valid_20),    //OUTPUT : Frame Type Indication Valid
2469 
                .data_tx_error_20(data_tx_error_20),        //INPUT  : Status
2470 
                .data_tx_data_20(data_tx_data_20),          //INPUT  : Data from FIFO transmit
2471 
                .data_tx_valid_20(data_tx_valid_20),        //INPUT  : Data FIFO transmit Empty
2472 
                .data_tx_sop_20(data_tx_sop_20),            //INPUT  : Start of Packet
2473 
                .data_tx_eop_20(data_tx_eop_20),            //INPUT  : End of Packet
2474 
                .data_tx_ready_20(data_tx_ready_20),        //OUTPUT : Data FIFO transmit Read Enable
2475 
                .tx_ff_uflow_20(tx_ff_uflow_20),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2476 
                .tx_crc_fwd_20(tx_crc_fwd_20),              //INPUT  : Forward Current Frame with CRC from Application
2477 
                .xoff_gen_20(xoff_gen_20),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2478 
                .xon_gen_20(xon_gen_20),                    //INPUT  : XON PAUSE FRAME GENERATE
2479 
                .magic_sleep_n_20(magic_sleep_n_20),        //INPUT  : MAC SLEEP MODE CONTROL
2480 
                .magic_wakeup_20(magic_wakeup_20),          //OUTPUT : MAC WAKE-UP INDICATION
2481 
 
2482 
             // Channel 21
2483 
 
2484 
                .rx_clk_21(rx_clk_21),                      //INPUT  : MAC RX CLK
2485 
                .tx_clk_21(tx_clk_21),                      //INPUT  : MAC TX CLK
2486 
                .gm_rx_d_21(gm_rx_d_21),                    //INPUT  : GMII RX DATA
2487 
                .gm_rx_dv_21(gm_rx_dv_21),                  //INPUT  : GMII RX VALID INDICATION
2488 
                .gm_rx_err_21(gm_rx_err_21),                //INPUT  : GMII RX ERROR INDICATION
2489 
                .gm_tx_d_21(gm_tx_d_21),                    //OUTPUT : GMII TX DATA
2490 
                .gm_tx_en_21(gm_tx_en_21),                  //OUTPUT : GMII TX VALID INDICATION
2491 
                .gm_tx_err_21(gm_tx_err_21),                //OUTPUT : GMII TX ERROR INDICATION
2492 
                .m_rx_crs_21(m_rx_crs_21),                  //INPUT  : MII RX CARRIER SENSE
2493 
                .m_rx_col_21(m_rx_col_21),                  //INPUT  : MII RX COLLISION
2494 
                .m_rx_d_21(m_rx_d_21),                      //INPUT  : MII RX DATA
2495 
                .m_rx_en_21(m_rx_en_21),                    //INPUT  : MII RX VALID INDICATION
2496 
                .m_rx_err_21(m_rx_err_21),                  //INPUT  : MII RX ERROR INDICATION
2497 
                .m_tx_d_21(m_tx_d_21),                      //OUTPUT : MII TX DATA
2498 
                .m_tx_en_21(m_tx_en_21),                    //OUTPUT : MII TX VALID INDICATION
2499 
                .m_tx_err_21(m_tx_err_21),                  //OUTPUT : MII TX ERROR INDICATION
2500 
                .rx_control_21(rx_control_21),              //INPUT  : RGMII RX CONTROL INDICATION
2501 
                .rgmii_in_21(rgmii_in_21),                  //INPUT  : RGMII RX DATA INDICATION
2502 
                .tx_control_21(tx_control_21),              //OUTPUT : RGMII TX CONTROL INDICATION
2503 
                .rgmii_out_21(rgmii_out_21),                //OUTPUT : RGMII TX DATA INDICATION
2504 
                .eth_mode_21(eth_mode_21),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2505 
                .ena_10_21(ena_10_21),                      //OUTPUT : SPEED 10 MBPS INDICATION
2506 
                .set_10_21(set_10_21),                      //INPUT  : SPEED 10 MBPS
2507 
                .set_1000_21(set_1000_21),                  //INPUT  : SPEED 1000 MBPS
2508 
                .mac_rx_clk_21(mac_rx_clk_21),              //OUTPUT : Av-ST Rx Clock
2509 
            .mac_tx_clk_21(mac_tx_clk_21),              //OUTPUT : Av-ST Tx Clock
2510 
                .data_rx_sop_21(data_rx_sop_21),            //OUTPUT : Start of Packet
2511 
                .data_rx_eop_21(data_rx_eop_21),            //OUTPUT : End of Packet
2512 
                .data_rx_data_21(data_rx_data_21),          //OUTPUT : Data from FIFO
2513 
                .data_rx_error_21(data_rx_error_21),        //OUTPUT : Receive packet error
2514 
                .data_rx_valid_21(data_rx_valid_21),        //OUTPUT : Data Receive FIFO Valid
2515 
                .data_rx_ready_21(data_rx_ready_21),        //OUTPUT : Data Receive Ready
2516 
                .pkt_class_data_21(pkt_class_data_21),      //OUTPUT : Frame Type Indication
2517 
                .pkt_class_valid_21(pkt_class_valid_21),    //OUTPUT : Frame Type Indication Valid
2518 
                .data_tx_error_21(data_tx_error_21),        //INPUT  : Status
2519 
                .data_tx_data_21(data_tx_data_21),          //INPUT  : Data from FIFO transmit
2520 
                .data_tx_valid_21(data_tx_valid_21),        //INPUT  : Data FIFO transmit Empty
2521 
                .data_tx_sop_21(data_tx_sop_21),            //INPUT  : Start of Packet
2522 
                .data_tx_eop_21(data_tx_eop_21),            //INPUT  : End of Packet
2523 
                .data_tx_ready_21(data_tx_ready_21),        //OUTPUT : Data FIFO transmit Read Enable
2524 
                .tx_ff_uflow_21(tx_ff_uflow_21),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2525 
                .tx_crc_fwd_21(tx_crc_fwd_21),              //INPUT  : Forward Current Frame with CRC from Application
2526 
                .xoff_gen_21(xoff_gen_21),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2527 
                .xon_gen_21(xon_gen_21),                    //INPUT  : XON PAUSE FRAME GENERATE
2528 
                .magic_sleep_n_21(magic_sleep_n_21),        //INPUT  : MAC SLEEP MODE CONTROL
2529 
                .magic_wakeup_21(magic_wakeup_21),          //OUTPUT : MAC WAKE-UP INDICATION
2530 
 
2531 
             // Channel 22
2532 
 
2533 
                .rx_clk_22(rx_clk_22),                      //INPUT  : MAC RX CLK
2534 
                .tx_clk_22(tx_clk_22),                      //INPUT  : MAC TX CLK
2535 
                .gm_rx_d_22(gm_rx_d_22),                    //INPUT  : GMII RX DATA
2536 
                .gm_rx_dv_22(gm_rx_dv_22),                  //INPUT  : GMII RX VALID INDICATION
2537 
                .gm_rx_err_22(gm_rx_err_22),                //INPUT  : GMII RX ERROR INDICATION
2538 
                .gm_tx_d_22(gm_tx_d_22),                    //OUTPUT : GMII TX DATA
2539 
                .gm_tx_en_22(gm_tx_en_22),                  //OUTPUT : GMII TX VALID INDICATION
2540 
                .gm_tx_err_22(gm_tx_err_22),                //OUTPUT : GMII TX ERROR INDICATION
2541 
                .m_rx_crs_22(m_rx_crs_22),                  //INPUT  : MII RX CARRIER SENSE
2542 
                .m_rx_col_22(m_rx_col_22),                  //INPUT  : MII RX COLLISION
2543 
                .m_rx_d_22(m_rx_d_22),                      //INPUT  : MII RX DATA
2544 
                .m_rx_en_22(m_rx_en_22),                    //INPUT  : MII RX VALID INDICATION
2545 
                .m_rx_err_22(m_rx_err_22),                  //INPUT  : MII RX ERROR INDICATION
2546 
                .m_tx_d_22(m_tx_d_22),                      //OUTPUT : MII TX DATA
2547 
                .m_tx_en_22(m_tx_en_22),                    //OUTPUT : MII TX VALID INDICATION
2548 
                .m_tx_err_22(m_tx_err_22),                  //OUTPUT : MII TX ERROR INDICATION
2549 
                .rx_control_22(rx_control_22),              //INPUT  : RGMII RX CONTROL INDICATION
2550 
                .rgmii_in_22(rgmii_in_22),                  //INPUT  : RGMII RX DATA INDICATION
2551 
                .tx_control_22(tx_control_22),              //OUTPUT : RGMII TX CONTROL INDICATION
2552 
                .rgmii_out_22(rgmii_out_22),                //OUTPUT : RGMII TX DATA INDICATION
2553 
                .eth_mode_22(eth_mode_22),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2554 
                .ena_10_22(ena_10_22),                      //OUTPUT : SPEED 10 MBPS INDICATION
2555 
                .set_10_22(set_10_22),                      //INPUT  : SPEED 10 MBPS
2556 
                .set_1000_22(set_1000_22),                  //INPUT  : SPEED 1000 MBPS
2557 
                .mac_rx_clk_22(mac_rx_clk_22),              //OUTPUT : Av-ST Rx Clock
2558 
            .mac_tx_clk_22(mac_tx_clk_22),              //OUTPUT : Av-ST Tx Clock
2559 
                .data_rx_sop_22(data_rx_sop_22),            //OUTPUT : Start of Packet
2560 
                .data_rx_eop_22(data_rx_eop_22),            //OUTPUT : End of Packet
2561 
                .data_rx_data_22(data_rx_data_22),          //OUTPUT : Data from FIFO
2562 
                .data_rx_error_22(data_rx_error_22),        //OUTPUT : Receive packet error
2563 
                .data_rx_valid_22(data_rx_valid_22),        //OUTPUT : Data Receive FIFO Valid
2564 
                .data_rx_ready_22(data_rx_ready_22),        //OUTPUT : Data Receive Ready
2565 
                .pkt_class_data_22(pkt_class_data_22),      //OUTPUT : Frame Type Indication
2566 
                .pkt_class_valid_22(pkt_class_valid_22),    //OUTPUT : Frame Type Indication Valid
2567 
                .data_tx_error_22(data_tx_error_22),        //INPUT  : Status
2568 
                .data_tx_data_22(data_tx_data_22),          //INPUT  : Data from FIFO transmit
2569 
                .data_tx_valid_22(data_tx_valid_22),        //INPUT  : Data FIFO transmit Empty
2570 
                .data_tx_sop_22(data_tx_sop_22),            //INPUT  : Start of Packet
2571 
                .data_tx_eop_22(data_tx_eop_22),            //INPUT  : End of Packet
2572 
                .data_tx_ready_22(data_tx_ready_22),        //OUTPUT : Data FIFO transmit Read Enable
2573 
                .tx_ff_uflow_22(tx_ff_uflow_22),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2574 
                .tx_crc_fwd_22(tx_crc_fwd_22),              //INPUT  : Forward Current Frame with CRC from Application
2575 
                .xoff_gen_22(xoff_gen_22),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2576 
                .xon_gen_22(xon_gen_22),                    //INPUT  : XON PAUSE FRAME GENERATE
2577 
                .magic_sleep_n_22(magic_sleep_n_22),        //INPUT  : MAC SLEEP MODE CONTROL
2578 
                .magic_wakeup_22(magic_wakeup_22),          //OUTPUT : MAC WAKE-UP INDICATION
2579 
 
2580 
 
2581 
             // Channel 23
2582 
 
2583 
                .rx_clk_23(rx_clk_23),                      //INPUT  : MAC RX CLK
2584 
                .tx_clk_23(tx_clk_23),                      //INPUT  : MAC TX CLK
2585 
                .gm_rx_d_23(gm_rx_d_23),                    //INPUT  : GMII RX DATA
2586 
                .gm_rx_dv_23(gm_rx_dv_23),                  //INPUT  : GMII RX VALID INDICATION
2587 
                .gm_rx_err_23(gm_rx_err_23),                //INPUT  : GMII RX ERROR INDICATION
2588 
                .gm_tx_d_23(gm_tx_d_23),                    //OUTPUT : GMII TX DATA
2589 
                .gm_tx_en_23(gm_tx_en_23),                  //OUTPUT : GMII TX VALID INDICATION
2590 
                .gm_tx_err_23(gm_tx_err_23),                //OUTPUT : GMII TX ERROR INDICATION
2591 
                .m_rx_crs_23(m_rx_crs_23),                  //INPUT  : MII RX CARRIER SENSE
2592 
                .m_rx_col_23(m_rx_col_23),                  //INPUT  : MII RX COLLISION
2593 
                .m_rx_d_23(m_rx_d_23),                      //INPUT  : MII RX DATA
2594 
                .m_rx_en_23(m_rx_en_23),                    //INPUT  : MII RX VALID INDICATION
2595 
                .m_rx_err_23(m_rx_err_23),                  //INPUT  : MII RX ERROR INDICATION
2596 
                .m_tx_d_23(m_tx_d_23),                      //OUTPUT : MII TX DATA
2597 
                .m_tx_en_23(m_tx_en_23),                    //OUTPUT : MII TX VALID INDICATION
2598 
                .m_tx_err_23(m_tx_err_23),                  //OUTPUT : MII TX ERROR INDICATION
2599 
                .rx_control_23(rx_control_23),              //INPUT  : RGMII RX CONTROL INDICATION
2600 
                .rgmii_in_23(rgmii_in_23),                  //INPUT  : RGMII RX DATA INDICATION
2601 
                .tx_control_23(tx_control_23),              //OUTPUT : RGMII TX CONTROL INDICATION
2602 
                .rgmii_out_23(rgmii_out_23),                //OUTPUT : RGMII TX DATA INDICATION
2603 
                .eth_mode_23(eth_mode_23),                  //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
2604 
                .ena_10_23(ena_10_23),                      //OUTPUT : SPEED 10 MBPS INDICATION
2605 
                .set_10_23(set_10_23),                      //INPUT  : SPEED 10 MBPS
2606 
                .set_1000_23(set_1000_23),                  //INPUT  : SPEED 1000 MBPS
2607 
                .mac_rx_clk_23(mac_rx_clk_23),              //OUTPUT : Av-ST Rx Clock
2608 
            .mac_tx_clk_23(mac_tx_clk_23),              //OUTPUT : Av-ST Tx Clock
2609 
                .data_rx_sop_23(data_rx_sop_23),            //OUTPUT : Start of Packet
2610 
                .data_rx_eop_23(data_rx_eop_23),            //OUTPUT : End of Packet
2611 
                .data_rx_data_23(data_rx_data_23),          //OUTPUT : Data from FIFO
2612 
                .data_rx_error_23(data_rx_error_23),        //OUTPUT : Receive packet error
2613 
                .data_rx_valid_23(data_rx_valid_23),        //OUTPUT : Data Receive FIFO Valid
2614 
                .data_rx_ready_23(data_rx_ready_23),        //OUTPUT : Data Receive Ready
2615 
                .pkt_class_data_23(pkt_class_data_23),      //OUTPUT : Frame Type Indication
2616 
                .pkt_class_valid_23(pkt_class_valid_23),    //OUTPUT : Frame Type Indication Valid
2617 
                .data_tx_error_23(data_tx_error_23),        //INPUT  : Status
2618 
                .data_tx_data_23(data_tx_data_23),          //INPUT  : Data from FIFO transmit
2619 
                .data_tx_valid_23(data_tx_valid_23),        //INPUT  : Data FIFO transmit Empty
2620 
                .data_tx_sop_23(data_tx_sop_23),            //INPUT  : Start of Packet
2621 
                .data_tx_eop_23(data_tx_eop_23),            //INPUT  : End of Packet
2622 
                .data_tx_ready_23(data_tx_ready_23),        //OUTPUT : Data FIFO transmit Read Enable
2623 
                .tx_ff_uflow_23(tx_ff_uflow_23),            //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
2624 
                .tx_crc_fwd_23(tx_crc_fwd_23),              //INPUT  : Forward Current Frame with CRC from Application
2625 
                .xoff_gen_23(xoff_gen_23),                  //INPUT  : XOFF PAUSE FRAME GENERATE
2626 
                .xon_gen_23(xon_gen_23),                    //INPUT  : XON PAUSE FRAME GENERATE
2627 
                .magic_sleep_n_23(magic_sleep_n_23),        //INPUT  : MAC SLEEP MODE CONTROL
2628 
                .magic_wakeup_23(magic_wakeup_23));         //OUTPUT : MAC WAKE-UP INDICATION
2629 
 
2630 
            defparam
2631 
                U_TOP_MULTI_MAC.USE_SYNC_RESET = USE_SYNC_RESET,
2632 
                U_TOP_MULTI_MAC.RESET_LEVEL = RESET_LEVEL,
2633 
                U_TOP_MULTI_MAC.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
2634 
                U_TOP_MULTI_MAC.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
2635 
                U_TOP_MULTI_MAC.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
2636 
                U_TOP_MULTI_MAC.ENA_HASH = ENA_HASH,
2637 
                U_TOP_MULTI_MAC.STAT_CNT_ENA = STAT_CNT_ENA,
2638 
                U_TOP_MULTI_MAC.CORE_VERSION = CORE_VERSION,
2639 
                U_TOP_MULTI_MAC.CUST_VERSION = CUST_VERSION,
2640 
                U_TOP_MULTI_MAC.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
2641 
                U_TOP_MULTI_MAC.ENABLE_MDIO = ENABLE_MDIO,
2642 
                U_TOP_MULTI_MAC.MDIO_CLK_DIV = MDIO_CLK_DIV,
2643 
                U_TOP_MULTI_MAC.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
2644 
                U_TOP_MULTI_MAC.CRC32DWIDTH = CRC32DWIDTH,
2645 
                U_TOP_MULTI_MAC.CRC32GENDELAY = CRC32GENDELAY,
2646 
                U_TOP_MULTI_MAC.CRC32CHECK16BIT = CRC32CHECK16BIT,
2647 
                U_TOP_MULTI_MAC.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
2648 
                U_TOP_MULTI_MAC.ENABLE_SHIFT16 = ENABLE_SHIFT16,
2649 
                U_TOP_MULTI_MAC.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
2650 
                U_TOP_MULTI_MAC.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
2651 
                U_TOP_MULTI_MAC.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
2652 
                U_TOP_MULTI_MAC.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
2653 
                U_TOP_MULTI_MAC.ADDR_WIDTH = ADDR_WIDTH,
2654 
                U_TOP_MULTI_MAC.MAX_CHANNELS = MAX_CHANNELS,
2655 
                U_TOP_MULTI_MAC.CHANNEL_WIDTH = CHANNEL_WIDTH,
2656 
                U_TOP_MULTI_MAC.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
2657 
                U_TOP_MULTI_MAC.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
2658 
                U_TOP_MULTI_MAC.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
2659 
                        U_TOP_MULTI_MAC.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
2660 
                U_TOP_MULTI_MAC.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING;
2661 
 
2662 
 
2663 
 
2664 
 
2665 
endmodule // module altera_tse_multi_mac

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.