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jefflieu |
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: altera_tse_multi_mac_pcs.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs.v,v $
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//
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// $Revision: #1 $
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jefflieu |
// $Date: 2012/06/21 $
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// Check in by : $Author: swbranch $
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9 |
jefflieu |
// Author : Arul Paniandi
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//
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// Project : Triple Speed Ethernet - 10/100/1000 MAC
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//
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// Description :
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//
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// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
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// interfaces, mdio module and register space (statistic, control and
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// management)
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
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module altera_tse_multi_mac_pcs
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/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,C105\"" */
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#(
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parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
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parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
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parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
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parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
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parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
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parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
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parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
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parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
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parameter CORE_VERSION = 16'h3, // ALTERA Core Version
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parameter CUST_VERSION = 1 , // Customer Core Version
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parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
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parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
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parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
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parameter ENABLE_PADDING = 1, // Enable padding operation.
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parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
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parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
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parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
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parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
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parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
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parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
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parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
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parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
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parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
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parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
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parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
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parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
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parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
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parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
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parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
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parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
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parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
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parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
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parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
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parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
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parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
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parameter CHANNEL_WIDTH = 1, // The width of the channel interface
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parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
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parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
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// Internal parameters
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parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
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(MAX_CHANNELS > 8)? 12 :
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(MAX_CHANNELS > 4)? 11 :
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(MAX_CHANNELS > 2)? 10 :
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(MAX_CHANNELS > 1)? 9 : 8
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)
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// Port List
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(
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// RESET / MAC REG IF / MDIO
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input wire reset, // Asynchronous Reset - clk Domain
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input wire clk, // 25MHz Host Interface Clock
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input wire read, // Register Read Strobe
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input wire write, // Register Write Strobe
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input wire [ADDR_WIDTH-1:0] address, // Register Address
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input wire [31:0] writedata, // Write Data for Host Bus
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output wire [31:0] readdata, // Read Data to Host Bus
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output wire waitrequest, // Interface Busy
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output wire mdc, // 2.5MHz Inteface
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input wire mdio_in, // MDIO Input
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output wire mdio_out, // MDIO Output
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output wire mdio_oen, // MDIO Output Enable
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input wire ref_clk, // Reference Clock
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// SHARED CLK SIGNALS
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output wire mac_rx_clk, // Av-ST Receive Clock
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output wire mac_tx_clk, // Av-ST Transmit Clock
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// SHARED RX STATUS
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input wire rx_afull_clk, // Almost full clk
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input wire [1:0] rx_afull_data, // Almost full data
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input wire rx_afull_valid, // Almost full valid
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input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
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// CHANNEL 0
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// PCS SIGNALS TO PHY
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input wire tbi_rx_clk_0, // 125MHz Recoved Clock
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input wire tbi_tx_clk_0, // 125MHz Transmit Clock
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input wire [9:0] tbi_rx_d_0, // Non Aligned 10-Bit Characters
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output wire [9:0] tbi_tx_d_0, // Transmit TBI Interface
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output wire sd_loopback_0, // SERDES Loopback Enable
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output wire powerdown_0, // Powerdown Enable
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output wire led_crs_0, // Carrier Sense
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output wire led_link_0, // Valid Link
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output wire led_col_0, // Collision Indication
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output wire led_an_0, // Auto-Negotiation Status
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output wire led_char_err_0, // Character Error
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output wire led_disp_err_0, // Disparity Error
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// AV-ST TX & RX
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output wire mac_rx_clk_0, // Av-ST Receive Clock
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output wire mac_tx_clk_0, // Av-ST Transmit Clock
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output wire data_rx_sop_0, // Start of Packet
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output wire data_rx_eop_0, // End of Packet
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output wire [7:0] data_rx_data_0, // Data from FIFO
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output wire [4:0] data_rx_error_0, // Receive packet error
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output wire data_rx_valid_0, // Data Receive FIFO Valid
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input wire data_rx_ready_0, // Data Receive Ready
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output wire [4:0] pkt_class_data_0, // Frame Type Indication
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output wire pkt_class_valid_0, // Frame Type Indication Valid
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input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
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input wire [7:0] data_tx_data_0, // Data from FIFO transmit
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input wire data_tx_valid_0, // Data FIFO transmit Empty
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input wire data_tx_sop_0, // Start of Packet
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input wire data_tx_eop_0, // END of Packet
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output wire data_tx_ready_0, // Data FIFO transmit Read Enable
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// STAND_ALONE CONDUITS
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output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
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input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
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input wire xoff_gen_0, // Xoff Pause frame generate
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input wire xon_gen_0, // Xon Pause frame generate
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input wire magic_sleep_n_0, // Enable Sleep Mode
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output wire magic_wakeup_0, // Wake Up Request
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// CHANNEL 1
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// PCS SIGNALS TO PHY
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input wire tbi_rx_clk_1, // 125MHz Recoved Clock
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input wire tbi_tx_clk_1, // 125MHz Transmit Clock
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input wire [9:0] tbi_rx_d_1, // Non Aligned 10-Bit Characters
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output wire [9:0] tbi_tx_d_1, // Transmit TBI Interface
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output wire sd_loopback_1, // SERDES Loopback Enable
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output wire powerdown_1, // Powerdown Enable
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output wire led_crs_1, // Carrier Sense
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output wire led_link_1, // Valid Link
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output wire led_col_1, // Collision Indication
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output wire led_an_1, // Auto-Negotiation Status
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output wire led_char_err_1, // Character Error
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output wire led_disp_err_1, // Disparity Error
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// AV-ST TX & RX
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output wire mac_rx_clk_1, // Av-ST Receive Clock
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output wire mac_tx_clk_1, // Av-ST Transmit Clock
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output wire data_rx_sop_1, // Start of Packet
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output wire data_rx_eop_1, // End of Packet
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output wire [7:0] data_rx_data_1, // Data from FIFO
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output wire [4:0] data_rx_error_1, // Receive packet error
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output wire data_rx_valid_1, // Data Receive FIFO Valid
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input wire data_rx_ready_1, // Data Receive Ready
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output wire [4:0] pkt_class_data_1, // Frame Type Indication
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output wire pkt_class_valid_1, // Frame Type Indication Valid
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input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
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input wire [7:0] data_tx_data_1, // Data from FIFO transmit
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input wire data_tx_valid_1, // Data FIFO transmit Empty
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input wire data_tx_sop_1, // Start of Packet
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input wire data_tx_eop_1, // END of Packet
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output wire data_tx_ready_1, // Data FIFO transmit Read Enable
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// STAND_ALONE CONDUITS
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output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
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input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
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input wire xoff_gen_1, // Xoff Pause frame generate
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input wire xon_gen_1, // Xon Pause frame generate
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input wire magic_sleep_n_1, // Enable Sleep Mode
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output wire magic_wakeup_1, // Wake Up Request
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// CHANNEL 2
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// PCS SIGNALS TO PHY
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input wire tbi_rx_clk_2, // 125MHz Recoved Clock
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input wire tbi_tx_clk_2, // 125MHz Transmit Clock
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| 202 |
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input wire [9:0] tbi_rx_d_2, // Non Aligned 10-Bit Characters
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| 203 |
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output wire [9:0] tbi_tx_d_2, // Transmit TBI Interface
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| 204 |
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output wire sd_loopback_2, // SERDES Loopback Enable
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output wire powerdown_2, // Powerdown Enable
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output wire led_crs_2, // Carrier Sense
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output wire led_link_2, // Valid Link
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output wire led_col_2, // Collision Indication
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| 209 |
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output wire led_an_2, // Auto-Negotiation Status
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| 210 |
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output wire led_char_err_2, // Character Error
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| 211 |
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output wire led_disp_err_2, // Disparity Error
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| 212 |
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// AV-ST TX & RX
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| 214 |
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output wire mac_rx_clk_2, // Av-ST Receive Clock
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| 215 |
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output wire mac_tx_clk_2, // Av-ST Transmit Clock
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| 216 |
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output wire data_rx_sop_2, // Start of Packet
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| 217 |
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output wire data_rx_eop_2, // End of Packet
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| 218 |
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output wire [7:0] data_rx_data_2, // Data from FIFO
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| 219 |
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output wire [4:0] data_rx_error_2, // Receive packet error
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| 220 |
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output wire data_rx_valid_2, // Data Receive FIFO Valid
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| 221 |
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input wire data_rx_ready_2, // Data Receive Ready
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| 222 |
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output wire [4:0] pkt_class_data_2, // Frame Type Indication
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| 223 |
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output wire pkt_class_valid_2, // Frame Type Indication Valid
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| 224 |
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input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
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| 225 |
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input wire [7:0] data_tx_data_2, // Data from FIFO transmit
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| 226 |
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input wire data_tx_valid_2, // Data FIFO transmit Empty
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| 227 |
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input wire data_tx_sop_2, // Start of Packet
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| 228 |
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input wire data_tx_eop_2, // END of Packet
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| 229 |
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output wire data_tx_ready_2, // Data FIFO transmit Read Enable
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| 230 |
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| 231 |
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// STAND_ALONE CONDUITS
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| 232 |
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output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
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| 233 |
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input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
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| 234 |
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input wire xoff_gen_2, // Xoff Pause frame generate
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| 235 |
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input wire xon_gen_2, // Xon Pause frame generate
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| 236 |
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input wire magic_sleep_n_2, // Enable Sleep Mode
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| 237 |
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output wire magic_wakeup_2, // Wake Up Request
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| 238 |
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| 239 |
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| 240 |
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// CHANNEL 3
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| 241 |
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| 242 |
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// PCS SIGNALS TO PHY
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| 243 |
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input wire tbi_rx_clk_3, // 125MHz Recoved Clock
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| 244 |
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input wire tbi_tx_clk_3, // 125MHz Transmit Clock
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| 245 |
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input wire [9:0] tbi_rx_d_3, // Non Aligned 10-Bit Characters
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| 246 |
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output wire [9:0] tbi_tx_d_3, // Transmit TBI Interface
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| 247 |
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output wire sd_loopback_3, // SERDES Loopback Enable
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| 248 |
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output wire powerdown_3, // Powerdown Enable
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| 249 |
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output wire led_crs_3, // Carrier Sense
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| 250 |
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output wire led_link_3, // Valid Link
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| 251 |
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output wire led_col_3, // Collision Indication
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| 252 |
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output wire led_an_3, // Auto-Negotiation Status
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| 253 |
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output wire led_char_err_3, // Character Error
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| 254 |
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output wire led_disp_err_3, // Disparity Error
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| 255 |
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| 256 |
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// AV-ST TX & RX
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| 257 |
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output wire mac_rx_clk_3, // Av-ST Receive Clock
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| 258 |
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output wire mac_tx_clk_3, // Av-ST Transmit Clock
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| 259 |
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output wire data_rx_sop_3, // Start of Packet
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| 260 |
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output wire data_rx_eop_3, // End of Packet
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| 261 |
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output wire [7:0] data_rx_data_3, // Data from FIFO
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| 262 |
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output wire [4:0] data_rx_error_3, // Receive packet error
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| 263 |
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output wire data_rx_valid_3, // Data Receive FIFO Valid
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| 264 |
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input wire data_rx_ready_3, // Data Receive Ready
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| 265 |
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output wire [4:0] pkt_class_data_3, // Frame Type Indication
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| 266 |
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output wire pkt_class_valid_3, // Frame Type Indication Valid
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| 267 |
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input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
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| 268 |
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input wire [7:0] data_tx_data_3, // Data from FIFO transmit
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| 269 |
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input wire data_tx_valid_3, // Data FIFO transmit Empty
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| 270 |
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input wire data_tx_sop_3, // Start of Packet
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| 271 |
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input wire data_tx_eop_3, // END of Packet
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| 272 |
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output wire data_tx_ready_3, // Data FIFO transmit Read Enable
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| 273 |
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| 274 |
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// STAND_ALONE CONDUITS
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| 275 |
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output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
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| 276 |
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input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
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| 277 |
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|
input wire xoff_gen_3, // Xoff Pause frame generate
|
| 278 |
|
|
input wire xon_gen_3, // Xon Pause frame generate
|
| 279 |
|
|
input wire magic_sleep_n_3, // Enable Sleep Mode
|
| 280 |
|
|
output wire magic_wakeup_3, // Wake Up Request
|
| 281 |
|
|
|
| 282 |
|
|
|
| 283 |
|
|
// CHANNEL 4
|
| 284 |
|
|
|
| 285 |
|
|
// PCS SIGNALS TO PHY
|
| 286 |
|
|
input wire tbi_rx_clk_4, // 125MHz Recoved Clock
|
| 287 |
|
|
input wire tbi_tx_clk_4, // 125MHz Transmit Clock
|
| 288 |
|
|
input wire [9:0] tbi_rx_d_4, // Non Aligned 10-Bit Characters
|
| 289 |
|
|
output wire [9:0] tbi_tx_d_4, // Transmit TBI Interface
|
| 290 |
|
|
output wire sd_loopback_4, // SERDES Loopback Enable
|
| 291 |
|
|
output wire powerdown_4, // Powerdown Enable
|
| 292 |
|
|
output wire led_crs_4, // Carrier Sense
|
| 293 |
|
|
output wire led_link_4, // Valid Link
|
| 294 |
|
|
output wire led_col_4, // Collision Indication
|
| 295 |
|
|
output wire led_an_4, // Auto-Negotiation Status
|
| 296 |
|
|
output wire led_char_err_4, // Character Error
|
| 297 |
|
|
output wire led_disp_err_4, // Disparity Error
|
| 298 |
|
|
|
| 299 |
|
|
// AV-ST TX & RX
|
| 300 |
|
|
output wire mac_rx_clk_4, // Av-ST Receive Clock
|
| 301 |
|
|
output wire mac_tx_clk_4, // Av-ST Transmit Clock
|
| 302 |
|
|
output wire data_rx_sop_4, // Start of Packet
|
| 303 |
|
|
output wire data_rx_eop_4, // End of Packet
|
| 304 |
|
|
output wire [7:0] data_rx_data_4, // Data from FIFO
|
| 305 |
|
|
output wire [4:0] data_rx_error_4, // Receive packet error
|
| 306 |
|
|
output wire data_rx_valid_4, // Data Receive FIFO Valid
|
| 307 |
|
|
input wire data_rx_ready_4, // Data Receive Ready
|
| 308 |
|
|
output wire [4:0] pkt_class_data_4, // Frame Type Indication
|
| 309 |
|
|
output wire pkt_class_valid_4, // Frame Type Indication Valid
|
| 310 |
|
|
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
|
| 311 |
|
|
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
|
| 312 |
|
|
input wire data_tx_valid_4, // Data FIFO transmit Empty
|
| 313 |
|
|
input wire data_tx_sop_4, // Start of Packet
|
| 314 |
|
|
input wire data_tx_eop_4, // END of Packet
|
| 315 |
|
|
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
|
| 316 |
|
|
|
| 317 |
|
|
// STAND_ALONE CONDUITS
|
| 318 |
|
|
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 319 |
|
|
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
|
| 320 |
|
|
input wire xoff_gen_4, // Xoff Pause frame generate
|
| 321 |
|
|
input wire xon_gen_4, // Xon Pause frame generate
|
| 322 |
|
|
input wire magic_sleep_n_4, // Enable Sleep Mode
|
| 323 |
|
|
output wire magic_wakeup_4, // Wake Up Request
|
| 324 |
|
|
|
| 325 |
|
|
|
| 326 |
|
|
// CHANNEL 5
|
| 327 |
|
|
|
| 328 |
|
|
// PCS SIGNALS TO PHY
|
| 329 |
|
|
input wire tbi_rx_clk_5, // 125MHz Recoved Clock
|
| 330 |
|
|
input wire tbi_tx_clk_5, // 125MHz Transmit Clock
|
| 331 |
|
|
input wire [9:0] tbi_rx_d_5, // Non Aligned 10-Bit Characters
|
| 332 |
|
|
output wire [9:0] tbi_tx_d_5, // Transmit TBI Interface
|
| 333 |
|
|
output wire sd_loopback_5, // SERDES Loopback Enable
|
| 334 |
|
|
output wire powerdown_5, // Powerdown Enable
|
| 335 |
|
|
output wire led_crs_5, // Carrier Sense
|
| 336 |
|
|
output wire led_link_5, // Valid Link
|
| 337 |
|
|
output wire led_col_5, // Collision Indication
|
| 338 |
|
|
output wire led_an_5, // Auto-Negotiation Status
|
| 339 |
|
|
output wire led_char_err_5, // Character Error
|
| 340 |
|
|
output wire led_disp_err_5, // Disparity Error
|
| 341 |
|
|
|
| 342 |
|
|
// AV-ST TX & RX
|
| 343 |
|
|
output wire mac_rx_clk_5, // Av-ST Receive Clock
|
| 344 |
|
|
output wire mac_tx_clk_5, // Av-ST Transmit Clock
|
| 345 |
|
|
output wire data_rx_sop_5, // Start of Packet
|
| 346 |
|
|
output wire data_rx_eop_5, // End of Packet
|
| 347 |
|
|
output wire [7:0] data_rx_data_5, // Data from FIFO
|
| 348 |
|
|
output wire [4:0] data_rx_error_5, // Receive packet error
|
| 349 |
|
|
output wire data_rx_valid_5, // Data Receive FIFO Valid
|
| 350 |
|
|
input wire data_rx_ready_5, // Data Receive Ready
|
| 351 |
|
|
output wire [4:0] pkt_class_data_5, // Frame Type Indication
|
| 352 |
|
|
output wire pkt_class_valid_5, // Frame Type Indication Valid
|
| 353 |
|
|
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
|
| 354 |
|
|
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
|
| 355 |
|
|
input wire data_tx_valid_5, // Data FIFO transmit Empty
|
| 356 |
|
|
input wire data_tx_sop_5, // Start of Packet
|
| 357 |
|
|
input wire data_tx_eop_5, // END of Packet
|
| 358 |
|
|
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
|
| 359 |
|
|
|
| 360 |
|
|
// STAND_ALONE CONDUITS
|
| 361 |
|
|
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 362 |
|
|
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
|
| 363 |
|
|
input wire xoff_gen_5, // Xoff Pause frame generate
|
| 364 |
|
|
input wire xon_gen_5, // Xon Pause frame generate
|
| 365 |
|
|
input wire magic_sleep_n_5, // Enable Sleep Mode
|
| 366 |
|
|
output wire magic_wakeup_5, // Wake Up Request
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
// CHANNEL 6
|
| 370 |
|
|
|
| 371 |
|
|
// PCS SIGNALS TO PHY
|
| 372 |
|
|
input wire tbi_rx_clk_6, // 125MHz Recoved Clock
|
| 373 |
|
|
input wire tbi_tx_clk_6, // 125MHz Transmit Clock
|
| 374 |
|
|
input wire [9:0] tbi_rx_d_6, // Non Aligned 10-Bit Characters
|
| 375 |
|
|
output wire [9:0] tbi_tx_d_6, // Transmit TBI Interface
|
| 376 |
|
|
output wire sd_loopback_6, // SERDES Loopback Enable
|
| 377 |
|
|
output wire powerdown_6, // Powerdown Enable
|
| 378 |
|
|
output wire led_crs_6, // Carrier Sense
|
| 379 |
|
|
output wire led_link_6, // Valid Link
|
| 380 |
|
|
output wire led_col_6, // Collision Indication
|
| 381 |
|
|
output wire led_an_6, // Auto-Negotiation Status
|
| 382 |
|
|
output wire led_char_err_6, // Character Error
|
| 383 |
|
|
output wire led_disp_err_6, // Disparity Error
|
| 384 |
|
|
|
| 385 |
|
|
// AV-ST TX & RX
|
| 386 |
|
|
output wire mac_rx_clk_6, // Av-ST Receive Clock
|
| 387 |
|
|
output wire mac_tx_clk_6, // Av-ST Transmit Clock
|
| 388 |
|
|
output wire data_rx_sop_6, // Start of Packet
|
| 389 |
|
|
output wire data_rx_eop_6, // End of Packet
|
| 390 |
|
|
output wire [7:0] data_rx_data_6, // Data from FIFO
|
| 391 |
|
|
output wire [4:0] data_rx_error_6, // Receive packet error
|
| 392 |
|
|
output wire data_rx_valid_6, // Data Receive FIFO Valid
|
| 393 |
|
|
input wire data_rx_ready_6, // Data Receive Ready
|
| 394 |
|
|
output wire [4:0] pkt_class_data_6, // Frame Type Indication
|
| 395 |
|
|
output wire pkt_class_valid_6, // Frame Type Indication Valid
|
| 396 |
|
|
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
|
| 397 |
|
|
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
|
| 398 |
|
|
input wire data_tx_valid_6, // Data FIFO transmit Empty
|
| 399 |
|
|
input wire data_tx_sop_6, // Start of Packet
|
| 400 |
|
|
input wire data_tx_eop_6, // END of Packet
|
| 401 |
|
|
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
|
| 402 |
|
|
|
| 403 |
|
|
// STAND_ALONE CONDUITS
|
| 404 |
|
|
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 405 |
|
|
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
|
| 406 |
|
|
input wire xoff_gen_6, // Xoff Pause frame generate
|
| 407 |
|
|
input wire xon_gen_6, // Xon Pause frame generate
|
| 408 |
|
|
input wire magic_sleep_n_6, // Enable Sleep Mode
|
| 409 |
|
|
output wire magic_wakeup_6, // Wake Up Request
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
// CHANNEL 7
|
| 413 |
|
|
|
| 414 |
|
|
// PCS SIGNALS TO PHY
|
| 415 |
|
|
input wire tbi_rx_clk_7, // 125MHz Recoved Clock
|
| 416 |
|
|
input wire tbi_tx_clk_7, // 125MHz Transmit Clock
|
| 417 |
|
|
input wire [9:0] tbi_rx_d_7, // Non Aligned 10-Bit Characters
|
| 418 |
|
|
output wire [9:0] tbi_tx_d_7, // Transmit TBI Interface
|
| 419 |
|
|
output wire sd_loopback_7, // SERDES Loopback Enable
|
| 420 |
|
|
output wire powerdown_7, // Powerdown Enable
|
| 421 |
|
|
output wire led_crs_7, // Carrier Sense
|
| 422 |
|
|
output wire led_link_7, // Valid Link
|
| 423 |
|
|
output wire led_col_7, // Collision Indication
|
| 424 |
|
|
output wire led_an_7, // Auto-Negotiation Status
|
| 425 |
|
|
output wire led_char_err_7, // Character Error
|
| 426 |
|
|
output wire led_disp_err_7, // Disparity Error
|
| 427 |
|
|
|
| 428 |
|
|
// AV-ST TX & RX
|
| 429 |
|
|
output wire mac_rx_clk_7, // Av-ST Receive Clock
|
| 430 |
|
|
output wire mac_tx_clk_7, // Av-ST Transmit Clock
|
| 431 |
|
|
output wire data_rx_sop_7, // Start of Packet
|
| 432 |
|
|
output wire data_rx_eop_7, // End of Packet
|
| 433 |
|
|
output wire [7:0] data_rx_data_7, // Data from FIFO
|
| 434 |
|
|
output wire [4:0] data_rx_error_7, // Receive packet error
|
| 435 |
|
|
output wire data_rx_valid_7, // Data Receive FIFO Valid
|
| 436 |
|
|
input wire data_rx_ready_7, // Data Receive Ready
|
| 437 |
|
|
output wire [4:0] pkt_class_data_7, // Frame Type Indication
|
| 438 |
|
|
output wire pkt_class_valid_7, // Frame Type Indication Valid
|
| 439 |
|
|
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
|
| 440 |
|
|
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
|
| 441 |
|
|
input wire data_tx_valid_7, // Data FIFO transmit Empty
|
| 442 |
|
|
input wire data_tx_sop_7, // Start of Packet
|
| 443 |
|
|
input wire data_tx_eop_7, // END of Packet
|
| 444 |
|
|
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
|
| 445 |
|
|
|
| 446 |
|
|
// STAND_ALONE CONDUITS
|
| 447 |
|
|
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 448 |
|
|
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
|
| 449 |
|
|
input wire xoff_gen_7, // Xoff Pause frame generate
|
| 450 |
|
|
input wire xon_gen_7, // Xon Pause frame generate
|
| 451 |
|
|
input wire magic_sleep_n_7, // Enable Sleep Mode
|
| 452 |
|
|
output wire magic_wakeup_7, // Wake Up Request
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
// CHANNEL 8
|
| 456 |
|
|
|
| 457 |
|
|
// PCS SIGNALS TO PHY
|
| 458 |
|
|
input wire tbi_rx_clk_8, // 125MHz Recoved Clock
|
| 459 |
|
|
input wire tbi_tx_clk_8, // 125MHz Transmit Clock
|
| 460 |
|
|
input wire [9:0] tbi_rx_d_8, // Non Aligned 10-Bit Characters
|
| 461 |
|
|
output wire [9:0] tbi_tx_d_8, // Transmit TBI Interface
|
| 462 |
|
|
output wire sd_loopback_8, // SERDES Loopback Enable
|
| 463 |
|
|
output wire powerdown_8, // Powerdown Enable
|
| 464 |
|
|
output wire led_crs_8, // Carrier Sense
|
| 465 |
|
|
output wire led_link_8, // Valid Link
|
| 466 |
|
|
output wire led_col_8, // Collision Indication
|
| 467 |
|
|
output wire led_an_8, // Auto-Negotiation Status
|
| 468 |
|
|
output wire led_char_err_8, // Character Error
|
| 469 |
|
|
output wire led_disp_err_8, // Disparity Error
|
| 470 |
|
|
|
| 471 |
|
|
// AV-ST TX & RX
|
| 472 |
|
|
output wire mac_rx_clk_8, // Av-ST Receive Clock
|
| 473 |
|
|
output wire mac_tx_clk_8, // Av-ST Transmit Clock
|
| 474 |
|
|
output wire data_rx_sop_8, // Start of Packet
|
| 475 |
|
|
output wire data_rx_eop_8, // End of Packet
|
| 476 |
|
|
output wire [7:0] data_rx_data_8, // Data from FIFO
|
| 477 |
|
|
output wire [4:0] data_rx_error_8, // Receive packet error
|
| 478 |
|
|
output wire data_rx_valid_8, // Data Receive FIFO Valid
|
| 479 |
|
|
input wire data_rx_ready_8, // Data Receive Ready
|
| 480 |
|
|
output wire [4:0] pkt_class_data_8, // Frame Type Indication
|
| 481 |
|
|
output wire pkt_class_valid_8, // Frame Type Indication Valid
|
| 482 |
|
|
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
|
| 483 |
|
|
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
|
| 484 |
|
|
input wire data_tx_valid_8, // Data FIFO transmit Empty
|
| 485 |
|
|
input wire data_tx_sop_8, // Start of Packet
|
| 486 |
|
|
input wire data_tx_eop_8, // END of Packet
|
| 487 |
|
|
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
|
| 488 |
|
|
|
| 489 |
|
|
// STAND_ALONE CONDUITS
|
| 490 |
|
|
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 491 |
|
|
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
|
| 492 |
|
|
input wire xoff_gen_8, // Xoff Pause frame generate
|
| 493 |
|
|
input wire xon_gen_8, // Xon Pause frame generate
|
| 494 |
|
|
input wire magic_sleep_n_8, // Enable Sleep Mode
|
| 495 |
|
|
output wire magic_wakeup_8, // Wake Up Request
|
| 496 |
|
|
|
| 497 |
|
|
|
| 498 |
|
|
// CHANNEL 9
|
| 499 |
|
|
|
| 500 |
|
|
// PCS SIGNALS TO PHY
|
| 501 |
|
|
input wire tbi_rx_clk_9, // 125MHz Recoved Clock
|
| 502 |
|
|
input wire tbi_tx_clk_9, // 125MHz Transmit Clock
|
| 503 |
|
|
input wire [9:0] tbi_rx_d_9, // Non Aligned 10-Bit Characters
|
| 504 |
|
|
output wire [9:0] tbi_tx_d_9, // Transmit TBI Interface
|
| 505 |
|
|
output wire sd_loopback_9, // SERDES Loopback Enable
|
| 506 |
|
|
output wire powerdown_9, // Powerdown Enable
|
| 507 |
|
|
output wire led_crs_9, // Carrier Sense
|
| 508 |
|
|
output wire led_link_9, // Valid Link
|
| 509 |
|
|
output wire led_col_9, // Collision Indication
|
| 510 |
|
|
output wire led_an_9, // Auto-Negotiation Status
|
| 511 |
|
|
output wire led_char_err_9, // Character Error
|
| 512 |
|
|
output wire led_disp_err_9, // Disparity Error
|
| 513 |
|
|
|
| 514 |
|
|
// AV-ST TX & RX
|
| 515 |
|
|
output wire mac_rx_clk_9, // Av-ST Receive Clock
|
| 516 |
|
|
output wire mac_tx_clk_9, // Av-ST Transmit Clock
|
| 517 |
|
|
output wire data_rx_sop_9, // Start of Packet
|
| 518 |
|
|
output wire data_rx_eop_9, // End of Packet
|
| 519 |
|
|
output wire [7:0] data_rx_data_9, // Data from FIFO
|
| 520 |
|
|
output wire [4:0] data_rx_error_9, // Receive packet error
|
| 521 |
|
|
output wire data_rx_valid_9, // Data Receive FIFO Valid
|
| 522 |
|
|
input wire data_rx_ready_9, // Data Receive Ready
|
| 523 |
|
|
output wire [4:0] pkt_class_data_9, // Frame Type Indication
|
| 524 |
|
|
output wire pkt_class_valid_9, // Frame Type Indication Valid
|
| 525 |
|
|
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
|
| 526 |
|
|
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
|
| 527 |
|
|
input wire data_tx_valid_9, // Data FIFO transmit Empty
|
| 528 |
|
|
input wire data_tx_sop_9, // Start of Packet
|
| 529 |
|
|
input wire data_tx_eop_9, // END of Packet
|
| 530 |
|
|
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
|
| 531 |
|
|
|
| 532 |
|
|
// STAND_ALONE CONDUITS
|
| 533 |
|
|
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 534 |
|
|
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
|
| 535 |
|
|
input wire xoff_gen_9, // Xoff Pause frame generate
|
| 536 |
|
|
input wire xon_gen_9, // Xon Pause frame generate
|
| 537 |
|
|
input wire magic_sleep_n_9, // Enable Sleep Mode
|
| 538 |
|
|
output wire magic_wakeup_9, // Wake Up Request
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
// CHANNEL 10
|
| 542 |
|
|
|
| 543 |
|
|
// PCS SIGNALS TO PHY
|
| 544 |
|
|
input wire tbi_rx_clk_10, // 125MHz Recoved Clock
|
| 545 |
|
|
input wire tbi_tx_clk_10, // 125MHz Transmit Clock
|
| 546 |
|
|
input wire [9:0] tbi_rx_d_10, // Non Aligned 10-Bit Characters
|
| 547 |
|
|
output wire [9:0] tbi_tx_d_10, // Transmit TBI Interface
|
| 548 |
|
|
output wire sd_loopback_10, // SERDES Loopback Enable
|
| 549 |
|
|
output wire powerdown_10, // Powerdown Enable
|
| 550 |
|
|
output wire led_crs_10, // Carrier Sense
|
| 551 |
|
|
output wire led_link_10, // Valid Link
|
| 552 |
|
|
output wire led_col_10, // Collision Indication
|
| 553 |
|
|
output wire led_an_10, // Auto-Negotiation Status
|
| 554 |
|
|
output wire led_char_err_10, // Character Error
|
| 555 |
|
|
output wire led_disp_err_10, // Disparity Error
|
| 556 |
|
|
|
| 557 |
|
|
// AV-ST TX & RX
|
| 558 |
|
|
output wire mac_rx_clk_10, // Av-ST Receive Clock
|
| 559 |
|
|
output wire mac_tx_clk_10, // Av-ST Transmit Clock
|
| 560 |
|
|
output wire data_rx_sop_10, // Start of Packet
|
| 561 |
|
|
output wire data_rx_eop_10, // End of Packet
|
| 562 |
|
|
output wire [7:0] data_rx_data_10, // Data from FIFO
|
| 563 |
|
|
output wire [4:0] data_rx_error_10, // Receive packet error
|
| 564 |
|
|
output wire data_rx_valid_10, // Data Receive FIFO Valid
|
| 565 |
|
|
input wire data_rx_ready_10, // Data Receive Ready
|
| 566 |
|
|
output wire [4:0] pkt_class_data_10, // Frame Type Indication
|
| 567 |
|
|
output wire pkt_class_valid_10, // Frame Type Indication Valid
|
| 568 |
|
|
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
|
| 569 |
|
|
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
|
| 570 |
|
|
input wire data_tx_valid_10, // Data FIFO transmit Empty
|
| 571 |
|
|
input wire data_tx_sop_10, // Start of Packet
|
| 572 |
|
|
input wire data_tx_eop_10, // END of Packet
|
| 573 |
|
|
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
|
| 574 |
|
|
|
| 575 |
|
|
// STAND_ALONE CONDUITS
|
| 576 |
|
|
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 577 |
|
|
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
|
| 578 |
|
|
input wire xoff_gen_10, // Xoff Pause frame generate
|
| 579 |
|
|
input wire xon_gen_10, // Xon Pause frame generate
|
| 580 |
|
|
input wire magic_sleep_n_10, // Enable Sleep Mode
|
| 581 |
|
|
output wire magic_wakeup_10, // Wake Up Request
|
| 582 |
|
|
|
| 583 |
|
|
|
| 584 |
|
|
// CHANNEL 11
|
| 585 |
|
|
|
| 586 |
|
|
// PCS SIGNALS TO PHY
|
| 587 |
|
|
input wire tbi_rx_clk_11, // 125MHz Recoved Clock
|
| 588 |
|
|
input wire tbi_tx_clk_11, // 125MHz Transmit Clock
|
| 589 |
|
|
input wire [9:0] tbi_rx_d_11, // Non Aligned 10-Bit Characters
|
| 590 |
|
|
output wire [9:0] tbi_tx_d_11, // Transmit TBI Interface
|
| 591 |
|
|
output wire sd_loopback_11, // SERDES Loopback Enable
|
| 592 |
|
|
output wire powerdown_11, // Powerdown Enable
|
| 593 |
|
|
output wire led_crs_11, // Carrier Sense
|
| 594 |
|
|
output wire led_link_11, // Valid Link
|
| 595 |
|
|
output wire led_col_11, // Collision Indication
|
| 596 |
|
|
output wire led_an_11, // Auto-Negotiation Status
|
| 597 |
|
|
output wire led_char_err_11, // Character Error
|
| 598 |
|
|
output wire led_disp_err_11, // Disparity Error
|
| 599 |
|
|
|
| 600 |
|
|
// AV-ST TX & RX
|
| 601 |
|
|
output wire mac_rx_clk_11, // Av-ST Receive Clock
|
| 602 |
|
|
output wire mac_tx_clk_11, // Av-ST Transmit Clock
|
| 603 |
|
|
output wire data_rx_sop_11, // Start of Packet
|
| 604 |
|
|
output wire data_rx_eop_11, // End of Packet
|
| 605 |
|
|
output wire [7:0] data_rx_data_11, // Data from FIFO
|
| 606 |
|
|
output wire [4:0] data_rx_error_11, // Receive packet error
|
| 607 |
|
|
output wire data_rx_valid_11, // Data Receive FIFO Valid
|
| 608 |
|
|
input wire data_rx_ready_11, // Data Receive Ready
|
| 609 |
|
|
output wire [4:0] pkt_class_data_11, // Frame Type Indication
|
| 610 |
|
|
output wire pkt_class_valid_11, // Frame Type Indication Valid
|
| 611 |
|
|
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
|
| 612 |
|
|
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
|
| 613 |
|
|
input wire data_tx_valid_11, // Data FIFO transmit Empty
|
| 614 |
|
|
input wire data_tx_sop_11, // Start of Packet
|
| 615 |
|
|
input wire data_tx_eop_11, // END of Packet
|
| 616 |
|
|
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
|
| 617 |
|
|
|
| 618 |
|
|
// STAND_ALONE CONDUITS
|
| 619 |
|
|
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 620 |
|
|
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
|
| 621 |
|
|
input wire xoff_gen_11, // Xoff Pause frame generate
|
| 622 |
|
|
input wire xon_gen_11, // Xon Pause frame generate
|
| 623 |
|
|
input wire magic_sleep_n_11, // Enable Sleep Mode
|
| 624 |
|
|
output wire magic_wakeup_11, // Wake Up Request
|
| 625 |
|
|
|
| 626 |
|
|
|
| 627 |
|
|
// CHANNEL 12
|
| 628 |
|
|
|
| 629 |
|
|
// PCS SIGNALS TO PHY
|
| 630 |
|
|
input wire tbi_rx_clk_12, // 125MHz Recoved Clock
|
| 631 |
|
|
input wire tbi_tx_clk_12, // 125MHz Transmit Clock
|
| 632 |
|
|
input wire [9:0] tbi_rx_d_12, // Non Aligned 10-Bit Characters
|
| 633 |
|
|
output wire [9:0] tbi_tx_d_12, // Transmit TBI Interface
|
| 634 |
|
|
output wire sd_loopback_12, // SERDES Loopback Enable
|
| 635 |
|
|
output wire powerdown_12, // Powerdown Enable
|
| 636 |
|
|
output wire led_crs_12, // Carrier Sense
|
| 637 |
|
|
output wire led_link_12, // Valid Link
|
| 638 |
|
|
output wire led_col_12, // Collision Indication
|
| 639 |
|
|
output wire led_an_12, // Auto-Negotiation Status
|
| 640 |
|
|
output wire led_char_err_12, // Character Error
|
| 641 |
|
|
output wire led_disp_err_12, // Disparity Error
|
| 642 |
|
|
|
| 643 |
|
|
// AV-ST TX & RX
|
| 644 |
|
|
output wire mac_rx_clk_12, // Av-ST Receive Clock
|
| 645 |
|
|
output wire mac_tx_clk_12, // Av-ST Transmit Clock
|
| 646 |
|
|
output wire data_rx_sop_12, // Start of Packet
|
| 647 |
|
|
output wire data_rx_eop_12, // End of Packet
|
| 648 |
|
|
output wire [7:0] data_rx_data_12, // Data from FIFO
|
| 649 |
|
|
output wire [4:0] data_rx_error_12, // Receive packet error
|
| 650 |
|
|
output wire data_rx_valid_12, // Data Receive FIFO Valid
|
| 651 |
|
|
input wire data_rx_ready_12, // Data Receive Ready
|
| 652 |
|
|
output wire [4:0] pkt_class_data_12, // Frame Type Indication
|
| 653 |
|
|
output wire pkt_class_valid_12, // Frame Type Indication Valid
|
| 654 |
|
|
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
|
| 655 |
|
|
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
|
| 656 |
|
|
input wire data_tx_valid_12, // Data FIFO transmit Empty
|
| 657 |
|
|
input wire data_tx_sop_12, // Start of Packet
|
| 658 |
|
|
input wire data_tx_eop_12, // END of Packet
|
| 659 |
|
|
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
|
| 660 |
|
|
|
| 661 |
|
|
// STAND_ALONE CONDUITS
|
| 662 |
|
|
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 663 |
|
|
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
|
| 664 |
|
|
input wire xoff_gen_12, // Xoff Pause frame generate
|
| 665 |
|
|
input wire xon_gen_12, // Xon Pause frame generate
|
| 666 |
|
|
input wire magic_sleep_n_12, // Enable Sleep Mode
|
| 667 |
|
|
output wire magic_wakeup_12, // Wake Up Request
|
| 668 |
|
|
|
| 669 |
|
|
|
| 670 |
|
|
// CHANNEL 13
|
| 671 |
|
|
|
| 672 |
|
|
// PCS SIGNALS TO PHY
|
| 673 |
|
|
input wire tbi_rx_clk_13, // 125MHz Recoved Clock
|
| 674 |
|
|
input wire tbi_tx_clk_13, // 125MHz Transmit Clock
|
| 675 |
|
|
input wire [9:0] tbi_rx_d_13, // Non Aligned 10-Bit Characters
|
| 676 |
|
|
output wire [9:0] tbi_tx_d_13, // Transmit TBI Interface
|
| 677 |
|
|
output wire sd_loopback_13, // SERDES Loopback Enable
|
| 678 |
|
|
output wire powerdown_13, // Powerdown Enable
|
| 679 |
|
|
output wire led_crs_13, // Carrier Sense
|
| 680 |
|
|
output wire led_link_13, // Valid Link
|
| 681 |
|
|
output wire led_col_13, // Collision Indication
|
| 682 |
|
|
output wire led_an_13, // Auto-Negotiation Status
|
| 683 |
|
|
output wire led_char_err_13, // Character Error
|
| 684 |
|
|
output wire led_disp_err_13, // Disparity Error
|
| 685 |
|
|
|
| 686 |
|
|
// AV-ST TX & RX
|
| 687 |
|
|
output wire mac_rx_clk_13, // Av-ST Receive Clock
|
| 688 |
|
|
output wire mac_tx_clk_13, // Av-ST Transmit Clock
|
| 689 |
|
|
output wire data_rx_sop_13, // Start of Packet
|
| 690 |
|
|
output wire data_rx_eop_13, // End of Packet
|
| 691 |
|
|
output wire [7:0] data_rx_data_13, // Data from FIFO
|
| 692 |
|
|
output wire [4:0] data_rx_error_13, // Receive packet error
|
| 693 |
|
|
output wire data_rx_valid_13, // Data Receive FIFO Valid
|
| 694 |
|
|
input wire data_rx_ready_13, // Data Receive Ready
|
| 695 |
|
|
output wire [4:0] pkt_class_data_13, // Frame Type Indication
|
| 696 |
|
|
output wire pkt_class_valid_13, // Frame Type Indication Valid
|
| 697 |
|
|
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
|
| 698 |
|
|
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
|
| 699 |
|
|
input wire data_tx_valid_13, // Data FIFO transmit Empty
|
| 700 |
|
|
input wire data_tx_sop_13, // Start of Packet
|
| 701 |
|
|
input wire data_tx_eop_13, // END of Packet
|
| 702 |
|
|
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
|
| 703 |
|
|
|
| 704 |
|
|
// STAND_ALONE CONDUITS
|
| 705 |
|
|
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 706 |
|
|
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
|
| 707 |
|
|
input wire xoff_gen_13, // Xoff Pause frame generate
|
| 708 |
|
|
input wire xon_gen_13, // Xon Pause frame generate
|
| 709 |
|
|
input wire magic_sleep_n_13, // Enable Sleep Mode
|
| 710 |
|
|
output wire magic_wakeup_13, // Wake Up Request
|
| 711 |
|
|
|
| 712 |
|
|
|
| 713 |
|
|
// CHANNEL 14
|
| 714 |
|
|
|
| 715 |
|
|
// PCS SIGNALS TO PHY
|
| 716 |
|
|
input wire tbi_rx_clk_14, // 125MHz Recoved Clock
|
| 717 |
|
|
input wire tbi_tx_clk_14, // 125MHz Transmit Clock
|
| 718 |
|
|
input wire [9:0] tbi_rx_d_14, // Non Aligned 10-Bit Characters
|
| 719 |
|
|
output wire [9:0] tbi_tx_d_14, // Transmit TBI Interface
|
| 720 |
|
|
output wire sd_loopback_14, // SERDES Loopback Enable
|
| 721 |
|
|
output wire powerdown_14, // Powerdown Enable
|
| 722 |
|
|
output wire led_crs_14, // Carrier Sense
|
| 723 |
|
|
output wire led_link_14, // Valid Link
|
| 724 |
|
|
output wire led_col_14, // Collision Indication
|
| 725 |
|
|
output wire led_an_14, // Auto-Negotiation Status
|
| 726 |
|
|
output wire led_char_err_14, // Character Error
|
| 727 |
|
|
output wire led_disp_err_14, // Disparity Error
|
| 728 |
|
|
|
| 729 |
|
|
// AV-ST TX & RX
|
| 730 |
|
|
output wire mac_rx_clk_14, // Av-ST Receive Clock
|
| 731 |
|
|
output wire mac_tx_clk_14, // Av-ST Transmit Clock
|
| 732 |
|
|
output wire data_rx_sop_14, // Start of Packet
|
| 733 |
|
|
output wire data_rx_eop_14, // End of Packet
|
| 734 |
|
|
output wire [7:0] data_rx_data_14, // Data from FIFO
|
| 735 |
|
|
output wire [4:0] data_rx_error_14, // Receive packet error
|
| 736 |
|
|
output wire data_rx_valid_14, // Data Receive FIFO Valid
|
| 737 |
|
|
input wire data_rx_ready_14, // Data Receive Ready
|
| 738 |
|
|
output wire [4:0] pkt_class_data_14, // Frame Type Indication
|
| 739 |
|
|
output wire pkt_class_valid_14, // Frame Type Indication Valid
|
| 740 |
|
|
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
|
| 741 |
|
|
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
|
| 742 |
|
|
input wire data_tx_valid_14, // Data FIFO transmit Empty
|
| 743 |
|
|
input wire data_tx_sop_14, // Start of Packet
|
| 744 |
|
|
input wire data_tx_eop_14, // END of Packet
|
| 745 |
|
|
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
|
| 746 |
|
|
|
| 747 |
|
|
// STAND_ALONE CONDUITS
|
| 748 |
|
|
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 749 |
|
|
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
|
| 750 |
|
|
input wire xoff_gen_14, // Xoff Pause frame generate
|
| 751 |
|
|
input wire xon_gen_14, // Xon Pause frame generate
|
| 752 |
|
|
input wire magic_sleep_n_14, // Enable Sleep Mode
|
| 753 |
|
|
output wire magic_wakeup_14, // Wake Up Request
|
| 754 |
|
|
|
| 755 |
|
|
|
| 756 |
|
|
// CHANNEL 15
|
| 757 |
|
|
|
| 758 |
|
|
// PCS SIGNALS TO PHY
|
| 759 |
|
|
input wire tbi_rx_clk_15, // 125MHz Recoved Clock
|
| 760 |
|
|
input wire tbi_tx_clk_15, // 125MHz Transmit Clock
|
| 761 |
|
|
input wire [9:0] tbi_rx_d_15, // Non Aligned 10-Bit Characters
|
| 762 |
|
|
output wire [9:0] tbi_tx_d_15, // Transmit TBI Interface
|
| 763 |
|
|
output wire sd_loopback_15, // SERDES Loopback Enable
|
| 764 |
|
|
output wire powerdown_15, // Powerdown Enable
|
| 765 |
|
|
output wire led_crs_15, // Carrier Sense
|
| 766 |
|
|
output wire led_link_15, // Valid Link
|
| 767 |
|
|
output wire led_col_15, // Collision Indication
|
| 768 |
|
|
output wire led_an_15, // Auto-Negotiation Status
|
| 769 |
|
|
output wire led_char_err_15, // Character Error
|
| 770 |
|
|
output wire led_disp_err_15, // Disparity Error
|
| 771 |
|
|
|
| 772 |
|
|
// AV-ST TX & RX
|
| 773 |
|
|
output wire mac_rx_clk_15, // Av-ST Receive Clock
|
| 774 |
|
|
output wire mac_tx_clk_15, // Av-ST Transmit Clock
|
| 775 |
|
|
output wire data_rx_sop_15, // Start of Packet
|
| 776 |
|
|
output wire data_rx_eop_15, // End of Packet
|
| 777 |
|
|
output wire [7:0] data_rx_data_15, // Data from FIFO
|
| 778 |
|
|
output wire [4:0] data_rx_error_15, // Receive packet error
|
| 779 |
|
|
output wire data_rx_valid_15, // Data Receive FIFO Valid
|
| 780 |
|
|
input wire data_rx_ready_15, // Data Receive Ready
|
| 781 |
|
|
output wire [4:0] pkt_class_data_15, // Frame Type Indication
|
| 782 |
|
|
output wire pkt_class_valid_15, // Frame Type Indication Valid
|
| 783 |
|
|
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
|
| 784 |
|
|
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
|
| 785 |
|
|
input wire data_tx_valid_15, // Data FIFO transmit Empty
|
| 786 |
|
|
input wire data_tx_sop_15, // Start of Packet
|
| 787 |
|
|
input wire data_tx_eop_15, // END of Packet
|
| 788 |
|
|
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
|
| 789 |
|
|
|
| 790 |
|
|
// STAND_ALONE CONDUITS
|
| 791 |
|
|
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 792 |
|
|
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
|
| 793 |
|
|
input wire xoff_gen_15, // Xoff Pause frame generate
|
| 794 |
|
|
input wire xon_gen_15, // Xon Pause frame generate
|
| 795 |
|
|
input wire magic_sleep_n_15, // Enable Sleep Mode
|
| 796 |
|
|
output wire magic_wakeup_15, // Wake Up Request
|
| 797 |
|
|
|
| 798 |
|
|
|
| 799 |
|
|
// CHANNEL 16
|
| 800 |
|
|
|
| 801 |
|
|
// PCS SIGNALS TO PHY
|
| 802 |
|
|
input wire tbi_rx_clk_16, // 125MHz Recoved Clock
|
| 803 |
|
|
input wire tbi_tx_clk_16, // 125MHz Transmit Clock
|
| 804 |
|
|
input wire [9:0] tbi_rx_d_16, // Non Aligned 10-Bit Characters
|
| 805 |
|
|
output wire [9:0] tbi_tx_d_16, // Transmit TBI Interface
|
| 806 |
|
|
output wire sd_loopback_16, // SERDES Loopback Enable
|
| 807 |
|
|
output wire powerdown_16, // Powerdown Enable
|
| 808 |
|
|
output wire led_crs_16, // Carrier Sense
|
| 809 |
|
|
output wire led_link_16, // Valid Link
|
| 810 |
|
|
output wire led_col_16, // Collision Indication
|
| 811 |
|
|
output wire led_an_16, // Auto-Negotiation Status
|
| 812 |
|
|
output wire led_char_err_16, // Character Error
|
| 813 |
|
|
output wire led_disp_err_16, // Disparity Error
|
| 814 |
|
|
|
| 815 |
|
|
// AV-ST TX & RX
|
| 816 |
|
|
output wire mac_rx_clk_16, // Av-ST Receive Clock
|
| 817 |
|
|
output wire mac_tx_clk_16, // Av-ST Transmit Clock
|
| 818 |
|
|
output wire data_rx_sop_16, // Start of Packet
|
| 819 |
|
|
output wire data_rx_eop_16, // End of Packet
|
| 820 |
|
|
output wire [7:0] data_rx_data_16, // Data from FIFO
|
| 821 |
|
|
output wire [4:0] data_rx_error_16, // Receive packet error
|
| 822 |
|
|
output wire data_rx_valid_16, // Data Receive FIFO Valid
|
| 823 |
|
|
input wire data_rx_ready_16, // Data Receive Ready
|
| 824 |
|
|
output wire [4:0] pkt_class_data_16, // Frame Type Indication
|
| 825 |
|
|
output wire pkt_class_valid_16, // Frame Type Indication Valid
|
| 826 |
|
|
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
|
| 827 |
|
|
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
|
| 828 |
|
|
input wire data_tx_valid_16, // Data FIFO transmit Empty
|
| 829 |
|
|
input wire data_tx_sop_16, // Start of Packet
|
| 830 |
|
|
input wire data_tx_eop_16, // END of Packet
|
| 831 |
|
|
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
|
| 832 |
|
|
|
| 833 |
|
|
// STAND_ALONE CONDUITS
|
| 834 |
|
|
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 835 |
|
|
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
|
| 836 |
|
|
input wire xoff_gen_16, // Xoff Pause frame generate
|
| 837 |
|
|
input wire xon_gen_16, // Xon Pause frame generate
|
| 838 |
|
|
input wire magic_sleep_n_16, // Enable Sleep Mode
|
| 839 |
|
|
output wire magic_wakeup_16, // Wake Up Request
|
| 840 |
|
|
|
| 841 |
|
|
|
| 842 |
|
|
// CHANNEL 17
|
| 843 |
|
|
|
| 844 |
|
|
// PCS SIGNALS TO PHY
|
| 845 |
|
|
input wire tbi_rx_clk_17, // 125MHz Recoved Clock
|
| 846 |
|
|
input wire tbi_tx_clk_17, // 125MHz Transmit Clock
|
| 847 |
|
|
input wire [9:0] tbi_rx_d_17, // Non Aligned 10-Bit Characters
|
| 848 |
|
|
output wire [9:0] tbi_tx_d_17, // Transmit TBI Interface
|
| 849 |
|
|
output wire sd_loopback_17, // SERDES Loopback Enable
|
| 850 |
|
|
output wire powerdown_17, // Powerdown Enable
|
| 851 |
|
|
output wire led_crs_17, // Carrier Sense
|
| 852 |
|
|
output wire led_link_17, // Valid Link
|
| 853 |
|
|
output wire led_col_17, // Collision Indication
|
| 854 |
|
|
output wire led_an_17, // Auto-Negotiation Status
|
| 855 |
|
|
output wire led_char_err_17, // Character Error
|
| 856 |
|
|
output wire led_disp_err_17, // Disparity Error
|
| 857 |
|
|
|
| 858 |
|
|
// AV-ST TX & RX
|
| 859 |
|
|
output wire mac_rx_clk_17, // Av-ST Receive Clock
|
| 860 |
|
|
output wire mac_tx_clk_17, // Av-ST Transmit Clock
|
| 861 |
|
|
output wire data_rx_sop_17, // Start of Packet
|
| 862 |
|
|
output wire data_rx_eop_17, // End of Packet
|
| 863 |
|
|
output wire [7:0] data_rx_data_17, // Data from FIFO
|
| 864 |
|
|
output wire [4:0] data_rx_error_17, // Receive packet error
|
| 865 |
|
|
output wire data_rx_valid_17, // Data Receive FIFO Valid
|
| 866 |
|
|
input wire data_rx_ready_17, // Data Receive Ready
|
| 867 |
|
|
output wire [4:0] pkt_class_data_17, // Frame Type Indication
|
| 868 |
|
|
output wire pkt_class_valid_17, // Frame Type Indication Valid
|
| 869 |
|
|
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
|
| 870 |
|
|
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
|
| 871 |
|
|
input wire data_tx_valid_17, // Data FIFO transmit Empty
|
| 872 |
|
|
input wire data_tx_sop_17, // Start of Packet
|
| 873 |
|
|
input wire data_tx_eop_17, // END of Packet
|
| 874 |
|
|
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
|
| 875 |
|
|
|
| 876 |
|
|
// STAND_ALONE CONDUITS
|
| 877 |
|
|
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 878 |
|
|
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
|
| 879 |
|
|
input wire xoff_gen_17, // Xoff Pause frame generate
|
| 880 |
|
|
input wire xon_gen_17, // Xon Pause frame generate
|
| 881 |
|
|
input wire magic_sleep_n_17, // Enable Sleep Mode
|
| 882 |
|
|
output wire magic_wakeup_17, // Wake Up Request
|
| 883 |
|
|
|
| 884 |
|
|
|
| 885 |
|
|
// CHANNEL 18
|
| 886 |
|
|
|
| 887 |
|
|
// PCS SIGNALS TO PHY
|
| 888 |
|
|
input wire tbi_rx_clk_18, // 125MHz Recoved Clock
|
| 889 |
|
|
input wire tbi_tx_clk_18, // 125MHz Transmit Clock
|
| 890 |
|
|
input wire [9:0] tbi_rx_d_18, // Non Aligned 10-Bit Characters
|
| 891 |
|
|
output wire [9:0] tbi_tx_d_18, // Transmit TBI Interface
|
| 892 |
|
|
output wire sd_loopback_18, // SERDES Loopback Enable
|
| 893 |
|
|
output wire powerdown_18, // Powerdown Enable
|
| 894 |
|
|
output wire led_crs_18, // Carrier Sense
|
| 895 |
|
|
output wire led_link_18, // Valid Link
|
| 896 |
|
|
output wire led_col_18, // Collision Indication
|
| 897 |
|
|
output wire led_an_18, // Auto-Negotiation Status
|
| 898 |
|
|
output wire led_char_err_18, // Character Error
|
| 899 |
|
|
output wire led_disp_err_18, // Disparity Error
|
| 900 |
|
|
|
| 901 |
|
|
// AV-ST TX & RX
|
| 902 |
|
|
output wire mac_rx_clk_18, // Av-ST Receive Clock
|
| 903 |
|
|
output wire mac_tx_clk_18, // Av-ST Transmit Clock
|
| 904 |
|
|
output wire data_rx_sop_18, // Start of Packet
|
| 905 |
|
|
output wire data_rx_eop_18, // End of Packet
|
| 906 |
|
|
output wire [7:0] data_rx_data_18, // Data from FIFO
|
| 907 |
|
|
output wire [4:0] data_rx_error_18, // Receive packet error
|
| 908 |
|
|
output wire data_rx_valid_18, // Data Receive FIFO Valid
|
| 909 |
|
|
input wire data_rx_ready_18, // Data Receive Ready
|
| 910 |
|
|
output wire [4:0] pkt_class_data_18, // Frame Type Indication
|
| 911 |
|
|
output wire pkt_class_valid_18, // Frame Type Indication Valid
|
| 912 |
|
|
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
|
| 913 |
|
|
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
|
| 914 |
|
|
input wire data_tx_valid_18, // Data FIFO transmit Empty
|
| 915 |
|
|
input wire data_tx_sop_18, // Start of Packet
|
| 916 |
|
|
input wire data_tx_eop_18, // END of Packet
|
| 917 |
|
|
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
|
| 918 |
|
|
|
| 919 |
|
|
// STAND_ALONE CONDUITS
|
| 920 |
|
|
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 921 |
|
|
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
|
| 922 |
|
|
input wire xoff_gen_18, // Xoff Pause frame generate
|
| 923 |
|
|
input wire xon_gen_18, // Xon Pause frame generate
|
| 924 |
|
|
input wire magic_sleep_n_18, // Enable Sleep Mode
|
| 925 |
|
|
output wire magic_wakeup_18, // Wake Up Request
|
| 926 |
|
|
|
| 927 |
|
|
|
| 928 |
|
|
// CHANNEL 19
|
| 929 |
|
|
|
| 930 |
|
|
// PCS SIGNALS TO PHY
|
| 931 |
|
|
input wire tbi_rx_clk_19, // 125MHz Recoved Clock
|
| 932 |
|
|
input wire tbi_tx_clk_19, // 125MHz Transmit Clock
|
| 933 |
|
|
input wire [9:0] tbi_rx_d_19, // Non Aligned 10-Bit Characters
|
| 934 |
|
|
output wire [9:0] tbi_tx_d_19, // Transmit TBI Interface
|
| 935 |
|
|
output wire sd_loopback_19, // SERDES Loopback Enable
|
| 936 |
|
|
output wire powerdown_19, // Powerdown Enable
|
| 937 |
|
|
output wire led_crs_19, // Carrier Sense
|
| 938 |
|
|
output wire led_link_19, // Valid Link
|
| 939 |
|
|
output wire led_col_19, // Collision Indication
|
| 940 |
|
|
output wire led_an_19, // Auto-Negotiation Status
|
| 941 |
|
|
output wire led_char_err_19, // Character Error
|
| 942 |
|
|
output wire led_disp_err_19, // Disparity Error
|
| 943 |
|
|
|
| 944 |
|
|
// AV-ST TX & RX
|
| 945 |
|
|
output wire mac_rx_clk_19, // Av-ST Receive Clock
|
| 946 |
|
|
output wire mac_tx_clk_19, // Av-ST Transmit Clock
|
| 947 |
|
|
output wire data_rx_sop_19, // Start of Packet
|
| 948 |
|
|
output wire data_rx_eop_19, // End of Packet
|
| 949 |
|
|
output wire [7:0] data_rx_data_19, // Data from FIFO
|
| 950 |
|
|
output wire [4:0] data_rx_error_19, // Receive packet error
|
| 951 |
|
|
output wire data_rx_valid_19, // Data Receive FIFO Valid
|
| 952 |
|
|
input wire data_rx_ready_19, // Data Receive Ready
|
| 953 |
|
|
output wire [4:0] pkt_class_data_19, // Frame Type Indication
|
| 954 |
|
|
output wire pkt_class_valid_19, // Frame Type Indication Valid
|
| 955 |
|
|
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
|
| 956 |
|
|
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
|
| 957 |
|
|
input wire data_tx_valid_19, // Data FIFO transmit Empty
|
| 958 |
|
|
input wire data_tx_sop_19, // Start of Packet
|
| 959 |
|
|
input wire data_tx_eop_19, // END of Packet
|
| 960 |
|
|
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
|
| 961 |
|
|
|
| 962 |
|
|
// STAND_ALONE CONDUITS
|
| 963 |
|
|
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 964 |
|
|
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
|
| 965 |
|
|
input wire xoff_gen_19, // Xoff Pause frame generate
|
| 966 |
|
|
input wire xon_gen_19, // Xon Pause frame generate
|
| 967 |
|
|
input wire magic_sleep_n_19, // Enable Sleep Mode
|
| 968 |
|
|
output wire magic_wakeup_19, // Wake Up Request
|
| 969 |
|
|
|
| 970 |
|
|
|
| 971 |
|
|
// CHANNEL 20
|
| 972 |
|
|
|
| 973 |
|
|
// PCS SIGNALS TO PHY
|
| 974 |
|
|
input wire tbi_rx_clk_20, // 125MHz Recoved Clock
|
| 975 |
|
|
input wire tbi_tx_clk_20, // 125MHz Transmit Clock
|
| 976 |
|
|
input wire [9:0] tbi_rx_d_20, // Non Aligned 10-Bit Characters
|
| 977 |
|
|
output wire [9:0] tbi_tx_d_20, // Transmit TBI Interface
|
| 978 |
|
|
output wire sd_loopback_20, // SERDES Loopback Enable
|
| 979 |
|
|
output wire powerdown_20, // Powerdown Enable
|
| 980 |
|
|
output wire led_crs_20, // Carrier Sense
|
| 981 |
|
|
output wire led_link_20, // Valid Link
|
| 982 |
|
|
output wire led_col_20, // Collision Indication
|
| 983 |
|
|
output wire led_an_20, // Auto-Negotiation Status
|
| 984 |
|
|
output wire led_char_err_20, // Character Error
|
| 985 |
|
|
output wire led_disp_err_20, // Disparity Error
|
| 986 |
|
|
|
| 987 |
|
|
// AV-ST TX & RX
|
| 988 |
|
|
output wire mac_rx_clk_20, // Av-ST Receive Clock
|
| 989 |
|
|
output wire mac_tx_clk_20, // Av-ST Transmit Clock
|
| 990 |
|
|
output wire data_rx_sop_20, // Start of Packet
|
| 991 |
|
|
output wire data_rx_eop_20, // End of Packet
|
| 992 |
|
|
output wire [7:0] data_rx_data_20, // Data from FIFO
|
| 993 |
|
|
output wire [4:0] data_rx_error_20, // Receive packet error
|
| 994 |
|
|
output wire data_rx_valid_20, // Data Receive FIFO Valid
|
| 995 |
|
|
input wire data_rx_ready_20, // Data Receive Ready
|
| 996 |
|
|
output wire [4:0] pkt_class_data_20, // Frame Type Indication
|
| 997 |
|
|
output wire pkt_class_valid_20, // Frame Type Indication Valid
|
| 998 |
|
|
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
|
| 999 |
|
|
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
|
| 1000 |
|
|
input wire data_tx_valid_20, // Data FIFO transmit Empty
|
| 1001 |
|
|
input wire data_tx_sop_20, // Start of Packet
|
| 1002 |
|
|
input wire data_tx_eop_20, // END of Packet
|
| 1003 |
|
|
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
|
| 1004 |
|
|
|
| 1005 |
|
|
// STAND_ALONE CONDUITS
|
| 1006 |
|
|
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1007 |
|
|
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
|
| 1008 |
|
|
input wire xoff_gen_20, // Xoff Pause frame generate
|
| 1009 |
|
|
input wire xon_gen_20, // Xon Pause frame generate
|
| 1010 |
|
|
input wire magic_sleep_n_20, // Enable Sleep Mode
|
| 1011 |
|
|
output wire magic_wakeup_20, // Wake Up Request
|
| 1012 |
|
|
|
| 1013 |
|
|
|
| 1014 |
|
|
// CHANNEL 21
|
| 1015 |
|
|
|
| 1016 |
|
|
// PCS SIGNALS TO PHY
|
| 1017 |
|
|
input wire tbi_rx_clk_21, // 125MHz Recoved Clock
|
| 1018 |
|
|
input wire tbi_tx_clk_21, // 125MHz Transmit Clock
|
| 1019 |
|
|
input wire [9:0] tbi_rx_d_21, // Non Aligned 10-Bit Characters
|
| 1020 |
|
|
output wire [9:0] tbi_tx_d_21, // Transmit TBI Interface
|
| 1021 |
|
|
output wire sd_loopback_21, // SERDES Loopback Enable
|
| 1022 |
|
|
output wire powerdown_21, // Powerdown Enable
|
| 1023 |
|
|
output wire led_crs_21, // Carrier Sense
|
| 1024 |
|
|
output wire led_link_21, // Valid Link
|
| 1025 |
|
|
output wire led_col_21, // Collision Indication
|
| 1026 |
|
|
output wire led_an_21, // Auto-Negotiation Status
|
| 1027 |
|
|
output wire led_char_err_21, // Character Error
|
| 1028 |
|
|
output wire led_disp_err_21, // Disparity Error
|
| 1029 |
|
|
|
| 1030 |
|
|
// AV-ST TX & RX
|
| 1031 |
|
|
output wire mac_rx_clk_21, // Av-ST Receive Clock
|
| 1032 |
|
|
output wire mac_tx_clk_21, // Av-ST Transmit Clock
|
| 1033 |
|
|
output wire data_rx_sop_21, // Start of Packet
|
| 1034 |
|
|
output wire data_rx_eop_21, // End of Packet
|
| 1035 |
|
|
output wire [7:0] data_rx_data_21, // Data from FIFO
|
| 1036 |
|
|
output wire [4:0] data_rx_error_21, // Receive packet error
|
| 1037 |
|
|
output wire data_rx_valid_21, // Data Receive FIFO Valid
|
| 1038 |
|
|
input wire data_rx_ready_21, // Data Receive Ready
|
| 1039 |
|
|
output wire [4:0] pkt_class_data_21, // Frame Type Indication
|
| 1040 |
|
|
output wire pkt_class_valid_21, // Frame Type Indication Valid
|
| 1041 |
|
|
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
|
| 1042 |
|
|
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
|
| 1043 |
|
|
input wire data_tx_valid_21, // Data FIFO transmit Empty
|
| 1044 |
|
|
input wire data_tx_sop_21, // Start of Packet
|
| 1045 |
|
|
input wire data_tx_eop_21, // END of Packet
|
| 1046 |
|
|
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
|
| 1047 |
|
|
|
| 1048 |
|
|
// STAND_ALONE CONDUITS
|
| 1049 |
|
|
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1050 |
|
|
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
|
| 1051 |
|
|
input wire xoff_gen_21, // Xoff Pause frame generate
|
| 1052 |
|
|
input wire xon_gen_21, // Xon Pause frame generate
|
| 1053 |
|
|
input wire magic_sleep_n_21, // Enable Sleep Mode
|
| 1054 |
|
|
output wire magic_wakeup_21, // Wake Up Request
|
| 1055 |
|
|
|
| 1056 |
|
|
|
| 1057 |
|
|
// CHANNEL 22
|
| 1058 |
|
|
|
| 1059 |
|
|
// PCS SIGNALS TO PHY
|
| 1060 |
|
|
input wire tbi_rx_clk_22, // 125MHz Recoved Clock
|
| 1061 |
|
|
input wire tbi_tx_clk_22, // 125MHz Transmit Clock
|
| 1062 |
|
|
input wire [9:0] tbi_rx_d_22, // Non Aligned 10-Bit Characters
|
| 1063 |
|
|
output wire [9:0] tbi_tx_d_22, // Transmit TBI Interface
|
| 1064 |
|
|
output wire sd_loopback_22, // SERDES Loopback Enable
|
| 1065 |
|
|
output wire powerdown_22, // Powerdown Enable
|
| 1066 |
|
|
output wire led_crs_22, // Carrier Sense
|
| 1067 |
|
|
output wire led_link_22, // Valid Link
|
| 1068 |
|
|
output wire led_col_22, // Collision Indication
|
| 1069 |
|
|
output wire led_an_22, // Auto-Negotiation Status
|
| 1070 |
|
|
output wire led_char_err_22, // Character Error
|
| 1071 |
|
|
output wire led_disp_err_22, // Disparity Error
|
| 1072 |
|
|
|
| 1073 |
|
|
// AV-ST TX & RX
|
| 1074 |
|
|
output wire mac_rx_clk_22, // Av-ST Receive Clock
|
| 1075 |
|
|
output wire mac_tx_clk_22, // Av-ST Transmit Clock
|
| 1076 |
|
|
output wire data_rx_sop_22, // Start of Packet
|
| 1077 |
|
|
output wire data_rx_eop_22, // End of Packet
|
| 1078 |
|
|
output wire [7:0] data_rx_data_22, // Data from FIFO
|
| 1079 |
|
|
output wire [4:0] data_rx_error_22, // Receive packet error
|
| 1080 |
|
|
output wire data_rx_valid_22, // Data Receive FIFO Valid
|
| 1081 |
|
|
input wire data_rx_ready_22, // Data Receive Ready
|
| 1082 |
|
|
output wire [4:0] pkt_class_data_22, // Frame Type Indication
|
| 1083 |
|
|
output wire pkt_class_valid_22, // Frame Type Indication Valid
|
| 1084 |
|
|
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
|
| 1085 |
|
|
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
|
| 1086 |
|
|
input wire data_tx_valid_22, // Data FIFO transmit Empty
|
| 1087 |
|
|
input wire data_tx_sop_22, // Start of Packet
|
| 1088 |
|
|
input wire data_tx_eop_22, // END of Packet
|
| 1089 |
|
|
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
|
| 1090 |
|
|
|
| 1091 |
|
|
// STAND_ALONE CONDUITS
|
| 1092 |
|
|
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1093 |
|
|
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
|
| 1094 |
|
|
input wire xoff_gen_22, // Xoff Pause frame generate
|
| 1095 |
|
|
input wire xon_gen_22, // Xon Pause frame generate
|
| 1096 |
|
|
input wire magic_sleep_n_22, // Enable Sleep Mode
|
| 1097 |
|
|
output wire magic_wakeup_22, // Wake Up Request
|
| 1098 |
|
|
|
| 1099 |
|
|
|
| 1100 |
|
|
// CHANNEL 23
|
| 1101 |
|
|
|
| 1102 |
|
|
// PCS SIGNALS TO PHY
|
| 1103 |
|
|
input wire tbi_rx_clk_23, // 125MHz Recoved Clock
|
| 1104 |
|
|
input wire tbi_tx_clk_23, // 125MHz Transmit Clock
|
| 1105 |
|
|
input wire [9:0] tbi_rx_d_23, // Non Aligned 10-Bit Characters
|
| 1106 |
|
|
output wire [9:0] tbi_tx_d_23, // Transmit TBI Interface
|
| 1107 |
|
|
output wire sd_loopback_23, // SERDES Loopback Enable
|
| 1108 |
|
|
output wire powerdown_23, // Powerdown Enable
|
| 1109 |
|
|
output wire led_crs_23, // Carrier Sense
|
| 1110 |
|
|
output wire led_link_23, // Valid Link
|
| 1111 |
|
|
output wire led_col_23, // Collision Indication
|
| 1112 |
|
|
output wire led_an_23, // Auto-Negotiation Status
|
| 1113 |
|
|
output wire led_char_err_23, // Character Error
|
| 1114 |
|
|
output wire led_disp_err_23, // Disparity Error
|
| 1115 |
|
|
|
| 1116 |
|
|
// AV-ST TX & RX
|
| 1117 |
|
|
output wire mac_rx_clk_23, // Av-ST Receive Clock
|
| 1118 |
|
|
output wire mac_tx_clk_23, // Av-ST Transmit Clock
|
| 1119 |
|
|
output wire data_rx_sop_23, // Start of Packet
|
| 1120 |
|
|
output wire data_rx_eop_23, // End of Packet
|
| 1121 |
|
|
output wire [7:0] data_rx_data_23, // Data from FIFO
|
| 1122 |
|
|
output wire [4:0] data_rx_error_23, // Receive packet error
|
| 1123 |
|
|
output wire data_rx_valid_23, // Data Receive FIFO Valid
|
| 1124 |
|
|
input wire data_rx_ready_23, // Data Receive Ready
|
| 1125 |
|
|
output wire [4:0] pkt_class_data_23, // Frame Type Indication
|
| 1126 |
|
|
output wire pkt_class_valid_23, // Frame Type Indication Valid
|
| 1127 |
|
|
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
|
| 1128 |
|
|
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
|
| 1129 |
|
|
input wire data_tx_valid_23, // Data FIFO transmit Empty
|
| 1130 |
|
|
input wire data_tx_sop_23, // Start of Packet
|
| 1131 |
|
|
input wire data_tx_eop_23, // END of Packet
|
| 1132 |
|
|
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
|
| 1133 |
|
|
|
| 1134 |
|
|
// STAND_ALONE CONDUITS
|
| 1135 |
|
|
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1136 |
|
|
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
|
| 1137 |
|
|
input wire xoff_gen_23, // Xoff Pause frame generate
|
| 1138 |
|
|
input wire xon_gen_23, // Xon Pause frame generate
|
| 1139 |
|
|
input wire magic_sleep_n_23, // Enable Sleep Mode
|
| 1140 |
|
|
output wire magic_wakeup_23); // Wake Up Request
|
| 1141 |
|
|
|
| 1142 |
|
|
|
| 1143 |
|
|
// Component instantiation
|
| 1144 |
|
|
|
| 1145 |
|
|
altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
|
| 1146 |
|
|
|
| 1147 |
|
|
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
|
| 1148 |
|
|
.clk(clk), //INPUT : CLOCK
|
| 1149 |
|
|
.read(read), //INPUT : REGISTER READ TRANSACTION
|
| 1150 |
|
|
.write(write), //INPUT : REGISTER WRITE TRANSACTION
|
| 1151 |
|
|
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
|
| 1152 |
|
|
.address(address), //INPUT : REGISTER ADDRESS
|
| 1153 |
|
|
.writedata(writedata), //INPUT : REGISTER WRITE DATA
|
| 1154 |
|
|
.readdata(readdata), //OUTPUT : REGISTER READ DATA
|
| 1155 |
|
|
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
|
| 1156 |
|
|
.mdc(mdc), //OUTPUT : MDIO Clock
|
| 1157 |
|
|
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
|
| 1158 |
|
|
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
|
| 1159 |
|
|
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
|
| 1160 |
|
|
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
|
| 1161 |
|
|
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
|
| 1162 |
|
|
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
|
| 1163 |
|
|
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
|
| 1164 |
|
|
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
|
| 1165 |
|
|
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
|
| 1166 |
|
|
|
| 1167 |
|
|
// Channel 0
|
| 1168 |
|
|
|
| 1169 |
|
|
.tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
|
| 1170 |
|
|
.tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
|
| 1171 |
|
|
.tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
|
| 1172 |
|
|
.tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
|
| 1173 |
|
|
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
|
| 1174 |
|
|
.powerdown_0(powerdown_0), //OUTPUT : Powerdown Enable
|
| 1175 |
|
|
.led_col_0(led_col_0), //OUTPUT : Collision Indication
|
| 1176 |
|
|
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
|
| 1177 |
|
|
.led_char_err_0(led_char_err_0), //OUTPUT : Character error
|
| 1178 |
|
|
.led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
|
| 1179 |
|
|
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
|
| 1180 |
|
|
.led_link_0(led_link_0), //OUTPUT : Valid link
|
| 1181 |
|
|
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
|
| 1182 |
|
|
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
|
| 1183 |
|
|
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
|
| 1184 |
|
|
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
|
| 1185 |
|
|
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
|
| 1186 |
|
|
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
|
| 1187 |
|
|
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
|
| 1188 |
|
|
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
|
| 1189 |
|
|
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
|
| 1190 |
|
|
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
|
| 1191 |
|
|
.data_tx_error_0(data_tx_error_0), //INPUT : Status
|
| 1192 |
|
|
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
|
| 1193 |
|
|
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
|
| 1194 |
|
|
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
|
| 1195 |
|
|
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
|
| 1196 |
|
|
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
|
| 1197 |
|
|
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1198 |
|
|
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
|
| 1199 |
|
|
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1200 |
|
|
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
|
| 1201 |
|
|
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
|
| 1202 |
|
|
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1203 |
|
|
|
| 1204 |
|
|
// Channel 1
|
| 1205 |
|
|
|
| 1206 |
|
|
.tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
|
| 1207 |
|
|
.tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
|
| 1208 |
|
|
.tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
|
| 1209 |
|
|
.tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
|
| 1210 |
|
|
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
|
| 1211 |
|
|
.powerdown_1(powerdown_1), //OUTPUT : Powerdown Enable
|
| 1212 |
|
|
.led_col_1(led_col_1), //OUTPUT : Collision Indication
|
| 1213 |
|
|
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
|
| 1214 |
|
|
.led_char_err_1(led_char_err_1), //OUTPUT : Character error
|
| 1215 |
|
|
.led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
|
| 1216 |
|
|
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
|
| 1217 |
|
|
.led_link_1(led_link_1), //OUTPUT : Valid link
|
| 1218 |
|
|
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
|
| 1219 |
|
|
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
|
| 1220 |
|
|
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
|
| 1221 |
|
|
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
|
| 1222 |
|
|
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
|
| 1223 |
|
|
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
|
| 1224 |
|
|
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
|
| 1225 |
|
|
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
|
| 1226 |
|
|
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
|
| 1227 |
|
|
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
|
| 1228 |
|
|
.data_tx_error_1(data_tx_error_1), //INPUT : Status
|
| 1229 |
|
|
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
|
| 1230 |
|
|
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
|
| 1231 |
|
|
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
|
| 1232 |
|
|
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
|
| 1233 |
|
|
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
|
| 1234 |
|
|
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1235 |
|
|
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
|
| 1236 |
|
|
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1237 |
|
|
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
|
| 1238 |
|
|
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
|
| 1239 |
|
|
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1240 |
|
|
|
| 1241 |
|
|
// Channel 2
|
| 1242 |
|
|
|
| 1243 |
|
|
.tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
|
| 1244 |
|
|
.tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
|
| 1245 |
|
|
.tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
|
| 1246 |
|
|
.tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
|
| 1247 |
|
|
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
|
| 1248 |
|
|
.powerdown_2(powerdown_2), //OUTPUT : Powerdown Enable
|
| 1249 |
|
|
.led_col_2(led_col_2), //OUTPUT : Collision Indication
|
| 1250 |
|
|
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
|
| 1251 |
|
|
.led_char_err_2(led_char_err_2), //OUTPUT : Character error
|
| 1252 |
|
|
.led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
|
| 1253 |
|
|
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
|
| 1254 |
|
|
.led_link_2(led_link_2), //OUTPUT : Valid link
|
| 1255 |
|
|
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
|
| 1256 |
|
|
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
|
| 1257 |
|
|
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
|
| 1258 |
|
|
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
|
| 1259 |
|
|
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
|
| 1260 |
|
|
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
|
| 1261 |
|
|
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
|
| 1262 |
|
|
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
|
| 1263 |
|
|
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
|
| 1264 |
|
|
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
|
| 1265 |
|
|
.data_tx_error_2(data_tx_error_2), //INPUT : Status
|
| 1266 |
|
|
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
|
| 1267 |
|
|
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
|
| 1268 |
|
|
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
|
| 1269 |
|
|
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
|
| 1270 |
|
|
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
|
| 1271 |
|
|
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1272 |
|
|
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
|
| 1273 |
|
|
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1274 |
|
|
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
|
| 1275 |
|
|
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
|
| 1276 |
|
|
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1277 |
|
|
|
| 1278 |
|
|
// Channel 3
|
| 1279 |
|
|
|
| 1280 |
|
|
.tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
|
| 1281 |
|
|
.tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
|
| 1282 |
|
|
.tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
|
| 1283 |
|
|
.tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
|
| 1284 |
|
|
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
|
| 1285 |
|
|
.powerdown_3(powerdown_3), //OUTPUT : Powerdown Enable
|
| 1286 |
|
|
.led_col_3(led_col_3), //OUTPUT : Collision Indication
|
| 1287 |
|
|
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
|
| 1288 |
|
|
.led_char_err_3(led_char_err_3), //OUTPUT : Character error
|
| 1289 |
|
|
.led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
|
| 1290 |
|
|
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
|
| 1291 |
|
|
.led_link_3(led_link_3), //OUTPUT : Valid link
|
| 1292 |
|
|
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
|
| 1293 |
|
|
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
|
| 1294 |
|
|
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
|
| 1295 |
|
|
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
|
| 1296 |
|
|
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
|
| 1297 |
|
|
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
|
| 1298 |
|
|
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
|
| 1299 |
|
|
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
|
| 1300 |
|
|
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
|
| 1301 |
|
|
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
|
| 1302 |
|
|
.data_tx_error_3(data_tx_error_3), //INPUT : Status
|
| 1303 |
|
|
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
|
| 1304 |
|
|
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
|
| 1305 |
|
|
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
|
| 1306 |
|
|
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
|
| 1307 |
|
|
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
|
| 1308 |
|
|
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1309 |
|
|
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
|
| 1310 |
|
|
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1311 |
|
|
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
|
| 1312 |
|
|
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
|
| 1313 |
|
|
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1314 |
|
|
|
| 1315 |
|
|
// Channel 4
|
| 1316 |
|
|
|
| 1317 |
|
|
.tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
|
| 1318 |
|
|
.tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
|
| 1319 |
|
|
.tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
|
| 1320 |
|
|
.tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
|
| 1321 |
|
|
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
|
| 1322 |
|
|
.powerdown_4(powerdown_4), //OUTPUT : Powerdown Enable
|
| 1323 |
|
|
.led_col_4(led_col_4), //OUTPUT : Collision Indication
|
| 1324 |
|
|
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
|
| 1325 |
|
|
.led_char_err_4(led_char_err_4), //OUTPUT : Character error
|
| 1326 |
|
|
.led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
|
| 1327 |
|
|
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
|
| 1328 |
|
|
.led_link_4(led_link_4), //OUTPUT : Valid link
|
| 1329 |
|
|
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
|
| 1330 |
|
|
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
|
| 1331 |
|
|
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
|
| 1332 |
|
|
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
|
| 1333 |
|
|
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
|
| 1334 |
|
|
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
|
| 1335 |
|
|
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
|
| 1336 |
|
|
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
|
| 1337 |
|
|
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
|
| 1338 |
|
|
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
|
| 1339 |
|
|
.data_tx_error_4(data_tx_error_4), //INPUT : Status
|
| 1340 |
|
|
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
|
| 1341 |
|
|
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
|
| 1342 |
|
|
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
|
| 1343 |
|
|
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
|
| 1344 |
|
|
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
|
| 1345 |
|
|
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1346 |
|
|
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
|
| 1347 |
|
|
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1348 |
|
|
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
|
| 1349 |
|
|
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
|
| 1350 |
|
|
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1351 |
|
|
|
| 1352 |
|
|
// Channel 5
|
| 1353 |
|
|
|
| 1354 |
|
|
.tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
|
| 1355 |
|
|
.tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
|
| 1356 |
|
|
.tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
|
| 1357 |
|
|
.tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
|
| 1358 |
|
|
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
|
| 1359 |
|
|
.powerdown_5(powerdown_5), //OUTPUT : Powerdown Enable
|
| 1360 |
|
|
.led_col_5(led_col_5), //OUTPUT : Collision Indication
|
| 1361 |
|
|
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
|
| 1362 |
|
|
.led_char_err_5(led_char_err_5), //OUTPUT : Character error
|
| 1363 |
|
|
.led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
|
| 1364 |
|
|
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
|
| 1365 |
|
|
.led_link_5(led_link_5), //OUTPUT : Valid link
|
| 1366 |
|
|
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
|
| 1367 |
|
|
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
|
| 1368 |
|
|
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
|
| 1369 |
|
|
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
|
| 1370 |
|
|
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
|
| 1371 |
|
|
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
|
| 1372 |
|
|
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
|
| 1373 |
|
|
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
|
| 1374 |
|
|
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
|
| 1375 |
|
|
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
|
| 1376 |
|
|
.data_tx_error_5(data_tx_error_5), //INPUT : Status
|
| 1377 |
|
|
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
|
| 1378 |
|
|
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
|
| 1379 |
|
|
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
|
| 1380 |
|
|
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
|
| 1381 |
|
|
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
|
| 1382 |
|
|
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1383 |
|
|
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
|
| 1384 |
|
|
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1385 |
|
|
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
|
| 1386 |
|
|
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
|
| 1387 |
|
|
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1388 |
|
|
|
| 1389 |
|
|
// Channel 6
|
| 1390 |
|
|
|
| 1391 |
|
|
.tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
|
| 1392 |
|
|
.tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
|
| 1393 |
|
|
.tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
|
| 1394 |
|
|
.tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
|
| 1395 |
|
|
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
|
| 1396 |
|
|
.powerdown_6(powerdown_6), //OUTPUT : Powerdown Enable
|
| 1397 |
|
|
.led_col_6(led_col_6), //OUTPUT : Collision Indication
|
| 1398 |
|
|
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
|
| 1399 |
|
|
.led_char_err_6(led_char_err_6), //OUTPUT : Character error
|
| 1400 |
|
|
.led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
|
| 1401 |
|
|
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
|
| 1402 |
|
|
.led_link_6(led_link_6), //OUTPUT : Valid link
|
| 1403 |
|
|
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
|
| 1404 |
|
|
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
|
| 1405 |
|
|
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
|
| 1406 |
|
|
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
|
| 1407 |
|
|
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
|
| 1408 |
|
|
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
|
| 1409 |
|
|
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
|
| 1410 |
|
|
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
|
| 1411 |
|
|
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
|
| 1412 |
|
|
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
|
| 1413 |
|
|
.data_tx_error_6(data_tx_error_6), //INPUT : Status
|
| 1414 |
|
|
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
|
| 1415 |
|
|
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
|
| 1416 |
|
|
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
|
| 1417 |
|
|
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
|
| 1418 |
|
|
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
|
| 1419 |
|
|
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1420 |
|
|
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
|
| 1421 |
|
|
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1422 |
|
|
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
|
| 1423 |
|
|
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
|
| 1424 |
|
|
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1425 |
|
|
|
| 1426 |
|
|
// Channel 7
|
| 1427 |
|
|
|
| 1428 |
|
|
.tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
|
| 1429 |
|
|
.tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
|
| 1430 |
|
|
.tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
|
| 1431 |
|
|
.tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
|
| 1432 |
|
|
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
|
| 1433 |
|
|
.powerdown_7(powerdown_7), //OUTPUT : Powerdown Enable
|
| 1434 |
|
|
.led_col_7(led_col_7), //OUTPUT : Collision Indication
|
| 1435 |
|
|
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
|
| 1436 |
|
|
.led_char_err_7(led_char_err_7), //OUTPUT : Character error
|
| 1437 |
|
|
.led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
|
| 1438 |
|
|
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
|
| 1439 |
|
|
.led_link_7(led_link_7), //OUTPUT : Valid link
|
| 1440 |
|
|
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
|
| 1441 |
|
|
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
|
| 1442 |
|
|
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
|
| 1443 |
|
|
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
|
| 1444 |
|
|
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
|
| 1445 |
|
|
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
|
| 1446 |
|
|
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
|
| 1447 |
|
|
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
|
| 1448 |
|
|
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
|
| 1449 |
|
|
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
|
| 1450 |
|
|
.data_tx_error_7(data_tx_error_7), //INPUT : Status
|
| 1451 |
|
|
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
|
| 1452 |
|
|
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
|
| 1453 |
|
|
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
|
| 1454 |
|
|
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
|
| 1455 |
|
|
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
|
| 1456 |
|
|
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1457 |
|
|
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
|
| 1458 |
|
|
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1459 |
|
|
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
|
| 1460 |
|
|
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
|
| 1461 |
|
|
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1462 |
|
|
|
| 1463 |
|
|
// Channel 8
|
| 1464 |
|
|
|
| 1465 |
|
|
.tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
|
| 1466 |
|
|
.tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
|
| 1467 |
|
|
.tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
|
| 1468 |
|
|
.tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
|
| 1469 |
|
|
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
|
| 1470 |
|
|
.powerdown_8(powerdown_8), //OUTPUT : Powerdown Enable
|
| 1471 |
|
|
.led_col_8(led_col_8), //OUTPUT : Collision Indication
|
| 1472 |
|
|
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
|
| 1473 |
|
|
.led_char_err_8(led_char_err_8), //OUTPUT : Character error
|
| 1474 |
|
|
.led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
|
| 1475 |
|
|
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
|
| 1476 |
|
|
.led_link_8(led_link_8), //OUTPUT : Valid link
|
| 1477 |
|
|
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
|
| 1478 |
|
|
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
|
| 1479 |
|
|
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
|
| 1480 |
|
|
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
|
| 1481 |
|
|
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
|
| 1482 |
|
|
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
|
| 1483 |
|
|
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
|
| 1484 |
|
|
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
|
| 1485 |
|
|
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
|
| 1486 |
|
|
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
|
| 1487 |
|
|
.data_tx_error_8(data_tx_error_8), //INPUT : Status
|
| 1488 |
|
|
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
|
| 1489 |
|
|
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
|
| 1490 |
|
|
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
|
| 1491 |
|
|
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
|
| 1492 |
|
|
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
|
| 1493 |
|
|
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1494 |
|
|
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
|
| 1495 |
|
|
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1496 |
|
|
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
|
| 1497 |
|
|
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
|
| 1498 |
|
|
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1499 |
|
|
|
| 1500 |
|
|
// Channel 9
|
| 1501 |
|
|
|
| 1502 |
|
|
.tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
|
| 1503 |
|
|
.tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
|
| 1504 |
|
|
.tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
|
| 1505 |
|
|
.tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
|
| 1506 |
|
|
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
|
| 1507 |
|
|
.powerdown_9(powerdown_9), //OUTPUT : Powerdown Enable
|
| 1508 |
|
|
.led_col_9(led_col_9), //OUTPUT : Collision Indication
|
| 1509 |
|
|
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
|
| 1510 |
|
|
.led_char_err_9(led_char_err_9), //OUTPUT : Character error
|
| 1511 |
|
|
.led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
|
| 1512 |
|
|
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
|
| 1513 |
|
|
.led_link_9(led_link_9), //OUTPUT : Valid link
|
| 1514 |
|
|
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
|
| 1515 |
|
|
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
|
| 1516 |
|
|
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
|
| 1517 |
|
|
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
|
| 1518 |
|
|
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
|
| 1519 |
|
|
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
|
| 1520 |
|
|
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
|
| 1521 |
|
|
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
|
| 1522 |
|
|
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
|
| 1523 |
|
|
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
|
| 1524 |
|
|
.data_tx_error_9(data_tx_error_9), //INPUT : Status
|
| 1525 |
|
|
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
|
| 1526 |
|
|
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
|
| 1527 |
|
|
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
|
| 1528 |
|
|
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
|
| 1529 |
|
|
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
|
| 1530 |
|
|
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1531 |
|
|
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
|
| 1532 |
|
|
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1533 |
|
|
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
|
| 1534 |
|
|
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
|
| 1535 |
|
|
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1536 |
|
|
|
| 1537 |
|
|
// Channel 10
|
| 1538 |
|
|
|
| 1539 |
|
|
.tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
|
| 1540 |
|
|
.tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
|
| 1541 |
|
|
.tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
|
| 1542 |
|
|
.tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
|
| 1543 |
|
|
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
|
| 1544 |
|
|
.powerdown_10(powerdown_10), //OUTPUT : Powerdown Enable
|
| 1545 |
|
|
.led_col_10(led_col_10), //OUTPUT : Collision Indication
|
| 1546 |
|
|
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
|
| 1547 |
|
|
.led_char_err_10(led_char_err_10), //OUTPUT : Character error
|
| 1548 |
|
|
.led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
|
| 1549 |
|
|
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
|
| 1550 |
|
|
.led_link_10(led_link_10), //OUTPUT : Valid link
|
| 1551 |
|
|
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
|
| 1552 |
|
|
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
|
| 1553 |
|
|
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
|
| 1554 |
|
|
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
|
| 1555 |
|
|
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
|
| 1556 |
|
|
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
|
| 1557 |
|
|
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
|
| 1558 |
|
|
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
|
| 1559 |
|
|
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
|
| 1560 |
|
|
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
|
| 1561 |
|
|
.data_tx_error_10(data_tx_error_10), //INPUT : Status
|
| 1562 |
|
|
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
|
| 1563 |
|
|
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
|
| 1564 |
|
|
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
|
| 1565 |
|
|
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
|
| 1566 |
|
|
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
|
| 1567 |
|
|
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1568 |
|
|
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
|
| 1569 |
|
|
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1570 |
|
|
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
|
| 1571 |
|
|
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
|
| 1572 |
|
|
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1573 |
|
|
|
| 1574 |
|
|
// Channel 11
|
| 1575 |
|
|
|
| 1576 |
|
|
.tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
|
| 1577 |
|
|
.tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
|
| 1578 |
|
|
.tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
|
| 1579 |
|
|
.tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
|
| 1580 |
|
|
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
|
| 1581 |
|
|
.powerdown_11(powerdown_11), //OUTPUT : Powerdown Enable
|
| 1582 |
|
|
.led_col_11(led_col_11), //OUTPUT : Collision Indication
|
| 1583 |
|
|
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
|
| 1584 |
|
|
.led_char_err_11(led_char_err_11), //OUTPUT : Character error
|
| 1585 |
|
|
.led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
|
| 1586 |
|
|
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
|
| 1587 |
|
|
.led_link_11(led_link_11), //OUTPUT : Valid link
|
| 1588 |
|
|
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
|
| 1589 |
|
|
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
|
| 1590 |
|
|
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
|
| 1591 |
|
|
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
|
| 1592 |
|
|
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
|
| 1593 |
|
|
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
|
| 1594 |
|
|
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
|
| 1595 |
|
|
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
|
| 1596 |
|
|
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
|
| 1597 |
|
|
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
|
| 1598 |
|
|
.data_tx_error_11(data_tx_error_11), //INPUT : Status
|
| 1599 |
|
|
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
|
| 1600 |
|
|
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
|
| 1601 |
|
|
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
|
| 1602 |
|
|
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
|
| 1603 |
|
|
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
|
| 1604 |
|
|
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1605 |
|
|
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
|
| 1606 |
|
|
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1607 |
|
|
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
|
| 1608 |
|
|
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
|
| 1609 |
|
|
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1610 |
|
|
|
| 1611 |
|
|
// Channel 12
|
| 1612 |
|
|
|
| 1613 |
|
|
.tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
|
| 1614 |
|
|
.tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
|
| 1615 |
|
|
.tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
|
| 1616 |
|
|
.tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
|
| 1617 |
|
|
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
|
| 1618 |
|
|
.powerdown_12(powerdown_12), //OUTPUT : Powerdown Enable
|
| 1619 |
|
|
.led_col_12(led_col_12), //OUTPUT : Collision Indication
|
| 1620 |
|
|
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
|
| 1621 |
|
|
.led_char_err_12(led_char_err_12), //OUTPUT : Character error
|
| 1622 |
|
|
.led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
|
| 1623 |
|
|
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
|
| 1624 |
|
|
.led_link_12(led_link_12), //OUTPUT : Valid link
|
| 1625 |
|
|
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
|
| 1626 |
|
|
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
|
| 1627 |
|
|
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
|
| 1628 |
|
|
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
|
| 1629 |
|
|
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
|
| 1630 |
|
|
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
|
| 1631 |
|
|
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
|
| 1632 |
|
|
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
|
| 1633 |
|
|
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
|
| 1634 |
|
|
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
|
| 1635 |
|
|
.data_tx_error_12(data_tx_error_12), //INPUT : Status
|
| 1636 |
|
|
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
|
| 1637 |
|
|
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
|
| 1638 |
|
|
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
|
| 1639 |
|
|
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
|
| 1640 |
|
|
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
|
| 1641 |
|
|
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1642 |
|
|
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
|
| 1643 |
|
|
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1644 |
|
|
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
|
| 1645 |
|
|
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
|
| 1646 |
|
|
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1647 |
|
|
|
| 1648 |
|
|
// Channel 13
|
| 1649 |
|
|
|
| 1650 |
|
|
.tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
|
| 1651 |
|
|
.tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
|
| 1652 |
|
|
.tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
|
| 1653 |
|
|
.tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
|
| 1654 |
|
|
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
|
| 1655 |
|
|
.powerdown_13(powerdown_13), //OUTPUT : Powerdown Enable
|
| 1656 |
|
|
.led_col_13(led_col_13), //OUTPUT : Collision Indication
|
| 1657 |
|
|
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
|
| 1658 |
|
|
.led_char_err_13(led_char_err_13), //OUTPUT : Character error
|
| 1659 |
|
|
.led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
|
| 1660 |
|
|
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
|
| 1661 |
|
|
.led_link_13(led_link_13), //OUTPUT : Valid link
|
| 1662 |
|
|
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
|
| 1663 |
|
|
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
|
| 1664 |
|
|
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
|
| 1665 |
|
|
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
|
| 1666 |
|
|
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
|
| 1667 |
|
|
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
|
| 1668 |
|
|
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
|
| 1669 |
|
|
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
|
| 1670 |
|
|
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
|
| 1671 |
|
|
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
|
| 1672 |
|
|
.data_tx_error_13(data_tx_error_13), //INPUT : Status
|
| 1673 |
|
|
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
|
| 1674 |
|
|
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
|
| 1675 |
|
|
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
|
| 1676 |
|
|
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
|
| 1677 |
|
|
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
|
| 1678 |
|
|
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1679 |
|
|
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
|
| 1680 |
|
|
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1681 |
|
|
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
|
| 1682 |
|
|
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
|
| 1683 |
|
|
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1684 |
|
|
|
| 1685 |
|
|
// Channel 14
|
| 1686 |
|
|
|
| 1687 |
|
|
.tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
|
| 1688 |
|
|
.tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
|
| 1689 |
|
|
.tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
|
| 1690 |
|
|
.tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
|
| 1691 |
|
|
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
|
| 1692 |
|
|
.powerdown_14(powerdown_14), //OUTPUT : Powerdown Enable
|
| 1693 |
|
|
.led_col_14(led_col_14), //OUTPUT : Collision Indication
|
| 1694 |
|
|
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
|
| 1695 |
|
|
.led_char_err_14(led_char_err_14), //OUTPUT : Character error
|
| 1696 |
|
|
.led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
|
| 1697 |
|
|
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
|
| 1698 |
|
|
.led_link_14(led_link_14), //OUTPUT : Valid link
|
| 1699 |
|
|
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
|
| 1700 |
|
|
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
|
| 1701 |
|
|
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
|
| 1702 |
|
|
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
|
| 1703 |
|
|
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
|
| 1704 |
|
|
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
|
| 1705 |
|
|
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
|
| 1706 |
|
|
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
|
| 1707 |
|
|
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
|
| 1708 |
|
|
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
|
| 1709 |
|
|
.data_tx_error_14(data_tx_error_14), //INPUT : Status
|
| 1710 |
|
|
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
|
| 1711 |
|
|
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
|
| 1712 |
|
|
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
|
| 1713 |
|
|
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
|
| 1714 |
|
|
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
|
| 1715 |
|
|
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1716 |
|
|
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
|
| 1717 |
|
|
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1718 |
|
|
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
|
| 1719 |
|
|
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
|
| 1720 |
|
|
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1721 |
|
|
|
| 1722 |
|
|
// Channel 15
|
| 1723 |
|
|
|
| 1724 |
|
|
.tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
|
| 1725 |
|
|
.tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
|
| 1726 |
|
|
.tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
|
| 1727 |
|
|
.tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
|
| 1728 |
|
|
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
|
| 1729 |
|
|
.powerdown_15(powerdown_15), //OUTPUT : Powerdown Enable
|
| 1730 |
|
|
.led_col_15(led_col_15), //OUTPUT : Collision Indication
|
| 1731 |
|
|
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
|
| 1732 |
|
|
.led_char_err_15(led_char_err_15), //OUTPUT : Character error
|
| 1733 |
|
|
.led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
|
| 1734 |
|
|
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
|
| 1735 |
|
|
.led_link_15(led_link_15), //OUTPUT : Valid link
|
| 1736 |
|
|
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
|
| 1737 |
|
|
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
|
| 1738 |
|
|
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
|
| 1739 |
|
|
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
|
| 1740 |
|
|
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
|
| 1741 |
|
|
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
|
| 1742 |
|
|
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
|
| 1743 |
|
|
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
|
| 1744 |
|
|
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
|
| 1745 |
|
|
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
|
| 1746 |
|
|
.data_tx_error_15(data_tx_error_15), //INPUT : Status
|
| 1747 |
|
|
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
|
| 1748 |
|
|
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
|
| 1749 |
|
|
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
|
| 1750 |
|
|
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
|
| 1751 |
|
|
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
|
| 1752 |
|
|
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1753 |
|
|
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
|
| 1754 |
|
|
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1755 |
|
|
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
|
| 1756 |
|
|
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
|
| 1757 |
|
|
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1758 |
|
|
|
| 1759 |
|
|
// Channel 16
|
| 1760 |
|
|
|
| 1761 |
|
|
.tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
|
| 1762 |
|
|
.tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
|
| 1763 |
|
|
.tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
|
| 1764 |
|
|
.tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
|
| 1765 |
|
|
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
|
| 1766 |
|
|
.powerdown_16(powerdown_16), //OUTPUT : Powerdown Enable
|
| 1767 |
|
|
.led_col_16(led_col_16), //OUTPUT : Collision Indication
|
| 1768 |
|
|
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
|
| 1769 |
|
|
.led_char_err_16(led_char_err_16), //OUTPUT : Character error
|
| 1770 |
|
|
.led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
|
| 1771 |
|
|
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
|
| 1772 |
|
|
.led_link_16(led_link_16), //OUTPUT : Valid link
|
| 1773 |
|
|
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
|
| 1774 |
|
|
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
|
| 1775 |
|
|
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
|
| 1776 |
|
|
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
|
| 1777 |
|
|
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
|
| 1778 |
|
|
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
|
| 1779 |
|
|
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
|
| 1780 |
|
|
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
|
| 1781 |
|
|
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
|
| 1782 |
|
|
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
|
| 1783 |
|
|
.data_tx_error_16(data_tx_error_16), //INPUT : Status
|
| 1784 |
|
|
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
|
| 1785 |
|
|
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
|
| 1786 |
|
|
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
|
| 1787 |
|
|
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
|
| 1788 |
|
|
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
|
| 1789 |
|
|
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1790 |
|
|
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
|
| 1791 |
|
|
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1792 |
|
|
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
|
| 1793 |
|
|
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
|
| 1794 |
|
|
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1795 |
|
|
|
| 1796 |
|
|
// Channel 17
|
| 1797 |
|
|
|
| 1798 |
|
|
.tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
|
| 1799 |
|
|
.tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
|
| 1800 |
|
|
.tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
|
| 1801 |
|
|
.tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
|
| 1802 |
|
|
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
|
| 1803 |
|
|
.powerdown_17(powerdown_17), //OUTPUT : Powerdown Enable
|
| 1804 |
|
|
.led_col_17(led_col_17), //OUTPUT : Collision Indication
|
| 1805 |
|
|
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
|
| 1806 |
|
|
.led_char_err_17(led_char_err_17), //OUTPUT : Character error
|
| 1807 |
|
|
.led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
|
| 1808 |
|
|
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
|
| 1809 |
|
|
.led_link_17(led_link_17), //OUTPUT : Valid link
|
| 1810 |
|
|
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
|
| 1811 |
|
|
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
|
| 1812 |
|
|
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
|
| 1813 |
|
|
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
|
| 1814 |
|
|
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
|
| 1815 |
|
|
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
|
| 1816 |
|
|
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
|
| 1817 |
|
|
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
|
| 1818 |
|
|
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
|
| 1819 |
|
|
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
|
| 1820 |
|
|
.data_tx_error_17(data_tx_error_17), //INPUT : Status
|
| 1821 |
|
|
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
|
| 1822 |
|
|
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
|
| 1823 |
|
|
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
|
| 1824 |
|
|
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
|
| 1825 |
|
|
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
|
| 1826 |
|
|
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1827 |
|
|
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
|
| 1828 |
|
|
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1829 |
|
|
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
|
| 1830 |
|
|
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
|
| 1831 |
|
|
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1832 |
|
|
|
| 1833 |
|
|
// Channel 18
|
| 1834 |
|
|
|
| 1835 |
|
|
.tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
|
| 1836 |
|
|
.tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
|
| 1837 |
|
|
.tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
|
| 1838 |
|
|
.tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
|
| 1839 |
|
|
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
|
| 1840 |
|
|
.powerdown_18(powerdown_18), //OUTPUT : Powerdown Enable
|
| 1841 |
|
|
.led_col_18(led_col_18), //OUTPUT : Collision Indication
|
| 1842 |
|
|
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
|
| 1843 |
|
|
.led_char_err_18(led_char_err_18), //OUTPUT : Character error
|
| 1844 |
|
|
.led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
|
| 1845 |
|
|
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
|
| 1846 |
|
|
.led_link_18(led_link_18), //OUTPUT : Valid link
|
| 1847 |
|
|
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
|
| 1848 |
|
|
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
|
| 1849 |
|
|
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
|
| 1850 |
|
|
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
|
| 1851 |
|
|
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
|
| 1852 |
|
|
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
|
| 1853 |
|
|
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
|
| 1854 |
|
|
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
|
| 1855 |
|
|
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
|
| 1856 |
|
|
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
|
| 1857 |
|
|
.data_tx_error_18(data_tx_error_18), //INPUT : Status
|
| 1858 |
|
|
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
|
| 1859 |
|
|
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
|
| 1860 |
|
|
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
|
| 1861 |
|
|
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
|
| 1862 |
|
|
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
|
| 1863 |
|
|
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1864 |
|
|
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
|
| 1865 |
|
|
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1866 |
|
|
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
|
| 1867 |
|
|
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
|
| 1868 |
|
|
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1869 |
|
|
|
| 1870 |
|
|
// Channel 19
|
| 1871 |
|
|
|
| 1872 |
|
|
.tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
|
| 1873 |
|
|
.tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
|
| 1874 |
|
|
.tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
|
| 1875 |
|
|
.tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
|
| 1876 |
|
|
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
|
| 1877 |
|
|
.powerdown_19(powerdown_19), //OUTPUT : Powerdown Enable
|
| 1878 |
|
|
.led_col_19(led_col_19), //OUTPUT : Collision Indication
|
| 1879 |
|
|
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
|
| 1880 |
|
|
.led_char_err_19(led_char_err_19), //OUTPUT : Character error
|
| 1881 |
|
|
.led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
|
| 1882 |
|
|
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
|
| 1883 |
|
|
.led_link_19(led_link_19), //OUTPUT : Valid link
|
| 1884 |
|
|
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
|
| 1885 |
|
|
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
|
| 1886 |
|
|
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
|
| 1887 |
|
|
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
|
| 1888 |
|
|
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
|
| 1889 |
|
|
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
|
| 1890 |
|
|
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
|
| 1891 |
|
|
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
|
| 1892 |
|
|
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
|
| 1893 |
|
|
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
|
| 1894 |
|
|
.data_tx_error_19(data_tx_error_19), //INPUT : Status
|
| 1895 |
|
|
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
|
| 1896 |
|
|
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
|
| 1897 |
|
|
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
|
| 1898 |
|
|
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
|
| 1899 |
|
|
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
|
| 1900 |
|
|
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1901 |
|
|
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
|
| 1902 |
|
|
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1903 |
|
|
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
|
| 1904 |
|
|
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
|
| 1905 |
|
|
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1906 |
|
|
|
| 1907 |
|
|
// Channel 20
|
| 1908 |
|
|
|
| 1909 |
|
|
.tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
|
| 1910 |
|
|
.tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
|
| 1911 |
|
|
.tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
|
| 1912 |
|
|
.tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
|
| 1913 |
|
|
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
|
| 1914 |
|
|
.powerdown_20(powerdown_20), //OUTPUT : Powerdown Enable
|
| 1915 |
|
|
.led_col_20(led_col_20), //OUTPUT : Collision Indication
|
| 1916 |
|
|
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
|
| 1917 |
|
|
.led_char_err_20(led_char_err_20), //OUTPUT : Character error
|
| 1918 |
|
|
.led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
|
| 1919 |
|
|
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
|
| 1920 |
|
|
.led_link_20(led_link_20), //OUTPUT : Valid link
|
| 1921 |
|
|
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
|
| 1922 |
|
|
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
|
| 1923 |
|
|
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
|
| 1924 |
|
|
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
|
| 1925 |
|
|
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
|
| 1926 |
|
|
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
|
| 1927 |
|
|
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
|
| 1928 |
|
|
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
|
| 1929 |
|
|
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
|
| 1930 |
|
|
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
|
| 1931 |
|
|
.data_tx_error_20(data_tx_error_20), //INPUT : Status
|
| 1932 |
|
|
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
|
| 1933 |
|
|
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
|
| 1934 |
|
|
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
|
| 1935 |
|
|
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
|
| 1936 |
|
|
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
|
| 1937 |
|
|
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1938 |
|
|
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
|
| 1939 |
|
|
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1940 |
|
|
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
|
| 1941 |
|
|
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
|
| 1942 |
|
|
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1943 |
|
|
|
| 1944 |
|
|
// Channel 21
|
| 1945 |
|
|
|
| 1946 |
|
|
.tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
|
| 1947 |
|
|
.tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
|
| 1948 |
|
|
.tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
|
| 1949 |
|
|
.tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
|
| 1950 |
|
|
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
|
| 1951 |
|
|
.powerdown_21(powerdown_21), //OUTPUT : Powerdown Enable
|
| 1952 |
|
|
.led_col_21(led_col_21), //OUTPUT : Collision Indication
|
| 1953 |
|
|
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
|
| 1954 |
|
|
.led_char_err_21(led_char_err_21), //OUTPUT : Character error
|
| 1955 |
|
|
.led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
|
| 1956 |
|
|
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
|
| 1957 |
|
|
.led_link_21(led_link_21), //OUTPUT : Valid link
|
| 1958 |
|
|
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
|
| 1959 |
|
|
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
|
| 1960 |
|
|
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
|
| 1961 |
|
|
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
|
| 1962 |
|
|
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
|
| 1963 |
|
|
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
|
| 1964 |
|
|
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
|
| 1965 |
|
|
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
|
| 1966 |
|
|
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
|
| 1967 |
|
|
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
|
| 1968 |
|
|
.data_tx_error_21(data_tx_error_21), //INPUT : Status
|
| 1969 |
|
|
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
|
| 1970 |
|
|
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
|
| 1971 |
|
|
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
|
| 1972 |
|
|
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
|
| 1973 |
|
|
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
|
| 1974 |
|
|
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 1975 |
|
|
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
|
| 1976 |
|
|
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 1977 |
|
|
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
|
| 1978 |
|
|
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
|
| 1979 |
|
|
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
|
| 1980 |
|
|
|
| 1981 |
|
|
// Channel 22
|
| 1982 |
|
|
|
| 1983 |
|
|
.tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
|
| 1984 |
|
|
.tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
|
| 1985 |
|
|
.tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
|
| 1986 |
|
|
.tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
|
| 1987 |
|
|
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
|
| 1988 |
|
|
.powerdown_22(powerdown_22), //OUTPUT : Powerdown Enable
|
| 1989 |
|
|
.led_col_22(led_col_22), //OUTPUT : Collision Indication
|
| 1990 |
|
|
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
|
| 1991 |
|
|
.led_char_err_22(led_char_err_22), //OUTPUT : Character error
|
| 1992 |
|
|
.led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
|
| 1993 |
|
|
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
|
| 1994 |
|
|
.led_link_22(led_link_22), //OUTPUT : Valid link
|
| 1995 |
|
|
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
|
| 1996 |
|
|
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
|
| 1997 |
|
|
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
|
| 1998 |
|
|
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
|
| 1999 |
|
|
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
|
| 2000 |
|
|
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
|
| 2001 |
|
|
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
|
| 2002 |
|
|
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
|
| 2003 |
|
|
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
|
| 2004 |
|
|
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
|
| 2005 |
|
|
.data_tx_error_22(data_tx_error_22), //INPUT : Status
|
| 2006 |
|
|
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
|
| 2007 |
|
|
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
|
| 2008 |
|
|
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
|
| 2009 |
|
|
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
|
| 2010 |
|
|
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
|
| 2011 |
|
|
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 2012 |
|
|
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
|
| 2013 |
|
|
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 2014 |
|
|
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
|
| 2015 |
|
|
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
|
| 2016 |
|
|
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
|
| 2017 |
|
|
|
| 2018 |
|
|
// Channel 23
|
| 2019 |
|
|
|
| 2020 |
|
|
.tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
|
| 2021 |
|
|
.tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
|
| 2022 |
|
|
.tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
|
| 2023 |
|
|
.tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
|
| 2024 |
|
|
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
|
| 2025 |
|
|
.powerdown_23(powerdown_23), //OUTPUT : Powerdown Enable
|
| 2026 |
|
|
.led_col_23(led_col_23), //OUTPUT : Collision Indication
|
| 2027 |
|
|
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
|
| 2028 |
|
|
.led_char_err_23(led_char_err_23), //OUTPUT : Character error
|
| 2029 |
|
|
.led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
|
| 2030 |
|
|
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
|
| 2031 |
|
|
.led_link_23(led_link_23), //OUTPUT : Valid link
|
| 2032 |
|
|
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
|
| 2033 |
|
|
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
|
| 2034 |
|
|
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
|
| 2035 |
|
|
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
|
| 2036 |
|
|
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
|
| 2037 |
|
|
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
|
| 2038 |
|
|
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
|
| 2039 |
|
|
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
|
| 2040 |
|
|
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
|
| 2041 |
|
|
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
|
| 2042 |
|
|
.data_tx_error_23(data_tx_error_23), //INPUT : Status
|
| 2043 |
|
|
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
|
| 2044 |
|
|
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
|
| 2045 |
|
|
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
|
| 2046 |
|
|
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
|
| 2047 |
|
|
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
|
| 2048 |
|
|
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
|
| 2049 |
|
|
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
|
| 2050 |
|
|
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
|
| 2051 |
|
|
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
|
| 2052 |
|
|
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
|
| 2053 |
|
|
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
|
| 2054 |
|
|
|
| 2055 |
|
|
defparam
|
| 2056 |
|
|
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
|
| 2057 |
|
|
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
|
| 2058 |
|
|
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
|
| 2059 |
|
|
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
|
| 2060 |
|
|
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
|
| 2061 |
|
|
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
|
| 2062 |
|
|
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
|
| 2063 |
|
|
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
|
| 2064 |
|
|
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
|
| 2065 |
|
|
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
|
| 2066 |
|
|
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
|
| 2067 |
|
|
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
|
| 2068 |
|
|
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
|
| 2069 |
|
|
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
|
| 2070 |
|
|
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
|
| 2071 |
|
|
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
|
| 2072 |
|
|
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
|
| 2073 |
|
|
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
|
| 2074 |
|
|
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
|
| 2075 |
|
|
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
|
| 2076 |
|
|
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
|
| 2077 |
|
|
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
|
| 2078 |
|
|
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
|
| 2079 |
|
|
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
|
| 2080 |
|
|
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
|
| 2081 |
|
|
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
|
| 2082 |
|
|
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
|
| 2083 |
|
|
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
|
| 2084 |
|
|
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
|
| 2085 |
|
|
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
|
| 2086 |
|
|
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
|
| 2087 |
|
|
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
|
| 2088 |
|
|
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
|
| 2089 |
|
|
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
|
| 2090 |
|
|
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
|
| 2091 |
|
|
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
|
| 2092 |
|
|
|
| 2093 |
|
|
|
| 2094 |
|
|
endmodule // module altera_tse_multi_mac_pcs
|
