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// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

//

// Revision Control Information

//

// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $

// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige.v,v $

//

// $Revision: #1 $

// $Date: 2012/06/21 $

// Check in by : $Author: swbranch $

// Author      : Arul Paniandi

//

// Project     : Triple Speed Ethernet - 10/100/1000 MAC

//

// Description : 

//

// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII

// interfaces, mdio module and register space (statistic, control and 

// management)

// 

// ALTERA Confidential and Proprietary

// Copyright 2006 (c) Altera Corporation  

// All rights reserved

//

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)

module altera_tse_multi_mac_pcs_pma_gige

#(

parameter USE_SYNC_RESET        = 0,                    //  Use Synchronized Reset Inputs

parameter RESET_LEVEL           = 1'b 1 ,               //  Reset Active Level

parameter ENABLE_GMII_LOOPBACK  = 1,                    //  GMII_LOOPBACK_ENA : Enable GMII Loopback Logic 

parameter ENABLE_HD_LOGIC       = 1,                    //  HD_LOGIC_ENA : Enable Half Duplex Logic

parameter ENABLE_SUP_ADDR       = 1,                    //  SUP_ADDR_ENA : Enable Supplemental Addresses

parameter ENA_HASH              = 1,                    //  ENA_HASH Enable Hash Table 

parameter STAT_CNT_ENA          = 1,                    //  STAT_CNT_ENA Enable Statistic Counters

parameter MDIO_CLK_DIV          = 40 ,                  //  Host Clock Division - MDC Generation

parameter CORE_VERSION          = 16'h3,                //  ALTERA Core Version

parameter CUST_VERSION          = 1 ,                   //  Customer Core Version

parameter REDUCED_INTERFACE_ENA = 0,                    //  Enable the RGMII Interface

parameter ENABLE_MDIO           = 1,                    //  Enable the MDIO Interface

parameter ENABLE_MAGIC_DETECT   = 1,                    //  Enable magic packet detection 

parameter ENABLE_PADDING        = 1,                    //  Enable padding operation.

parameter ENABLE_LGTH_CHECK     = 1,                    //  Enable frame length checking.

parameter GBIT_ONLY             = 1,                    //  Enable Gigabit only operation.

parameter MBIT_ONLY             = 1,                    //  Enable Megabit (10/100) only operation.

parameter REDUCED_CONTROL       = 0,                    //  Reduced control for MAC LITE

parameter CRC32DWIDTH           = 4'b 1000,             //  input data width (informal, not for change)

parameter CRC32GENDELAY         = 3'b 110,              //  when the data from the generator is valid

parameter CRC32CHECK16BIT       = 1'b 0,                //  1 compare two times 16 bit of the CRC (adds one pipeline step) 

parameter CRC32S1L2_EXTERN      = 1'b0,                 //  false: merge enable

parameter ENABLE_SHIFT16        = 0,                    //  Enable byte stuffing at packet header 

parameter ENABLE_MAC_FLOW_CTRL  = 1'b1,                 //  Option to enable flow control 

parameter ENABLE_MAC_TXADDR_SET = 1'b1,                 //  Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path

parameter ENABLE_MAC_RX_VLAN    = 1'b1,                 //  Option to enable VLAN tagged Ethernet frames on MAC RX data path

parameter ENABLE_MAC_TX_VLAN    = 1'b1,                 //  Option to enable VLAN tagged Ethernet frames on MAC TX data path

parameter PHY_IDENTIFIER        = 32'h 00000000,        //  PHY Identifier

parameter DEV_VERSION           = 16'h 0001 ,           //  Customer Phy's Core Version

parameter ENABLE_SGMII          = 1,                    //  Enable SGMII logic for synthesis

parameter ENABLE_CLK_SHARING    = 1,                    //  Option to share clock for multiple channels (Clocks are rate-matched).

parameter ENABLE_REG_SHARING    = 0,                    //  Option to share register space. Uses certain hard-coded values from input.

parameter ENABLE_EXTENDED_STAT_REG = 0,                 //  Enable a few extended statistic registers

parameter MAX_CHANNELS          = 1,                    //  The number of channels in Multi-TSE component

parameter ENABLE_PKT_CLASS      = 1,                    //  Enable Packet Classification Av-ST Interface

parameter ENABLE_RX_FIFO_STATUS = 1,                    //  Enable Receive FIFO Almost Full status interface

parameter CHANNEL_WIDTH         = 1,                    //  The width of the channel interface

parameter EXPORT_PWRDN          = 1'b0,                 //  Option to export the Alt2gxb powerdown signal

parameter DEVICE_FAMILY         = "ARRIAGX",            //  The device family the the core is targetted for.

parameter TRANSCEIVER_OPTION    = 1'b0,                 //  Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1:  0 - GXB (GIGE Mode) 1 - LVDS IO

parameter ENABLE_ALT_RECONFIG   = 0,                    //  Option to expose the altreconfig ports

parameter SYNCHRONIZER_DEPTH    = 3,                    //  Number of synchronizer

// Internal parameters

parameter STARTING_CHANNEL_NUMBER = 0,

parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :

                       (MAX_CHANNELS > 8)? 12 :

                       (MAX_CHANNELS > 4)? 11 :

                       (MAX_CHANNELS > 2)? 10 :

                       (MAX_CHANNELS > 1)? 9 : 8,

//IEEE1588 code

parameter ENABLE_TIMESTAMPING               = 0,                //      To enable time stamping logic

parameter ENABLE_PTP_1STEP                      = 0,            //      To enable time 1 step clock PTP

parameter TSTAMP_FP_WIDTH                   = 4         //      Finger print width associated to the timestamp request

)

// Port List

(

    // RESET / MAC REG IF / MDIO

    input wire                               reset, //  Asynchronous Reset - clk Domain

    input wire                               clk, //  25MHz Host Interface Clock

    input wire                               read, //  Register Read Strobe

    input wire                               write, //  Register Write Strobe

    input wire [ADDR_WIDTH-1:0]              address, //  Register Address

    input wire [31:0]                        writedata, //  Write Data for Host Bus

    output wire [31:0]                       readdata, //  Read Data to Host Bus

    output wire                              waitrequest, //  Interface Busy

    output wire                              mdc, //  2.5MHz Inteface

    input wire                               mdio_in, //  MDIO Input

    output wire                              mdio_out, //  MDIO Output

    output wire                              mdio_oen, //  MDIO Output Enable

    // DEVICE SPECIFIC SIGNALS

    input wire                               gxb_cal_blk_clk, //  GXB Calibration Clock

    input wire                               ref_clk, //  Rference Clock

        // SHARED CLK SIGNALS

    output wire                              mac_rx_clk, //  Av-ST Receive Clock

    output wire                              mac_tx_clk, //  Av-ST Transmit Clock 

    input wire                               pcs_phase_measure_clk,

        // SHARED RX STATUS

    input wire                               rx_afull_clk, //  Almost full clk

    input wire [1:0]                         rx_afull_data, //  Almost full data

    input wire                               rx_afull_valid, //  Almost full valid

    input wire [CHANNEL_WIDTH-1:0]           rx_afull_channel, //  Almost full channel

    // CHANNEL 0

    // PCS SIGNALS TO PHY

    input wire                               rxp_0, //  Differential Receive Data 

    output wire                              txp_0, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_0, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_0, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_0, //  Receiver Recovered Clock 

    output wire                              led_crs_0, //  Carrier Sense

    output wire                              led_link_0, //  Valid Link 

    output wire                              led_col_0, //  Collision Indication

    output wire                              led_an_0, //  Auto-Negotiation Status

    output wire                              led_char_err_0, //  Character Error

    output wire                              led_disp_err_0, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_0, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_0, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_0, //  Start of Packet

    output wire                              data_rx_eop_0, //  End of Packet

    output wire [7:0]                        data_rx_data_0, //  Data from FIFO

    output wire [4:0]                        data_rx_error_0, //  Receive packet error

    output wire                              data_rx_valid_0, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_0, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_0, //  Frame Type Indication

    output wire                              pkt_class_valid_0, //  Frame Type Indication Valid 

    input wire                               data_tx_error_0, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_0, //  Data from FIFO transmit

    input wire                               data_tx_valid_0, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_0, //  Start of Packet

    input wire                               data_tx_eop_0, //  END of Packet

    output wire                              data_tx_ready_0, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_0, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_0, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_0, //  Xoff Pause frame generate 

    input wire                               xon_gen_0, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_0, //  Enable Sleep Mode

    output wire                              magic_wakeup_0, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_0, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_0, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_0, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_0, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_0, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_0, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_0, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_0, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_0, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_0, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_0, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_0, //  Clock for reconfiguration block

    input wire                               reconfig_busy_0, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_0, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_0, //  Signals from the gxb block to the reconfig block

    // CHANNEL 1

    // PCS SIGNALS TO PHY

    input wire                               rxp_1, //  Differential Receive Data 

    output wire                              txp_1, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_1, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_1, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_1, //  Receiver Recovered Clock 

    output wire                              led_crs_1, //  Carrier Sense

    output wire                              led_link_1, //  Valid Link 

    output wire                              led_col_1, //  Collision Indication

    output wire                              led_an_1, //  Auto-Negotiation Status

    output wire                              led_char_err_1, //  Character Error

    output wire                              led_disp_err_1, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_1, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_1, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_1, //  Start of Packet

    output wire                              data_rx_eop_1, //  End of Packet

    output wire [7:0]                        data_rx_data_1, //  Data from FIFO

    output wire [4:0]                        data_rx_error_1, //  Receive packet error

    output wire                              data_rx_valid_1, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_1, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_1, //  Frame Type Indication

    output wire                              pkt_class_valid_1, //  Frame Type Indication Valid 

    input wire                               data_tx_error_1, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_1, //  Data from FIFO transmit

    input wire                               data_tx_valid_1, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_1, //  Start of Packet

    input wire                               data_tx_eop_1, //  END of Packet

    output wire                              data_tx_ready_1, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_1, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_1, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_1, //  Xoff Pause frame generate 

    input wire                               xon_gen_1, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_1, //  Enable Sleep Mode

    output wire                              magic_wakeup_1, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_1, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_1, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_1, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_1, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_1, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_1, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_1, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_1, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_1, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_1, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_1, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_1, //  Clock for reconfiguration block

    input wire                               reconfig_busy_1, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_1, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_1, //  Signals from the gxb block to the reconfig block

    // CHANNEL 2

    // PCS SIGNALS TO PHY

    input wire                               rxp_2, //  Differential Receive Data 

    output wire                              txp_2, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_2, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_2, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_2, //  Receiver Recovered Clock 

    output wire                              led_crs_2, //  Carrier Sense

    output wire                              led_link_2, //  Valid Link 

    output wire                              led_col_2, //  Collision Indication

    output wire                              led_an_2, //  Auto-Negotiation Status

    output wire                              led_char_err_2, //  Character Error

    output wire                              led_disp_err_2, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_2, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_2, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_2, //  Start of Packet

    output wire                              data_rx_eop_2, //  End of Packet

    output wire [7:0]                        data_rx_data_2, //  Data from FIFO

    output wire [4:0]                        data_rx_error_2, //  Receive packet error

    output wire                              data_rx_valid_2, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_2, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_2, //  Frame Type Indication

    output wire                              pkt_class_valid_2, //  Frame Type Indication Valid 

    input wire                               data_tx_error_2, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_2, //  Data from FIFO transmit

    input wire                               data_tx_valid_2, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_2, //  Start of Packet

    input wire                               data_tx_eop_2, //  END of Packet

    output wire                              data_tx_ready_2, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_2, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_2, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_2, //  Xoff Pause frame generate 

    input wire                               xon_gen_2, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_2, //  Enable Sleep Mode

    output wire                              magic_wakeup_2, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_2, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_2, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_2, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_2, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_2, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_2, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_2, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_2, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_2, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_2, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_2, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_2, //  Clock for reconfiguration block

    input wire                               reconfig_busy_2, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_2, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_2, //  Signals from the gxb block to the reconfig block

    // CHANNEL 3

    // PCS SIGNALS TO PHY

    input wire                               rxp_3, //  Differential Receive Data 

    output wire                              txp_3, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_3, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_3, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_3, //  Receiver Recovered Clock 

    output wire                              led_crs_3, //  Carrier Sense

    output wire                              led_link_3, //  Valid Link 

    output wire                              led_col_3, //  Collision Indication

    output wire                              led_an_3, //  Auto-Negotiation Status

    output wire                              led_char_err_3, //  Character Error

    output wire                              led_disp_err_3, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_3, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_3, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_3, //  Start of Packet

    output wire                              data_rx_eop_3, //  End of Packet

    output wire [7:0]                        data_rx_data_3, //  Data from FIFO

    output wire [4:0]                        data_rx_error_3, //  Receive packet error

    output wire                              data_rx_valid_3, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_3, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_3, //  Frame Type Indication

    output wire                              pkt_class_valid_3, //  Frame Type Indication Valid 

    input wire                               data_tx_error_3, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_3, //  Data from FIFO transmit

    input wire                               data_tx_valid_3, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_3, //  Start of Packet

    input wire                               data_tx_eop_3, //  END of Packet

    output wire                              data_tx_ready_3, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_3, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_3, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_3, //  Xoff Pause frame generate 

    input wire                               xon_gen_3, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_3, //  Enable Sleep Mode

    output wire                              magic_wakeup_3, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_3, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_3, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_3, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_3, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_3, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_3, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_3, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_3, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_3, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_3, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_3, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_3, //  Clock for reconfiguration block

    input wire                               reconfig_busy_3, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_3, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_3, //  Signals from the gxb block to the reconfig block

    // CHANNEL 4

    // PCS SIGNALS TO PHY

    input wire                               rxp_4, //  Differential Receive Data 

    output wire                              txp_4, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_4, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_4, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_4, //  Receiver Recovered Clock 

    output wire                              led_crs_4, //  Carrier Sense

    output wire                              led_link_4, //  Valid Link 

    output wire                              led_col_4, //  Collision Indication

    output wire                              led_an_4, //  Auto-Negotiation Status

    output wire                              led_char_err_4, //  Character Error

    output wire                              led_disp_err_4, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_4, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_4, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_4, //  Start of Packet

    output wire                              data_rx_eop_4, //  End of Packet

    output wire [7:0]                        data_rx_data_4, //  Data from FIFO

    output wire [4:0]                        data_rx_error_4, //  Receive packet error

    output wire                              data_rx_valid_4, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_4, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_4, //  Frame Type Indication

    output wire                              pkt_class_valid_4, //  Frame Type Indication Valid 

    input wire                               data_tx_error_4, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_4, //  Data from FIFO transmit

    input wire                               data_tx_valid_4, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_4, //  Start of Packet

    input wire                               data_tx_eop_4, //  END of Packet

    output wire                              data_tx_ready_4, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_4, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_4, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_4, //  Xoff Pause frame generate 

    input wire                               xon_gen_4, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_4, //  Enable Sleep Mode

    output wire                              magic_wakeup_4, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_4, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_4, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_4, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_4, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_4, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_4, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_4, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_4, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_4, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_4, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_4, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_4, //  Clock for reconfiguration block

    input wire                               reconfig_busy_4, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_4, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_4, //  Signals from the gxb block to the reconfig block

    // CHANNEL 5

    // PCS SIGNALS TO PHY

    input wire                               rxp_5, //  Differential Receive Data 

    output wire                              txp_5, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_5, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_5, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_5, //  Receiver Recovered Clock 

    output wire                              led_crs_5, //  Carrier Sense

    output wire                              led_link_5, //  Valid Link 

    output wire                              led_col_5, //  Collision Indication

    output wire                              led_an_5, //  Auto-Negotiation Status

    output wire                              led_char_err_5, //  Character Error

    output wire                              led_disp_err_5, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_5, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_5, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_5, //  Start of Packet

    output wire                              data_rx_eop_5, //  End of Packet

    output wire [7:0]                        data_rx_data_5, //  Data from FIFO

    output wire [4:0]                        data_rx_error_5, //  Receive packet error

    output wire                              data_rx_valid_5, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_5, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_5, //  Frame Type Indication

    output wire                              pkt_class_valid_5, //  Frame Type Indication Valid 

    input wire                               data_tx_error_5, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_5, //  Data from FIFO transmit

    input wire                               data_tx_valid_5, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_5, //  Start of Packet

    input wire                               data_tx_eop_5, //  END of Packet

    output wire                              data_tx_ready_5, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_5, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_5, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_5, //  Xoff Pause frame generate 

    input wire                               xon_gen_5, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_5, //  Enable Sleep Mode

    output wire                              magic_wakeup_5, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_5, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_5, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_5, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_5, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_5, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_5, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_5, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_5, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_5, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_5, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_5, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_5, //  Clock for reconfiguration block

    input wire                               reconfig_busy_5, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_5, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_5, //  Signals from the gxb block to the reconfig block

    // CHANNEL 6

    // PCS SIGNALS TO PHY

    input wire                               rxp_6, //  Differential Receive Data 

    output wire                              txp_6, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_6, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_6, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_6, //  Receiver Recovered Clock 

    output wire                              led_crs_6, //  Carrier Sense

    output wire                              led_link_6, //  Valid Link 

    output wire                              led_col_6, //  Collision Indication

    output wire                              led_an_6, //  Auto-Negotiation Status

    output wire                              led_char_err_6, //  Character Error

    output wire                              led_disp_err_6, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_6, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_6, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_6, //  Start of Packet

    output wire                              data_rx_eop_6, //  End of Packet

    output wire [7:0]                        data_rx_data_6, //  Data from FIFO

    output wire [4:0]                        data_rx_error_6, //  Receive packet error

    output wire                              data_rx_valid_6, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_6, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_6, //  Frame Type Indication

    output wire                              pkt_class_valid_6, //  Frame Type Indication Valid 

    input wire                               data_tx_error_6, //  STATUS FIFO (Tx frame Error from Apps)

    input wire [7:0]                         data_tx_data_6, //  Data from FIFO transmit

    input wire                               data_tx_valid_6, //  Data FIFO transmit Empty

    input wire                               data_tx_sop_6, //  Start of Packet

    input wire                               data_tx_eop_6, //  END of Packet

    output wire                              data_tx_ready_6, //  Data FIFO transmit Read Enable        

    // STAND_ALONE CONDUITS 

    output wire                              tx_ff_uflow_6, //  TX FIFO underflow occured (Synchronous with tx_clk)

    input wire                               tx_crc_fwd_6, //  Forward Current Frame with CRC from Application

    input wire                               xoff_gen_6, //  Xoff Pause frame generate 

    input wire                               xon_gen_6, //  Xon Pause frame generate 

    input wire                               magic_sleep_n_6, //  Enable Sleep Mode

    output wire                              magic_wakeup_6, //  Wake Up Request

// IEEE1588's code

    input wire                               tx_egress_timestamp_request_valid_6, //    Timestamp request valid from user

    input wire [(TSTAMP_FP_WIDTH)-1:0]       tx_egress_timestamp_request_data_6, //    Fingerprint associated to the timestamp request

    input wire                               tx_egress_timestamp_insert_valid_6, //    Timestamp insert in 1 step clock

    output wire                              tx_egress_timestamp_valid_6, //    Timestamp + fingerprint from TSU

    output wire [(96 + TSTAMP_FP_WIDTH)-1:0] tx_egress_timestamp_data_6, //    Timestamp + fingerprint from TSU

    input wire [96-1:0]                      tx_time_of_day_data_6, //    Time of Day

    input wire                               tx_ingress_timestamp_valid_6, //    Timestamp to TSU

    input wire [(96)-1:0]                    tx_ingress_timestamp_data_6, //    Timestamp to TSU

    output wire                              rx_ingress_timestamp_valid_6, //    RX timestamp valid

    output wire [(96)-1:0]                   rx_ingress_timestamp_data_6, //    RX timestamp data

    input wire [96-1:0]                      rx_time_of_day_data_6, //    Time of Day

    // RECONFIG BLOCK SIGNALS

    input wire                               reconfig_clk_6, //  Clock for reconfiguration block

    input wire                               reconfig_busy_6, //  Busy from reconfiguration block

    input wire [3:0]                         reconfig_togxb_6, //  Signals from the reconfig block to the GXB block

    output wire [16:0]                       reconfig_fromgxb_6, //  Signals from the gxb block to the reconfig block

    // CHANNEL 7

    // PCS SIGNALS TO PHY

    input wire                               rxp_7, //  Differential Receive Data 

    output wire                              txp_7, //  Differential Transmit Data 

    input wire                               gxb_pwrdn_in_7, //  Powerdown signal to GXB

    output wire                              pcs_pwrdn_out_7, //  Powerdown Enable from PCS

    output wire                              rx_recovclkout_7, //  Receiver Recovered Clock 

    output wire                              led_crs_7, //  Carrier Sense

    output wire                              led_link_7, //  Valid Link 

    output wire                              led_col_7, //  Collision Indication

    output wire                              led_an_7, //  Auto-Negotiation Status

    output wire                              led_char_err_7, //  Character Error

    output wire                              led_disp_err_7, //  Disparity Error

    // AV-ST TX & RX

    output wire                              mac_rx_clk_7, //  Av-ST Receive Clock

    output wire                              mac_tx_clk_7, //  Av-ST Transmit Clock   

    output wire                              data_rx_sop_7, //  Start of Packet

    output wire                              data_rx_eop_7, //  End of Packet

    output wire [7:0]                        data_rx_data_7, //  Data from FIFO

    output wire [4:0]                        data_rx_error_7, //  Receive packet error

    output wire                              data_rx_valid_7, //  Data Receive FIFO Valid

    input wire                               data_rx_ready_7, //  Data Receive Ready

    output wire [4:0]                        pkt_class_data_7, //  Frame Type Indication