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jefflieu |
// megafunction wizard: %ALTDDIO_IN%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altddio_in
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// ============================================================
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// File Name: rgmii_in4.v
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// Megafunction Name(s):
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// altddio_in
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 6.0 Build 176 04/19/2006 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2006 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module altera_tse_rgmii_in4 (
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aclr,
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datain,
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inclock,
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dataout_h,
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dataout_l);
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input aclr;
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input [3:0] datain;
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input inclock;
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output [3:0] dataout_h;
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output [3:0] dataout_l;
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wire [3:0] sub_wire0;
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wire [3:0] sub_wire1;
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wire [3:0] dataout_h = sub_wire0[3:0];
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wire [3:0] dataout_l = sub_wire1[3:0];
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altddio_in altddio_in_component (
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.datain (datain),
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.inclock (inclock),
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.aclr (aclr),
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.dataout_h (sub_wire0),
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.dataout_l (sub_wire1),
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.aset (1'b0),
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.inclocken (1'b1));
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defparam
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altddio_in_component.intended_device_family = "Stratix II",
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altddio_in_component.invert_input_clocks = "OFF",
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altddio_in_component.lpm_type = "altddio_in",
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altddio_in_component.width = 4;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
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// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
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// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
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// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
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// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
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// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
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// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
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// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
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// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
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// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
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// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
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// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
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// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
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// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
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