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[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [triple_speed_ethernet-library/] [altera_tse_rgmii_module.v] - Blame information for rev 20

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1 9 jefflieu 
// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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//
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// Revision Control Information
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//
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// $RCSfile: altera_tse_rgmii_module.v,v $
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// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
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//
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// $Revision: #1 $
10 20 jefflieu 
// $Date: 2012/06/21 $
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// Check in by : $Author: swbranch $
12 9 jefflieu 
// Author      : Arul Paniandi
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//
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// Project     : Triple Speed Ethernet - 10/100/1000 MAC
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//
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// Description :
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//
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// Top level RGMII interface (receive and transmit) module.
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//
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// ALTERA Confidential and Proprietary
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// Copyright 2006 (c) Altera Corporation
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// All rights reserved
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//
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// synthesis translate_off
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`timescale 1ns / 100ps
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// synthesis translate_on
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module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ (   // new ports to cater for mii with RGMII interface are added
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                      // inputs
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                       rgmii_in,
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                                           speed,
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                                           //data
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                       gm_tx_d,
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                                           m_tx_d,
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                                           //control
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                       gm_tx_en,
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                                           m_tx_en,
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                       gm_tx_err,
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                                           m_tx_err,
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                       reset_rx_clk,
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                       reset_tx_clk,
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                       rx_clk,
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                       rx_control,
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                       tx_clk,
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                      // outputs:
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                       rgmii_out,
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                                           gm_rx_d,
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                                           m_rx_d,
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                       gm_rx_dv,
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                                           m_rx_en,
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                       gm_rx_err,
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                       m_rx_err,
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                                           m_rx_col,
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                                           m_rx_crs,
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                                           tx_control
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                    );
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  parameter SYNCHRONIZER_DEPTH  = 3;                //  Number of synchronizer
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  output  [  3: 0] rgmii_out;
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  output  [  7: 0] gm_rx_d;
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  output  [  3: 0] m_rx_d;
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  output           gm_rx_dv;
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  output           m_rx_en;
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  output           gm_rx_err;
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  output           m_rx_err;
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  output           m_rx_col;
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  output           m_rx_crs;
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  output           tx_control;
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  input   [  3: 0] rgmii_in;
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  input            speed;
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  input   [  7: 0] gm_tx_d;
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  input   [  3: 0] m_tx_d;
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  input            gm_tx_en;
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  input            m_tx_en;
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  input            gm_tx_err;
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  input            m_tx_err;
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  input            reset_rx_clk;
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  input            reset_tx_clk;
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  input            rx_clk;
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  input            rx_control;
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  input            tx_clk;
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  wire    [  3: 0] rgmii_out;
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  wire    [  7: 0] gm_rx_d;
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  wire             gm_rx_dv;
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  wire             m_rx_en;
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  wire             gm_rx_err;
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  wire             m_rx_err;
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  wire                     m_rx_col;
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  reg              m_rx_col_reg;
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  reg              m_rx_crs;
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  reg              rx_dv;
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  reg              rx_err;
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  wire             tx_control;
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  //wire             tx_err;
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  reg     [  7: 0] rgmii_out_4_wire;
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  reg              rgmii_out_1_wire_inp1;
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  reg              rgmii_out_1_wire_inp2;
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  wire    [  7:0 ] rgmii_in_4_wire;
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  reg     [  7:0 ] rgmii_in_4_reg;
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  reg     [  7:0 ] rgmii_in_4_temp_reg;
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  wire    [  1:0 ] rgmii_in_1_wire;
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  reg     [  1:0 ] rgmii_in_1_temp_reg;
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  reg m_tx_en_reg1;
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  reg m_tx_en_reg2;
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  reg m_tx_en_reg3;
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  reg m_tx_en_reg4;
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  assign gm_rx_d = rgmii_in_4_reg;
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  assign m_rx_d  = rgmii_in_4_reg[3:0];  // mii is only 4 bits, data are duplicated so we only take one nibble
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  altera_tse_rgmii_in4 the_rgmii_in4
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    (
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      .aclr (),         //INPUT
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      .datain (rgmii_in),           //INPUT
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      .dataout_h (rgmii_in_4_wire[7 : 4]),  //OUTPUT
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      .dataout_l (rgmii_in_4_wire[3 : 0]),  //OUTPUT
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      .inclock (rx_clk)             //OUTPUT
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    );
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  altera_tse_rgmii_in1 the_rgmii_in1
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    (
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      .aclr (),            //INPUT
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      .datain (rx_control),            //INPUT
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      .dataout_h (rgmii_in_1_wire[1]), //INPUT    rx_err
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      .dataout_l (rgmii_in_1_wire[0]), //OUTPUT   rx_dv
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      .inclock (rx_clk)                //OUTPUT
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    );
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always @(posedge rx_clk or posedge reset_rx_clk)
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    begin
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        if (reset_rx_clk == 1'b1) begin
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            rgmii_in_4_temp_reg <= {8{1'b0}};
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            rgmii_in_1_temp_reg <= {2{1'b0}};
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        end
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        else begin
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            rgmii_in_4_temp_reg <= rgmii_in_4_wire;
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            rgmii_in_1_temp_reg <= rgmii_in_1_wire;
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        end
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    end
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always @(posedge rx_clk or posedge reset_rx_clk)
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    begin
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        if (reset_rx_clk == 1'b1) begin
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            rgmii_in_4_reg <= {8{1'b0}};
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            rx_err <= 1'b0;
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            rx_dv <= 1'b0;
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        end
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        else begin
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            rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
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            rx_err <= rgmii_in_1_wire[0];
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            rx_dv <= rgmii_in_1_temp_reg[1];
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        end
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    end
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always @(rx_dv or rx_err or rgmii_in_4_reg)
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  begin
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                m_rx_crs = 1'b0;
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                if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
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                begin
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                        m_rx_crs = 1'b1;   // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
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                end
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  end
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always @(posedge tx_clk or posedge reset_tx_clk)
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begin
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        if(reset_tx_clk == 1'b1)
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        begin
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                m_tx_en_reg1 <= 1'b0;
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                m_tx_en_reg2 <= 1'b0;
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                m_tx_en_reg3 <= 1'b0;
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                m_tx_en_reg4 <= 1'b0;
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        end
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        else
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        begin
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                m_tx_en_reg1 <= m_tx_en;
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                m_tx_en_reg2 <= m_tx_en_reg1;
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                m_tx_en_reg3 <= m_tx_en_reg2;
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                m_tx_en_reg4 <= m_tx_en_reg3;
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        end
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end
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always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
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begin
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        m_rx_col_reg = 1'b0;
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        if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
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        begin
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                m_rx_col_reg = 1'b1;
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        end
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end
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altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
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                        .clk(tx_clk), // INPUT
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                        .reset_n(~reset_tx_clk), //INPUT
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                        .din(m_rx_col_reg), //INPUT
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                        .dout(m_rx_col));// OUTPUT
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  assign gm_rx_err = rx_err ^ rx_dv;
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  assign gm_rx_dv = rx_dv;
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  assign m_rx_err = rx_err ^ rx_dv;
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  assign m_rx_en = rx_dv;
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    // mux for Out 4
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  always @(*)
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  begin
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    case (speed)
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      1'b1:  rgmii_out_4_wire = gm_tx_d;
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      1'b0:  rgmii_out_4_wire = {m_tx_d,m_tx_d};
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    endcase
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  end
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   // mux for Out 1
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  always @(*)
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  begin
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    case (speed)
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      1'b1:
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                begin
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                        rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
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                        rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
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                end
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      1'b0:
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                begin
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                        rgmii_out_1_wire_inp1 = m_tx_en;
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                        rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
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                end
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    endcase
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  end
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  altera_tse_rgmii_out4 the_rgmii_out4
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    (
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      .aclr (reset_tx_clk),         //INPUT
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      .datain_h (rgmii_out_4_wire[3 : 0]),   //INPUT
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      .datain_l (rgmii_out_4_wire[7 : 4]),   //INPUT
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      .dataout (rgmii_out),         //INPUT
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      .outclock (tx_clk)            //OUTPUT
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    );
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  //assign tx_err = gm_tx_en ^ gm_tx_err;
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  altera_tse_rgmii_out1 the_rgmii_out1
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    (
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      .aclr (reset_tx_clk),         //INPUT
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      .datain_h (rgmii_out_1_wire_inp1),         //INPUT
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      .datain_l (rgmii_out_1_wire_inp2),           //INPUT
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      .dataout (tx_control),        //INPUT
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      .outclock (tx_clk)            //OUTPUT
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    );
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endmodule
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