| 1 |
4 |
jefflieu |
/*
|
| 2 |
|
|
Developed by Jeff Lieu (lieumychuong@gmail.com)
|
| 3 |
|
|
|
| 4 |
|
|
File :
|
| 5 |
|
|
Description :
|
| 6 |
|
|
In this test, we use Altera Tranceiver as Link Partner
|
| 7 |
|
|
Configure bothside to be 1000BaseX Mode
|
| 8 |
|
|
|
| 9 |
|
|
Remarks :
|
| 10 |
|
|
There seems to be a bug in Altera's core, tx path
|
| 11 |
|
|
- The Tx Path sometime omits 1 pre-ample octet depending on the cycle that TxEN is aserted.
|
| 12 |
|
|
- At the transmit task, the #8 delay will have effect on the Altera's core. Without delay,
|
| 13 |
|
|
the first packet is transmitted with the first octet somehow removed (you can confirm this
|
| 14 |
|
|
by looking at the Codegroup that is input of u0SGMII/u0Receive/
|
| 15 |
|
|
- With the delay on, the first packet is fine, but the second packet has some problem.
|
| 16 |
|
|
- This has something todo with the alignment of the TxEN,
|
| 17 |
|
|
I'm not sure whether the MAC layer is responsible for aligning TxEN's assertion or not.
|
| 18 |
|
|
- This test only Transmits normal frame, i.e no Carrier Extension or Error Propagation
|
| 19 |
|
|
|
| 20 |
|
|
- The Path of U0 --> U1 is ok.
|
| 21 |
|
|
|
| 22 |
9 |
jefflieu |
- Testing with Version 11.1sp2 core seems to be ok, this problem is not found
|
| 23 |
|
|
|
| 24 |
4 |
jefflieu |
Revision :
|
| 25 |
|
|
Date Author Description
|
| 26 |
|
|
|
| 27 |
|
|
*/
|
| 28 |
|
|
`timescale 1ns/1ps
|
| 29 |
|
|
`include "SGMIIDefs.v"
|
| 30 |
|
|
|
| 31 |
|
|
module mSGMIITestbench();
|
| 32 |
|
|
`include "Veritil.v"
|
| 33 |
|
|
|
| 34 |
|
|
|
| 35 |
|
|
reg r_Reset_L;
|
| 36 |
|
|
reg r_Clk125M;
|
| 37 |
|
|
reg r_Clk50M;
|
| 38 |
|
|
|
| 39 |
|
|
|
| 40 |
|
|
wire w_u1RxClk;
|
| 41 |
|
|
wire w_u1TxClk;
|
| 42 |
|
|
wire w_u1RxDV;
|
| 43 |
|
|
wire w_u1RxER;
|
| 44 |
|
|
wire [07:00] w8_u1RxD;
|
| 45 |
|
|
wire [07:00] w8_u1TxD;
|
| 46 |
|
|
wire w_u1TxEN;
|
| 47 |
|
|
wire w_u1TxER;
|
| 48 |
|
|
|
| 49 |
|
|
wire w_u0RxDV;
|
| 50 |
|
|
wire w_u0RxER;
|
| 51 |
|
|
wire [07:00] w8_u0RxD;
|
| 52 |
|
|
wire [07:00] w8_u0TxD;
|
| 53 |
|
|
wire w_u0TxEN;
|
| 54 |
|
|
wire w_u0TxER;
|
| 55 |
|
|
|
| 56 |
|
|
|
| 57 |
|
|
wire w_u0WbCyc, w_u0WbAck, w_u0WbStb, w_u0WbWEn;
|
| 58 |
|
|
wire [31:00] w32_u0WbAddr, w32_u0WbWrData, w32_u0WbRdData;
|
| 59 |
|
|
wire w_u1WbCyc, w_u1WbAck, w_u1WbStb, w_u1WbWEn;
|
| 60 |
|
|
wire [31:00] w32_u1WbAddr, w32_u1WbWrData, w32_u1WbRdData;
|
| 61 |
|
|
wire w_u0ANDone,w_u1ANDone;
|
| 62 |
|
|
|
| 63 |
|
|
`define tstcfg_Normal 0
|
| 64 |
|
|
`define tstcfg_CarrierExt 1
|
| 65 |
|
|
`define tstcfg_BurstTrans 2
|
| 66 |
|
|
`define tstcfg_ErrorProp1 3
|
| 67 |
|
|
`define tstcfg_ErrorProp2 4
|
| 68 |
|
|
`define tstcfg_SizeXShort 0
|
| 69 |
|
|
`define tstcfg_SizeShort 1
|
| 70 |
|
|
`define tstcfg_SizeMedium 2
|
| 71 |
|
|
`define tstcfg_SizeLarge 3
|
| 72 |
|
|
`define tstcfg_SizeXLarge 4
|
| 73 |
|
|
|
| 74 |
|
|
`define tstcfg_1000X 0
|
| 75 |
|
|
`define tstcfg_SGMII1G 1
|
| 76 |
|
|
`define tstcfg_SGMII100M 2
|
| 77 |
|
|
|
| 78 |
|
|
integer tstcfg_Standard;
|
| 79 |
|
|
|
| 80 |
|
|
integer tstcfg_PktSize;
|
| 81 |
|
|
integer tstcfg_Type;
|
| 82 |
|
|
integer tstcfg_Seed;
|
| 83 |
|
|
integer tstcfg_TxPktCnt;
|
| 84 |
|
|
integer tstcfg_RxPktCnt;
|
| 85 |
|
|
|
| 86 |
|
|
reg [15:00] r16_CoreVersion;
|
| 87 |
|
|
wire [01:00] w2_u0Speed;
|
| 88 |
|
|
|
| 89 |
|
|
|
| 90 |
|
|
initial r_Clk125M <= 1'b0;
|
| 91 |
|
|
initial r_Clk50M <= 1'b0;
|
| 92 |
|
|
always@*
|
| 93 |
|
|
#4 r_Clk125M <= ~r_Clk125M;
|
| 94 |
|
|
|
| 95 |
|
|
always@*
|
| 96 |
|
|
#10 r_Clk50M <= ~r_Clk50M;
|
| 97 |
|
|
|
| 98 |
|
|
wire w_u0Rx,w_u0Tx;
|
| 99 |
|
|
wire w_u1Rx,w_u1Tx;
|
| 100 |
|
|
|
| 101 |
|
|
initial
|
| 102 |
|
|
begin
|
| 103 |
|
|
$display("------------------------------------");
|
| 104 |
|
|
$display("-------Subtleware Ltd Pte 2012------");
|
| 105 |
|
|
$display("--Testing SGMII in 1000Gb Mode------");
|
| 106 |
|
|
$display("------------------------------------");
|
| 107 |
|
|
u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
|
| 108 |
|
|
$display("---Core Version : %x", r16_CoreVersion);
|
| 109 |
|
|
tstcfg_TxPktCnt = 0;
|
| 110 |
|
|
tstcfg_RxPktCnt = 0;
|
| 111 |
|
|
r_Reset_L <= 1'b0;
|
| 112 |
|
|
#1000;
|
| 113 |
|
|
r_Reset_L <= 1'b1;
|
| 114 |
|
|
tsk_Setup();
|
| 115 |
|
|
end
|
| 116 |
|
|
|
| 117 |
|
|
mWishboneMstr u0WishboneMstr(
|
| 118 |
|
|
.o_WbCyc (w_u0WbCyc),
|
| 119 |
|
|
.o_WbStb (w_u0WbStb),
|
| 120 |
|
|
.o_WbWEn (w_u0WbWEn),
|
| 121 |
|
|
.ov_WbAddr (w32_u0WbAddr),
|
| 122 |
|
|
.ov_WbWrData(w32_u0WbWrData),
|
| 123 |
|
|
.iv_WbRdData(w32_u0WbRdData),
|
| 124 |
|
|
.i_Ack (w_u0WbAck),
|
| 125 |
|
|
.i_Stall (1'b0),
|
| 126 |
|
|
.i_Rty (1'b0),
|
| 127 |
|
|
.i_Clk (w_u0GMIIClk));
|
| 128 |
|
|
|
| 129 |
|
|
mWishboneMstr u1WishboneMstr(
|
| 130 |
|
|
.o_WbCyc (w_u1WbCyc),
|
| 131 |
|
|
.o_WbStb (w_u1WbStb),
|
| 132 |
|
|
.o_WbWEn (w_u1WbWEn),
|
| 133 |
|
|
.ov_WbAddr (w32_u1WbAddr),
|
| 134 |
|
|
.ov_WbWrData(w32_u1WbWrData),
|
| 135 |
|
|
.iv_WbRdData(w32_u1WbRdData),
|
| 136 |
|
|
.i_Ack (w_u1WbAck),
|
| 137 |
|
|
.i_Stall (1'b0),
|
| 138 |
|
|
.i_Rty (1'b0),
|
| 139 |
|
|
.i_Clk (w_u1RxClk));
|
| 140 |
|
|
|
| 141 |
|
|
//Tranceiver Interface
|
| 142 |
|
|
mSGMII u0SGMII (
|
| 143 |
|
|
.i_SerRx (w_u0Rx),
|
| 144 |
|
|
.o_SerTx (w_u0Tx),
|
| 145 |
|
|
.i_CalClk (r_Clk50M),
|
| 146 |
|
|
.i_RefClk125M (r_Clk125M),
|
| 147 |
|
|
.i_ARstHardware_L (r_Reset_L),
|
| 148 |
|
|
|
| 149 |
|
|
//Local BUS interface
|
| 150 |
|
|
//Wishbonebus, single transaction mode (non-pipeline slave)
|
| 151 |
|
|
.i_Cyc (w_u0WbCyc),
|
| 152 |
|
|
.i_Stb (w_u0WbStb),
|
| 153 |
|
|
.i_WEn (w_u0WbWEn),
|
| 154 |
|
|
.i32_WrData (w32_u0WbWrData),
|
| 155 |
|
|
.iv_Addr (w32_u0WbAddr[7:0]),
|
| 156 |
|
|
.o32_RdData (w32_u0WbRdData),
|
| 157 |
|
|
.o_Ack (w_u0WbAck),
|
| 158 |
|
|
|
| 159 |
|
|
.i_Mdc (1'b0),
|
| 160 |
|
|
.io_Mdio (),
|
| 161 |
|
|
|
| 162 |
|
|
.i_PhyLink (1'b1),
|
| 163 |
|
|
.i2_PhySpeed(2'b00),
|
| 164 |
|
|
.i_PhyDuplex(1'b0),
|
| 165 |
|
|
//Status
|
| 166 |
|
|
.o_ANDone (w_u0ANDone),
|
| 167 |
|
|
.o_Linkup (w_u0LinkUp),
|
| 168 |
|
|
.o2_SGMIISpeed (w2_u0Speed),
|
| 169 |
|
|
.o_SGMIIDuplex (w_u0Duplex),
|
| 170 |
|
|
|
| 171 |
|
|
//GMII Interface
|
| 172 |
|
|
.i8_TxD (w8_u0TxD),
|
| 173 |
|
|
.i_TxEN (w_u0TxEN),
|
| 174 |
|
|
.i_TxER (w_u0TxER),
|
| 175 |
|
|
.o8_RxD (w8_u0RxD),
|
| 176 |
|
|
.o_RxDV (w_u0RxDV),
|
| 177 |
|
|
.o_RxER (w_u0RxER),
|
| 178 |
|
|
.o_GMIIClk (w_u0GMIIClk),
|
| 179 |
|
|
.o_Col (),
|
| 180 |
|
|
.o_Crs ());
|
| 181 |
|
|
|
| 182 |
|
|
|
| 183 |
|
|
|
| 184 |
|
|
sgmii u1SGMII (
|
| 185 |
|
|
.gmii_rx_d (w8_u1RxD),
|
| 186 |
|
|
.gmii_rx_dv (w_u1RxDV),
|
| 187 |
|
|
.gmii_rx_err (w_u1RxER),
|
| 188 |
|
|
|
| 189 |
|
|
.gmii_tx_d (w8_u1TxD),
|
| 190 |
|
|
.gmii_tx_en (w_u1TxEN),
|
| 191 |
|
|
.gmii_tx_err (w_u1TxER),
|
| 192 |
|
|
|
| 193 |
|
|
.tx_clk (w_u1TxClk),//output,
|
| 194 |
|
|
.rx_clk (w_u1RxClk),
|
| 195 |
|
|
.led_an (w_u1ANDone),
|
| 196 |
|
|
.led_disp_err (),
|
| 197 |
|
|
.led_char_err (),
|
| 198 |
|
|
.led_link (w_led_link),
|
| 199 |
|
|
.rx_recovclkout (),
|
| 200 |
|
|
|
| 201 |
|
|
.rxp (w_u1Rx),
|
| 202 |
|
|
.txp (w_u1Tx),
|
| 203 |
|
|
.pcs_pwrdn_out (),
|
| 204 |
|
|
.reconfig_fromgxb (),
|
| 205 |
|
|
|
| 206 |
|
|
.reset_tx_clk (~r_Reset_L),
|
| 207 |
|
|
.reset_rx_clk (~r_Reset_L),
|
| 208 |
|
|
|
| 209 |
|
|
.readdata (w32_u1WbRdData[15:00]),
|
| 210 |
|
|
.waitrequest (w_AvlWaitReq),
|
| 211 |
|
|
.address (w32_u1WbAddr[6:2]),
|
| 212 |
|
|
.read (w_AvlRd),
|
| 213 |
|
|
.writedata (w32_u1WbWrData[15:00]),
|
| 214 |
|
|
.write (w_AvlWr),
|
| 215 |
|
|
.clk (w_u1RxClk),
|
| 216 |
|
|
.reset (~r_Reset_L),
|
| 217 |
|
|
|
| 218 |
|
|
.ref_clk (r_Clk125M),
|
| 219 |
|
|
.gxb_pwrdn_in (1'b0),
|
| 220 |
|
|
.gxb_cal_blk_clk (r_Clk50M),
|
| 221 |
|
|
.reconfig_clk (r_Clk50M),
|
| 222 |
|
|
.reconfig_togxb (5'b0),
|
| 223 |
|
|
.reconfig_busy ());
|
| 224 |
|
|
|
| 225 |
|
|
|
| 226 |
|
|
//MacEmulation
|
| 227 |
|
|
mMACEmulator u0MacEmulator(
|
| 228 |
|
|
.i_RxClk (w_u0GMIIClk),
|
| 229 |
|
|
.i_TxClk (w_u0GMIIClk),
|
| 230 |
|
|
|
| 231 |
|
|
.i8_RxD (w8_u0RxD),
|
| 232 |
|
|
.i_RxDV (w_u0RxDV),
|
| 233 |
|
|
.i_RxER (w_u0RxER),
|
| 234 |
|
|
.o8_TxD (w8_u0TxD),
|
| 235 |
|
|
.o_TxEN (w_u0TxEN),
|
| 236 |
|
|
.o_TxER (w_u0TxER),
|
| 237 |
|
|
|
| 238 |
|
|
.i_Reset_L(r_Reset_L));
|
| 239 |
|
|
|
| 240 |
|
|
mMACEmulator u1MacEmulator(
|
| 241 |
|
|
.i_RxClk (w_u1RxClk),
|
| 242 |
|
|
.i_TxClk (w_u1TxClk),
|
| 243 |
|
|
.i8_RxD (w8_u1RxD),
|
| 244 |
|
|
.i_RxDV (w_u1RxDV),
|
| 245 |
|
|
.i_RxER (w_u1RxER),
|
| 246 |
|
|
.o8_TxD (w8_u1TxD),
|
| 247 |
|
|
.o_TxEN (w_u1TxEN),
|
| 248 |
|
|
.o_TxER (w_u1TxER),
|
| 249 |
|
|
|
| 250 |
|
|
.i_Reset_L(r_Reset_L));
|
| 251 |
|
|
|
| 252 |
|
|
|
| 253 |
|
|
|
| 254 |
|
|
//This portion translate Wishbone Signal to Avalon Signal
|
| 255 |
|
|
assign w_AvlWr = w_u1WbStb & w_u1WbCyc & w_u1WbWEn;
|
| 256 |
|
|
assign w_AvlRd = w_u1WbStb & w_u1WbCyc & (~w_u1WbWEn);
|
| 257 |
|
|
assign w_u1WbAck = ~w_AvlWaitReq;
|
| 258 |
|
|
|
| 259 |
|
|
assign w_u0Rx = w_u1Tx;
|
| 260 |
|
|
assign w_u1Rx = w_u0Tx;
|
| 261 |
|
|
|
| 262 |
|
|
reg [7:0] r8_TxBuffer[0:1023][0:10000];
|
| 263 |
|
|
integer s32_TxCarrierExtCycles[0:1023];
|
| 264 |
|
|
integer s32_TxCarrierErrCycles[0:1023];
|
| 265 |
|
|
reg [7:0] r8_u0RxBuffer[0:1023][0:10000];
|
| 266 |
|
|
reg [7:0] r8_u1RxBuffer[0:1023][0:10000];
|
| 267 |
|
|
|
| 268 |
|
|
|
| 269 |
|
|
reg [15:00] r16_u0Ability;
|
| 270 |
|
|
reg [15:00] r16_u1Ability;
|
| 271 |
|
|
reg [31:00] r32_ReadData;
|
| 272 |
|
|
integer I;
|
| 273 |
|
|
integer length;
|
| 274 |
|
|
integer u0RxPktCnt,u1RxPktCnt;
|
| 275 |
|
|
integer u0ExtCycles,u1ExtCycles;
|
| 276 |
|
|
integer u0ErrCycles,u1ErrCycles;
|
| 277 |
|
|
integer u0FrameSize,u1FrameSize;
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
initial
|
| 281 |
|
|
begin
|
| 282 |
|
|
length = 100;
|
| 283 |
|
|
|
| 284 |
|
|
#100;
|
| 285 |
|
|
|
| 286 |
|
|
$display("Waiting for Auto Negotiation Done");
|
| 287 |
|
|
#100;
|
| 288 |
|
|
while(w_u0ANDone==1'b0)
|
| 289 |
|
|
begin
|
| 290 |
|
|
@(posedge w_u0GMIIClk);#1;
|
| 291 |
|
|
end
|
| 292 |
|
|
|
| 293 |
|
|
//Verify link partner ability
|
| 294 |
|
|
u0WishboneMstr.tsk_Read(16'h14,r32_ReadData);
|
| 295 |
|
|
`CheckE(r32_ReadData,r16_u1Ability,"Link Partner Advertised Ability")
|
| 296 |
|
|
u1WishboneMstr.tsk_Read(16'h14,r32_ReadData);
|
| 297 |
|
|
`CheckE(r32_ReadData,r16_u0Ability,"Link Partner Advertised Ability")
|
| 298 |
|
|
|
| 299 |
|
|
#1000;
|
| 300 |
|
|
$display("Start Generating Scenarios");
|
| 301 |
|
|
for(I=0;I<1000;I=I+1)
|
| 302 |
|
|
tsk_ScenariosGenerator();
|
| 303 |
|
|
|
| 304 |
|
|
|
| 305 |
|
|
$display("Test Result: %s (Error Count = %d)",ErrorCnt>0?"FAILED":"PASSED",ErrorCnt);
|
| 306 |
|
|
#3000;
|
| 307 |
|
|
end
|
| 308 |
|
|
|
| 309 |
|
|
initial
|
| 310 |
|
|
begin:u1Receiving
|
| 311 |
|
|
u1RxPktCnt=0;
|
| 312 |
|
|
$display("Waiting for Auto Negotiation Done");
|
| 313 |
|
|
#100;
|
| 314 |
|
|
while(w_u1ANDone==1'b0)
|
| 315 |
|
|
begin
|
| 316 |
|
|
@(posedge w_u1RxClk);#1;
|
| 317 |
|
|
end
|
| 318 |
|
|
forever
|
| 319 |
|
|
begin
|
| 320 |
|
|
u1MacEmulator.tsk_ReceivePkt(r8_u1RxBuffer[u1RxPktCnt],u1FrameSize,u1ExtCycles,u1ErrCycles);
|
| 321 |
|
|
u1FrameSize--;
|
| 322 |
|
|
while(u1FrameSize>=0)
|
| 323 |
|
|
begin
|
| 324 |
|
|
`CheckF(r8_u1RxBuffer[u1RxPktCnt][u1FrameSize],r8_TxBuffer[u1RxPktCnt][u1FrameSize],"Received byte")
|
| 325 |
|
|
u1FrameSize--;
|
| 326 |
|
|
end
|
| 327 |
|
|
u1RxPktCnt=u1RxPktCnt+1;
|
| 328 |
|
|
$display("u1: Checked Pkt %d",u1RxPktCnt);
|
| 329 |
|
|
end
|
| 330 |
|
|
|
| 331 |
|
|
end
|
| 332 |
|
|
|
| 333 |
|
|
initial
|
| 334 |
|
|
begin:u0Receiving
|
| 335 |
|
|
u0RxPktCnt=0;
|
| 336 |
|
|
$display("Waiting for Auto Negotiation Done");
|
| 337 |
|
|
#100;
|
| 338 |
|
|
while(w_u0ANDone==1'b0)
|
| 339 |
|
|
begin
|
| 340 |
|
|
@(posedge w_u0GMIIClk);#1;
|
| 341 |
|
|
end
|
| 342 |
|
|
forever
|
| 343 |
|
|
begin
|
| 344 |
|
|
u0MacEmulator.tsk_ReceivePkt(r8_u0RxBuffer[u0RxPktCnt],u0FrameSize,u0ExtCycles,u0ErrCycles);
|
| 345 |
|
|
u0FrameSize--;
|
| 346 |
|
|
while(u0FrameSize>=0)
|
| 347 |
|
|
begin
|
| 348 |
|
|
`CheckF(r8_u0RxBuffer[u0RxPktCnt][u0FrameSize],r8_TxBuffer[u0RxPktCnt][u0FrameSize],"Received byte")
|
| 349 |
|
|
u0FrameSize--;
|
| 350 |
|
|
end
|
| 351 |
|
|
u0RxPktCnt=u0RxPktCnt+1;
|
| 352 |
|
|
$display("u0: Checked Pkt %d",u0RxPktCnt);
|
| 353 |
|
|
end
|
| 354 |
|
|
|
| 355 |
|
|
end
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
task tsk_Setup;
|
| 360 |
|
|
begin
|
| 361 |
|
|
//U1 is ALTERA's
|
| 362 |
|
|
u1WishboneMstr.tsk_Read(7'b10001_00,r16_CoreVersion);
|
| 363 |
|
|
$display("Altera SGMII Core Version %x",r16_CoreVersion);
|
| 364 |
|
|
|
| 365 |
|
|
u1WishboneMstr.tsk_Write(0,32'h0000_1000); //Enable Auto-Negotiation
|
| 366 |
|
|
r16_u1Ability=16'h01E0;
|
| 367 |
|
|
u1WishboneMstr.tsk_Write(7'b00100_00,r16_u1Ability); //Set Dev Ability
|
| 368 |
|
|
|
| 369 |
|
|
u1WishboneMstr.tsk_Write(7'b10010_00,32'h01E2); //Set Link Timer to 10000 ns
|
| 370 |
|
|
u1WishboneMstr.tsk_Write(7'b10011_00,32'h0000);
|
| 371 |
|
|
u1WishboneMstr.tsk_Read(7'b10010_00,r16_CoreVersion);
|
| 372 |
|
|
$display("Link Timer 0 %x",r16_CoreVersion);
|
| 373 |
|
|
u1WishboneMstr.tsk_Read(7'b10011_00,r16_CoreVersion);
|
| 374 |
|
|
$display("Link Timer 1 %x",r16_CoreVersion);
|
| 375 |
|
|
u1WishboneMstr.tsk_Write(7'b10100_00,{27'h0,1'b1,4'b1000}); //Enable 1000BASE-X Mode
|
| 376 |
|
|
u1WishboneMstr.tsk_Read(7'b10100_00,r16_CoreVersion);
|
| 377 |
|
|
$display("Mode Register 1 %x",r16_CoreVersion);
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
//U0 is MINE
|
| 381 |
|
|
r16_u0Ability=16'h01E0;
|
| 382 |
|
|
u0WishboneMstr.tsk_Write(7'b00100_00,r16_u0Ability); //Set Dev Ability
|
| 383 |
|
|
u0WishboneMstr.tsk_Write((8<<2),32'h0000_01E2); //Set Link Timer to 2500 ns
|
| 384 |
|
|
u0WishboneMstr.tsk_Write((9<<2),32'h0000_0000);
|
| 385 |
|
|
u0WishboneMstr.tsk_Write((31<<2),32'h0000); //Enable 1000BASE-X
|
| 386 |
|
|
$display("Restart PHY auto-nego");
|
| 387 |
|
|
u0WishboneMstr.tsk_Write(0,32'h0000_1200); //Restart Auto-negotiation
|
| 388 |
|
|
|
| 389 |
|
|
end
|
| 390 |
|
|
endtask
|
| 391 |
|
|
|
| 392 |
|
|
task tsk_ScenariosGenerator;
|
| 393 |
|
|
//Generate Type of Transmission
|
| 394 |
|
|
begin
|
| 395 |
|
|
tstcfg_Seed = $random;
|
| 396 |
|
|
tstcfg_Type = $dist_uniform(tstcfg_Seed,0,4);
|
| 397 |
|
|
tstcfg_Type = `tstcfg_Normal;
|
| 398 |
|
|
case(tstcfg_Type)
|
| 399 |
|
|
`tstcfg_Normal: begin $display("Transmit Type Normal"); tsk_TransmitNormal(); end
|
| 400 |
|
|
`tstcfg_BurstTrans: begin $display("Transmit Type Burst"); tsk_TransmitBurst(); end
|
| 401 |
|
|
`tstcfg_CarrierExt: begin $display("Transmit Type Carrier Extension"); tsk_TransmitCarrExt(); end
|
| 402 |
|
|
`tstcfg_ErrorProp1: begin $display("Transmit Type Error Prop within Frame"); tsk_TransmitErrInFrame(); end
|
| 403 |
|
|
`tstcfg_ErrorProp2: begin $display("Transmit Type Error Prop out of Frame"); tsk_TransmitErrOutFrame();end
|
| 404 |
|
|
endcase
|
| 405 |
|
|
|
| 406 |
|
|
end
|
| 407 |
|
|
endtask
|
| 408 |
|
|
|
| 409 |
|
|
task tsk_TransmitNormal;
|
| 410 |
|
|
integer PktSize;
|
| 411 |
|
|
integer PktNum;
|
| 412 |
|
|
integer PktIFG;
|
| 413 |
|
|
integer Idx;
|
| 414 |
|
|
integer Octet;
|
| 415 |
|
|
begin
|
| 416 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 417 |
|
|
for(Idx=0;Idx
|
| 418 |
|
|
begin
|
| 419 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 420 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 421 |
|
|
|
| 422 |
|
|
case(tstcfg_PktSize)
|
| 423 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 424 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 425 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 426 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 427 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 428 |
|
|
endcase
|
| 429 |
|
|
|
| 430 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=(PktSize&32'h1)?1:0;
|
| 431 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=0;
|
| 432 |
|
|
for(Octet=0;Octet
|
| 433 |
|
|
begin
|
| 434 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 435 |
|
|
end
|
| 436 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 437 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 438 |
|
|
//Transmit:
|
| 439 |
|
|
|
| 440 |
|
|
fork
|
| 441 |
|
|
begin
|
| 442 |
|
|
$display("u0: Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 443 |
|
|
u0MacEmulator.tsk_TransmitPkt(r8_TxBuffer[tstcfg_TxPktCnt+Idx],PktSize,PktIFG);
|
| 444 |
|
|
end
|
| 445 |
|
|
begin
|
| 446 |
6 |
jefflieu |
$display("u1: Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 447 |
|
|
//#8; //If You Remove This Delay, you will have error in first packet.
|
| 448 |
|
|
u1MacEmulator.tsk_TransmitPkt(r8_TxBuffer[tstcfg_TxPktCnt+Idx],PktSize,PktIFG);
|
| 449 |
4 |
jefflieu |
end
|
| 450 |
|
|
join
|
| 451 |
|
|
|
| 452 |
|
|
|
| 453 |
|
|
end
|
| 454 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 455 |
|
|
|
| 456 |
|
|
end
|
| 457 |
|
|
endtask
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
task tsk_TransmitBurst;
|
| 461 |
|
|
integer PktSize;
|
| 462 |
|
|
integer PktNum;
|
| 463 |
|
|
integer PktIFG;
|
| 464 |
|
|
integer Idx;
|
| 465 |
|
|
integer Octet;
|
| 466 |
|
|
integer ExtCycles;
|
| 467 |
|
|
integer TotalExtCycles;
|
| 468 |
|
|
integer TotalBytes;
|
| 469 |
|
|
integer PktStartOffset;
|
| 470 |
|
|
begin
|
| 471 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,6);//From 1 to 10
|
| 472 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 473 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt]=0;
|
| 474 |
|
|
TotalBytes=0;
|
| 475 |
|
|
TotalExtCycles=0;
|
| 476 |
|
|
PktStartOffset=0;
|
| 477 |
|
|
$display("Bursting : %d packets",PktNum);
|
| 478 |
|
|
for(Idx=0;Idx
|
| 479 |
|
|
begin
|
| 480 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,3); //Nojumbo
|
| 481 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,3,5);//Burst must have at least 2 /R/ interpacket R
|
| 482 |
|
|
|
| 483 |
|
|
case(tstcfg_PktSize)
|
| 484 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 485 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 486 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 487 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 488 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 489 |
|
|
endcase
|
| 490 |
|
|
|
| 491 |
|
|
TotalExtCycles=TotalExtCycles+ExtCycles;
|
| 492 |
|
|
TotalBytes = TotalBytes+PktSize;
|
| 493 |
|
|
|
| 494 |
|
|
//Generate Packet
|
| 495 |
|
|
for(Octet=0;Octet
|
| 496 |
|
|
begin
|
| 497 |
|
|
if(Octet<7)
|
| 498 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=8'h55;
|
| 499 |
|
|
else if(Octet==7)
|
| 500 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=8'hD5;
|
| 501 |
|
|
else
|
| 502 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=$random;
|
| 503 |
|
|
end
|
| 504 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+8]=PktSize & 32'h00FF;
|
| 505 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+9]=((PktSize & 32'hFF00)>>8);
|
| 506 |
|
|
//Transmit:
|
| 507 |
|
|
$display("Not complete task");
|
| 508 |
|
|
$display("Sender : Sending Packet %d (part %d) Size %d",tstcfg_TxPktCnt,Idx,PktSize);
|
| 509 |
|
|
end
|
| 510 |
|
|
//Send Interframe Gap
|
| 511 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt]=0;
|
| 512 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt]=((TotalBytes+TotalExtCycles)&32'h1)?(TotalExtCycles+1):TotalExtCycles;
|
| 513 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+1;
|
| 514 |
|
|
end
|
| 515 |
|
|
endtask
|
| 516 |
|
|
|
| 517 |
|
|
task tsk_TransmitCarrExt;
|
| 518 |
|
|
integer PktSize;
|
| 519 |
|
|
integer PktNum;
|
| 520 |
|
|
integer PktIFG;
|
| 521 |
|
|
integer Idx;
|
| 522 |
|
|
integer Octet;
|
| 523 |
|
|
integer ExtCycles;
|
| 524 |
|
|
begin
|
| 525 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 526 |
|
|
for(Idx=0;Idx
|
| 527 |
|
|
begin
|
| 528 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 529 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 530 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,1,100);//From 2 to 10
|
| 531 |
|
|
|
| 532 |
|
|
case(tstcfg_PktSize)
|
| 533 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 534 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 535 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 536 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 537 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 538 |
|
|
endcase
|
| 539 |
|
|
|
| 540 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=((PktSize+ExtCycles)&32'h1)?ExtCycles+1:ExtCycles;
|
| 541 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=0;
|
| 542 |
|
|
//Generate Packet
|
| 543 |
|
|
for(Octet=0;Octet
|
| 544 |
|
|
begin
|
| 545 |
|
|
if(Octet<7)
|
| 546 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 547 |
|
|
else if(Octet==7)
|
| 548 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 549 |
|
|
else
|
| 550 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 551 |
|
|
end
|
| 552 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 553 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 554 |
|
|
//Transmit:
|
| 555 |
|
|
$display("Not complete task");
|
| 556 |
|
|
$display("Sender : Sending Packet %d Size %d",(tstcfg_TxPktCnt+Idx),PktSize);
|
| 557 |
|
|
end
|
| 558 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 559 |
|
|
end
|
| 560 |
|
|
endtask
|
| 561 |
|
|
|
| 562 |
|
|
task tsk_TransmitErrInFrame;
|
| 563 |
|
|
integer PktSize;
|
| 564 |
|
|
integer PktNum;
|
| 565 |
|
|
integer PktIFG;
|
| 566 |
|
|
integer Idx;
|
| 567 |
|
|
integer Octet;
|
| 568 |
|
|
integer ErrorCycle;
|
| 569 |
|
|
integer ErrorPos;
|
| 570 |
|
|
begin
|
| 571 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 572 |
|
|
ErrorCycle = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 573 |
|
|
|
| 574 |
|
|
for(Idx=0;Idx
|
| 575 |
|
|
begin
|
| 576 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 577 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 578 |
|
|
|
| 579 |
|
|
case(tstcfg_PktSize)
|
| 580 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 581 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 582 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 583 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 584 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 585 |
|
|
endcase
|
| 586 |
|
|
|
| 587 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=(PktSize&32'h1)?1:0;
|
| 588 |
|
|
ErrorPos = $dist_uniform(tstcfg_Seed,1,(PktSize-ErrorCycle));
|
| 589 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=ErrorCycle;
|
| 590 |
|
|
for(Octet=0;Octet
|
| 591 |
|
|
begin
|
| 592 |
|
|
if(Octet<7)
|
| 593 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 594 |
|
|
else if(Octet==7)
|
| 595 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 596 |
|
|
else
|
| 597 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 598 |
|
|
end
|
| 599 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 600 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 601 |
|
|
//Transmit:
|
| 602 |
|
|
$display("Not complete task");
|
| 603 |
|
|
|
| 604 |
|
|
$display("Sender : Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 605 |
|
|
end
|
| 606 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 607 |
|
|
|
| 608 |
|
|
end
|
| 609 |
|
|
endtask
|
| 610 |
|
|
|
| 611 |
|
|
task tsk_TransmitErrOutFrame;
|
| 612 |
|
|
integer PktSize;
|
| 613 |
|
|
integer PktNum;
|
| 614 |
|
|
integer PktIFG;
|
| 615 |
|
|
integer Idx;
|
| 616 |
|
|
integer Octet;
|
| 617 |
|
|
integer ErrorCycle;
|
| 618 |
|
|
integer ErrorPos;
|
| 619 |
|
|
integer ExtCycles;
|
| 620 |
|
|
begin
|
| 621 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 622 |
|
|
|
| 623 |
|
|
for(Idx=0;Idx
|
| 624 |
|
|
begin
|
| 625 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,7,20);
|
| 626 |
|
|
ErrorCycle = $dist_uniform(tstcfg_Seed,1,3);//From 1 to 10
|
| 627 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 628 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 629 |
|
|
case(tstcfg_PktSize)
|
| 630 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 631 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 632 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 633 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 634 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 635 |
|
|
endcase
|
| 636 |
|
|
|
| 637 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=((PktSize+ExtCycles)&32'h1)?(ExtCycles+1):ExtCycles;
|
| 638 |
|
|
ErrorPos = $dist_uniform(tstcfg_Seed,3,(ExtCycles-ErrorCycle));
|
| 639 |
|
|
$display("----Ext = %d, Error = %d",ExtCycles,ErrorCycle);
|
| 640 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=ErrorCycle;
|
| 641 |
|
|
for(Octet=0;Octet
|
| 642 |
|
|
begin
|
| 643 |
|
|
if(Octet<7)
|
| 644 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 645 |
|
|
else if(Octet==7)
|
| 646 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 647 |
|
|
else
|
| 648 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 649 |
|
|
end
|
| 650 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 651 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 652 |
|
|
//Transmit:
|
| 653 |
|
|
$display("Not complete task");
|
| 654 |
|
|
|
| 655 |
|
|
$display("Sender : Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 656 |
|
|
end
|
| 657 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 658 |
|
|
|
| 659 |
|
|
end
|
| 660 |
|
|
endtask
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
//Informatiion
|
| 664 |
|
|
always@(*)
|
| 665 |
|
|
begin
|
| 666 |
|
|
if(w_u0LinkUp==1'b1) $display("Link Acquired"); else $display("Link Dropped");
|
| 667 |
|
|
if(w_u0ANDone==1'b1) begin
|
| 668 |
|
|
$display("Auto-nego completes");
|
| 669 |
|
|
$display("Link Speed %d Mbps",(w2_u0Speed==2'b10)?1000:100);
|
| 670 |
|
|
$display("Link Duplex %s ",w_u0Duplex?"Full":"Half");
|
| 671 |
|
|
end
|
| 672 |
|
|
end
|
| 673 |
|
|
|
| 674 |
|
|
reg [15:00] r16_LpAbility;
|
| 675 |
|
|
initial
|
| 676 |
|
|
begin
|
| 677 |
|
|
|
| 678 |
|
|
forever
|
| 679 |
|
|
begin
|
| 680 |
|
|
#1000;
|
| 681 |
|
|
u1WishboneMstr.tsk_Read(7'b00101_00,r16_LpAbility); //Enable SGMII Mode, Speed 1000Gb, Full Duplex
|
| 682 |
|
|
//$display("Partner Ability %x",r16_LpAbility);
|
| 683 |
|
|
end
|
| 684 |
|
|
end
|
| 685 |
|
|
|
| 686 |
|
|
endmodule
|
| 687 |
|
|
|
| 688 |
|
|
//TODO Test case Loopback
|
| 689 |
|
|
//TODO Test Auto Negotiation (Good)
|
| 690 |
|
|
//TODO Test Restart Auto Negotiation (Good)
|
| 691 |
|
|
//TODO Test case 1) Basic, Random size packets from 16 bytes to 10000 bytes
|
| 692 |
|
|
//TODO Test case 2) Carrier Extension, figure 35-6
|
| 693 |
|
|
//TODO Test case 3) Burst transmission, figure 35-7
|
| 694 |
|
|
//TODO Test case 4) Error Propagation with in aframe, figure 35-4
|
| 695 |
|
|
//TODO Test case 5) Error Propagation with carrier extension, figure 35-4
|
