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jefflieu |
//IP Functional Simulation Model
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//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:10:19:19:54:28:SJ cbx_simgen 2012:10:19:19:52:08:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 1991-2012 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// You may only use these simulation model output files for simulation
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// purposes and expressly not for synthesis or any other purposes (in which
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// event Altera disclaims all warranties of any kind).
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//synopsys translate_off
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//synthesis_resources = altera_pll 1
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`timescale 1 ps / 1 ps
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module mAltLvdsPll
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(
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locked,
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outclk_0,
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outclk_1,
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outclk_2,
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refclk,
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rst) /* synthesis synthesis_clearbox=1 */;
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output locked;
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output outclk_0;
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output outclk_1;
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output outclk_2;
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input refclk;
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input rst;
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wire wire_maltlvdspll_altera_pll_altera_pll_i_191_locked;
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wire [2:0] wire_maltlvdspll_altera_pll_altera_pll_i_191_outclk;
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altera_pll maltlvdspll_altera_pll_altera_pll_i_191
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(
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.fbclk(1'b0),
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.locked(wire_maltlvdspll_altera_pll_altera_pll_i_191_locked),
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.outclk(wire_maltlvdspll_altera_pll_altera_pll_i_191_outclk),
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.refclk(refclk),
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.rst(rst));
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defparam
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en0 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en1 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en10 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en11 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en12 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en13 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en14 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en15 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en16 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en17 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en2 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en3 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en4 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en5 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en6 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en7 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en8 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_bypass_en9 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div0 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div1 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div10 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div11 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div12 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div13 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div14 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div15 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div16 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div17 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div2 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div3 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div4 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div5 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div6 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div7 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div8 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_hi_div9 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div0 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div1 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div10 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div11 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div12 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div13 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div14 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div15 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div16 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div17 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div2 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div3 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div4 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div5 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div6 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div7 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div8 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_lo_div9 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en0 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en1 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en10 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en11 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en12 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en13 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en14 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en15 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en16 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en17 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en2 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en3 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en4 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en5 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en6 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en7 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en8 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_odd_div_duty_en9 = "false",
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst0 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst1 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst10 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst11 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst12 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst13 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst14 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst15 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst16 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst17 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst2 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst3 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst4 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst5 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst6 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst7 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst8 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_ph_mux_prst9 = 0,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst0 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst1 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst10 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst11 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst12 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst13 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst14 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst15 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst16 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst17 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst2 = 1,
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| 158 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst3 = 1,
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| 159 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst4 = 1,
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| 160 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst5 = 1,
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| 161 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst6 = 1,
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| 162 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst7 = 1,
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| 163 |
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst8 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.c_cnt_prst9 = 1,
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maltlvdspll_altera_pll_altera_pll_i_191.data_rate = 0,
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| 166 |
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maltlvdspll_altera_pll_altera_pll_i_191.deserialization_factor = 4,
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| 167 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle0 = 50,
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| 168 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle1 = 10,
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| 169 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle10 = 50,
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| 170 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle11 = 50,
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| 171 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle12 = 50,
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| 172 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle13 = 50,
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| 173 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle14 = 50,
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| 174 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle15 = 50,
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| 175 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle16 = 50,
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| 176 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle17 = 50,
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| 177 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle2 = 50,
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| 178 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle3 = 50,
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| 179 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle4 = 50,
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| 180 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle5 = 50,
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| 181 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle6 = 50,
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| 182 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle7 = 50,
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| 183 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle8 = 50,
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| 184 |
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maltlvdspll_altera_pll_altera_pll_i_191.duty_cycle9 = 50,
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| 185 |
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maltlvdspll_altera_pll_altera_pll_i_191.fractional_vco_multiplier = "false",
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| 186 |
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maltlvdspll_altera_pll_altera_pll_i_191.m_cnt_bypass_en = "false",
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| 187 |
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maltlvdspll_altera_pll_altera_pll_i_191.m_cnt_hi_div = 1,
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| 188 |
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maltlvdspll_altera_pll_altera_pll_i_191.m_cnt_lo_div = 1,
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| 189 |
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maltlvdspll_altera_pll_altera_pll_i_191.m_cnt_odd_div_duty_en = "false",
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| 190 |
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maltlvdspll_altera_pll_altera_pll_i_191.mimic_fbclk_type = "gclk",
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| 191 |
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maltlvdspll_altera_pll_altera_pll_i_191.n_cnt_bypass_en = "false",
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| 192 |
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maltlvdspll_altera_pll_altera_pll_i_191.n_cnt_hi_div = 1,
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| 193 |
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maltlvdspll_altera_pll_altera_pll_i_191.n_cnt_lo_div = 1,
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| 194 |
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maltlvdspll_altera_pll_altera_pll_i_191.n_cnt_odd_div_duty_en = "false",
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| 195 |
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maltlvdspll_altera_pll_altera_pll_i_191.number_of_clocks = 3,
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| 196 |
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maltlvdspll_altera_pll_altera_pll_i_191.operation_mode = "lvds",
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| 197 |
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maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency0 = "1250.0 MHz",
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| 198 |
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maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency1 = "125.0 MHz",
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| 199 |
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maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency10 = "0 MHz",
|
| 200 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency11 = "0 MHz",
|
| 201 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency12 = "0 MHz",
|
| 202 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency13 = "0 MHz",
|
| 203 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency14 = "0 MHz",
|
| 204 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency15 = "0 MHz",
|
| 205 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency16 = "0 MHz",
|
| 206 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency17 = "0 MHz",
|
| 207 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency2 = "125.0 MHz",
|
| 208 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency3 = "0 MHz",
|
| 209 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency4 = "0 MHz",
|
| 210 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency5 = "0 MHz",
|
| 211 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency6 = "0 MHz",
|
| 212 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency7 = "0 MHz",
|
| 213 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency8 = "0 MHz",
|
| 214 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.output_clock_frequency9 = "0 MHz",
|
| 215 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift0 = "400 ps",
|
| 216 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift1 = "6400 ps",
|
| 217 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift10 = "0 ps",
|
| 218 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift11 = "0 ps",
|
| 219 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift12 = "0 ps",
|
| 220 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift13 = "0 ps",
|
| 221 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift14 = "0 ps",
|
| 222 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift15 = "0 ps",
|
| 223 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift16 = "0 ps",
|
| 224 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift17 = "0 ps",
|
| 225 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift2 = "400 ps",
|
| 226 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift3 = "0 ps",
|
| 227 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift4 = "0 ps",
|
| 228 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift5 = "0 ps",
|
| 229 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift6 = "0 ps",
|
| 230 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift7 = "0 ps",
|
| 231 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift8 = "0 ps",
|
| 232 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.phase_shift9 = "0 ps",
|
| 233 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_auto_clk_sw_en = "false",
|
| 234 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_bwctrl = 0,
|
| 235 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_clk_loss_sw_en = "false",
|
| 236 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_clk_sw_dly = 0,
|
| 237 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_clkin_1_src = "clk_0",
|
| 238 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_cp_current = 0,
|
| 239 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_fbclk_mux_1 = "glb",
|
| 240 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_fbclk_mux_2 = "fb_1",
|
| 241 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_fractional_cout = 24,
|
| 242 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_fractional_division = 1,
|
| 243 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_m_cnt_in_src = "ph_mux_clk",
|
| 244 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_manu_clk_sw_en = "false",
|
| 245 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_output_clk_frequency = "0 MHz",
|
| 246 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_subtype = "General",
|
| 247 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_type = "General",
|
| 248 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.pll_vco_div = 1,
|
| 249 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.refclk1_frequency = "0 MHz",
|
| 250 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.reference_clock_frequency = "125.0 MHz",
|
| 251 |
|
|
maltlvdspll_altera_pll_altera_pll_i_191.sim_additional_refclk_cycles_to_lock = 0;
|
| 252 |
|
|
assign
|
| 253 |
|
|
locked = wire_maltlvdspll_altera_pll_altera_pll_i_191_locked,
|
| 254 |
|
|
outclk_0 = wire_maltlvdspll_altera_pll_altera_pll_i_191_outclk[0],
|
| 255 |
|
|
outclk_1 = wire_maltlvdspll_altera_pll_altera_pll_i_191_outclk[1],
|
| 256 |
|
|
outclk_2 = wire_maltlvdspll_altera_pll_altera_pll_i_191_outclk[2];
|
| 257 |
|
|
endmodule //mAltLvdsPll
|
| 258 |
|
|
//synopsys translate_on
|
| 259 |
|
|
//VALID FILE
|
