| 1 |
2 |
jdoin |
-----------------------------------------------------------------------------------------------------------------------
|
| 2 |
6 |
jdoin |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com
|
| 3 |
2 |
jdoin |
--
|
| 4 |
6 |
jdoin |
-- Create Date: 09:56:30 05/06/2016
|
| 5 |
2 |
jdoin |
-- Module Name: sha256_control - RTL
|
| 6 |
|
|
-- Project Name: sha256 hash engine
|
| 7 |
|
|
-- Target Devices: Spartan-6
|
| 8 |
|
|
-- Tool versions: ISE 14.7
|
| 9 |
|
|
-- Description:
|
| 10 |
|
|
--
|
| 11 |
|
|
-- This is the control path logic for the GV_SHA256 fast engine.
|
| 12 |
|
|
--
|
| 13 |
|
|
-- It is a fully synchronous design, with all signals synchronous to the rising edge of the system clock.
|
| 14 |
|
|
-- The sequencer state machine controls the hash datapath modules, generating addresses for the coefficients ROM, load/enable signals for the
|
| 15 |
|
|
-- message schedule, hash core and output registers circuit blocks, and control signals for the input padding logic.
|
| 16 |
|
|
--
|
| 17 |
|
|
-- The SHA256 hash core follows the FIPS-180-4 logic description for the SHA-256 algorithm, optimized as a single-cycle per iteration engine.
|
| 18 |
|
|
--
|
| 19 |
|
|
-- This implementation follows the implementation guidelines of the NIST Cryptographic Toolkit, and the NIST Approved Algorithms notes.
|
| 20 |
|
|
--
|
| 21 |
|
|
-- RELEVANT NIST PUBLICATIONS
|
| 22 |
|
|
-- Link to Document | Description
|
| 23 |
|
|
-- ------------------------------------------------------------------------------ | ---------------------------------------------------------
|
| 24 |
|
|
-- http://csrc.nist.gov/publications/fips/fips140-2/fips1402.pdf | SECURITY REQUIREMENTS FOR CRYPTOGRAPHIC MODULES
|
| 25 |
|
|
-- http://csrc.nist.gov/groups/ST/toolkit/index.html | NIST CRYPTOGRAPHIC TOOLKIT
|
| 26 |
|
|
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf | Secure Hash Standard (SHS) SHA-256
|
| 27 |
|
|
-- http://csrc.nist.gov/publications/fips/fips198-1/FIPS-198-1_final.pdf | The Keyed-Hash Message Authentication Code (HMAC)
|
| 28 |
|
|
-- http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf | SHA-256 verification test vectors
|
| 29 |
|
|
-- http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA2_Additional.pdf | Additional SHA-256 corner case verification test vectors
|
| 30 |
|
|
--
|
| 31 |
|
|
-- RELEVANT RFCs
|
| 32 |
|
|
-- Link to PDF document | Description
|
| 33 |
|
|
-- ------------------------------------------ | ---------------------------------------------------------
|
| 34 |
|
|
-- https://tools.ietf.org/pdf/rfc2104.pdf | RFC2104 - HMAC: Keyed-Hashing for Message Authentication
|
| 35 |
|
|
-- https://tools.ietf.org/pdf/rfc4231.pdf | RFC4231 - Identifiers and Test Vectors for HMAC-SHA-256
|
| 36 |
|
|
-- https://tools.ietf.org/pdf/rfc4868.pdf | RFC4868 - Using HMAC-SHA-256, HMAC-SHA-384, and HMAC-SHA-512 with IPsec
|
| 37 |
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 38 |
|
|
-- SHA256 ENGINE
|
| 39 |
|
|
-- =============
|
| 40 |
|
|
--
|
| 41 |
|
|
-- The setup of all circuit blocks is performed in a single extra clock cycle, besides the 64 steps needed to compute a hash block operation,
|
| 42 |
|
|
-- resulting in a 65-cycle per block hash computation processor. Heavy pipelining is implemented to suppress control path operations logic steps.
|
| 43 |
|
|
-- The engine is internally implemented as a 256-bit machine, with all combinational operations performed as a single-cycle operation on each
|
| 44 |
|
|
-- 64 steps of the hash algorithm. Wide transfers of 256-bit data are also performed as single-cycle operations.
|
| 45 |
|
|
--
|
| 46 |
|
|
-- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'ack_i' can be
|
| 47 |
|
|
-- used as a flow control input to hold the processor to wait for slower data.
|
| 48 |
|
|
--
|
| 49 |
|
|
-- A hash computation starts with a 'start_i' pulse that resets the processor. A pulse of the 'end_i' signal marks the last input data word. The
|
| 50 |
|
|
-- core will pad the last block according to the SHA256 rules, and present the results of the hash computation at the output registers, raising the
|
| 51 |
|
|
-- 'data_valid' signal to mark the end of the computation. The hash results are available at the 256-bit output port.
|
| 52 |
|
|
--
|
| 53 |
|
|
-- The following waveforms describe the detailed operation for message start, update and end, with internal signals and FSM states.
|
| 54 |
|
|
--
|
| 55 |
|
|
-- BEGIN BLOCK (1st block) - showing lookahead Wt and Kt
|
| 56 |
|
|
-- ======================
|
| 57 |
|
|
--
|
| 58 |
|
|
-- The hash operation starts with a 'start' sync pulse, which causes the RESET of the processor. The processor comes out of RESET only after 'start' is
|
| 59 |
|
|
-- released.
|
| 60 |
|
|
-- The DATA_INPUT state is signalled by the data request signal 'di_req' going HIGH. The processor will latch 16 words from the 'di' port, at every
|
| 61 |
|
|
-- rising edge of the system clock. At the end of the block input, the 'di_req' signal goes LOW.
|
| 62 |
|
|
-- The input data can be held by bringing the 'ack' input LOW. When the 'ack' input is held LOW, it includes a wait state in the whole processor, to
|
| 63 |
|
|
-- cope with slow inputs or to allow periodic fetches of input data from multiple data sources.
|
| 64 |
|
|
--
|
| 65 |
|
|
-- STATE |reset| data |wait | | process
|
| 66 |
|
|
-- __ |__ |__ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ |__ __ __
|
| 67 |
|
|
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
|
| 68 |
|
|
-- _____
|
| 69 |
|
|
-- start_i ______/ \_\_______________________________________________________________________________________________________________________... -- 'start_i' resets the processor and starts a new hash
|
| 70 |
|
|
--
|
| 71 |
|
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
| 72 |
|
|
-- __ _ _ _ _____________________________________________________________________________________________________
|
| 73 |
|
|
-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
|
| 74 |
|
|
-- ___________________________________________ _________________________________________________________
|
| 75 |
|
|
-- ack_i __________/____/ \_____/ \_____________... -- 'ack_i' can hold the core for slow data
|
| 76 |
|
|
-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
|
| 77 |
|
|
-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
| 78 |
|
|
-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
| 79 |
|
|
-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
|
| 80 |
|
|
-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
| 81 |
|
|
-- Wt_i@core __________\___\__W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_________________... -- msg scheduler lookahead output for Wt_i at core
|
| 82 |
|
|
-- ______________ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
| 83 |
|
|
-- Kt_i@core ______________/__K0_/__K1_/__K2_/__K3_/__K4_/__K5_/__K6_______/__K7_/__K8_/__K9_/_K10_/_K11_/_K12_/_K13_/_K14_/_K15_________________... -- Kt rom synchronous with scheduler for Kt_i at core
|
| 84 |
|
|
-- __ _ _ _
|
| 85 |
|
|
-- error_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' clears any error condition
|
| 86 |
|
|
-- __ _ _ _
|
| 87 |
|
|
-- do_valid_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' invalidates any previous results
|
| 88 |
|
|
--
|
| 89 |
|
|
--
|
| 90 |
|
|
-- UPDATE BLOCK (preload)
|
| 91 |
|
|
-- =====================
|
| 92 |
|
|
--
|
| 93 |
|
|
-- At the start of each block, the 'di_req' signal is raised to request new data.
|
| 94 |
|
|
--
|
| 95 |
|
|
-- STATE ... process |next | data |wait | | process
|
| 96 |
|
|
-- __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ __
|
| 97 |
|
|
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
|
| 98 |
|
|
--
|
| 99 |
|
|
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
| 100 |
|
|
-- _____________________________________________________________________________________________________
|
| 101 |
|
|
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
|
| 102 |
|
|
-- ___________________________________________________ _________________________________________________________
|
| 103 |
|
|
-- ack_i ________/__________/ \_____/ \_... -- 'ack_i' can hold the core for slow data
|
| 104 |
|
|
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
|
| 105 |
|
|
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
| 106 |
|
|
--
|
| 107 |
|
|
--
|
| 108 |
|
|
-- UPDATE BLOCK (delayed start)
|
| 109 |
|
|
-- ===========================
|
| 110 |
|
|
--
|
| 111 |
|
|
-- The data for the new block can be delayed, by keeping the 'ack' signal low until the data is present at the data input port.
|
| 112 |
|
|
--
|
| 113 |
|
|
-- STATE ..|next | data |wait | | process
|
| 114 |
|
|
-- __ __ __ __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __
|
| 115 |
|
|
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
|
| 116 |
|
|
--
|
| 117 |
|
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
| 118 |
|
|
-- _______ _ _ ___________________________________________________________________________________________________________
|
| 119 |
|
|
-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
|
| 120 |
|
|
-- __________________________________________________ _____________________________________________
|
| 121 |
|
|
-- ack_i ________________ _ _ ______/ \_____/ \_... -- 'ack_i' valid on rising edge of 'clk_i'
|
| 122 |
|
|
-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
|
| 123 |
|
|
-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\\\\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
| 124 |
|
|
--
|
| 125 |
|
|
--
|
| 126 |
|
|
-- END BLOCK (success)
|
| 127 |
|
|
-- ==================
|
| 128 |
|
|
--
|
| 129 |
|
|
-- At the end of the last block the signal 'end' must be raised for at least one clock cycle.
|
| 130 |
|
|
-- The 'bytes' input marks the number of valid bytes in the last word.
|
| 131 |
|
|
-- A PADDING state completes the last data block and a BLK_PROCESS finishes the hash computation.
|
| 132 |
|
|
-- The 'do_valid' remains HIGH until the next RESET.
|
| 133 |
|
|
--
|
| 134 |
|
|
-- STATE ..|next | data | padding | process |next | valid |reset| data
|
| 135 |
|
|
-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
|
| 136 |
|
|
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock
|
| 137 |
|
|
-- ______
|
| 138 |
|
|
-- start_i ____________________________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash
|
| 139 |
|
|
-- ______
|
| 140 |
|
|
-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
|
| 141 |
|
|
-- ___________________________________ __________
|
| 142 |
|
|
-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
|
| 143 |
|
|
-- ______________________________________ _________
|
| 144 |
|
|
-- ack_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'ack_i' can hold the core for slow data
|
| 145 |
|
|
-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
|
| 146 |
|
|
-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
| 147 |
|
|
-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
|
| 148 |
|
|
-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
|
| 149 |
|
|
-- _____ _____ _____ _____ _____ _____ _____ ____
|
| 150 |
|
|
-- bytes_i --------<__0__\__0__\__0__\__0__\__0__\__3__>-----------------------------------------------------------------------<__0__\__0_... -- bytes_i mark number of valid bytes in each word
|
| 151 |
|
|
--
|
| 152 |
|
|
-- error_o _______________________________________________________ _ _ ___________________ _ _ ___________________________________________... -- 'error_o' goes high on an invalid computation
|
| 153 |
|
|
-- ___________
|
| 154 |
|
|
-- do_valid_o _______________________________________________________ _ _ ___________________ _ _ ______________/ \________________... -- 'do_valid_o' goes high at the end of a computation
|
| 155 |
|
|
-- ___________
|
| 156 |
|
|
-- H0_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H0______\________________... -- H0 holds the bytes 0..3 of the output
|
| 157 |
|
|
-- ___________
|
| 158 |
|
|
-- H1_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H1______\________________... -- H1 holds the bytes 4..7 of the output
|
| 159 |
|
|
-- ___________
|
| 160 |
|
|
-- H2_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H2______\________________... -- H2 holds the bytes 8..11 of the output
|
| 161 |
|
|
-- ___________
|
| 162 |
|
|
-- H3_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H3______\________________... -- H3 holds the bytes 12..15 of the output
|
| 163 |
|
|
-- ___________
|
| 164 |
|
|
-- H4_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H4______\________________... -- H4 holds the bytes 16..19 of the output
|
| 165 |
|
|
-- ___________
|
| 166 |
|
|
-- H5_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H5______\________________... -- H5 holds the bytes 20..23 of the output
|
| 167 |
|
|
-- ___________
|
| 168 |
|
|
-- H6_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H6______\________________... -- H6 holds the bytes 24..27 of the output
|
| 169 |
|
|
-- ___________
|
| 170 |
|
|
-- H7_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H7______\________________... -- H7 holds the bytes 28..31 of the output
|
| 171 |
|
|
--
|
| 172 |
|
|
--
|
| 173 |
|
|
-- END BLOCK (full last block)
|
| 174 |
|
|
-- ==================
|
| 175 |
|
|
--
|
| 176 |
|
|
-- If the last block has exactly 16 full words, the controller inserts a dummy PADDING cycle, processes the input block, and inserts a
|
| 177 |
|
|
-- last PADDING block followed by a last BLK_PROCESS block.
|
| 178 |
|
|
--
|
| 179 |
|
|
-- STATE ... data |pad | process |next | pad | process |next | valid |reset| data
|
| 180 |
|
|
-- __ __ __ |__ |__ |__ |__ __ __ |__ |__ |__ __ |__ |__ __
|
| 181 |
|
|
-- clk_i \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock
|
| 182 |
|
|
-- ______
|
| 183 |
|
|
-- start_i ____________________________ _ _ ____________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash
|
| 184 |
|
|
-- _____
|
| 185 |
|
|
-- end_i ____________/ \_________ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
|
| 186 |
|
|
-- _________________ __________
|
| 187 |
|
|
-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
|
| 188 |
|
|
-- ____________________ _________
|
| 189 |
|
|
-- ack_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'ack_i' valid on rising edge of 'clk_i'
|
| 190 |
|
|
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
|
| 191 |
|
|
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
| 192 |
|
|
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
|
| 193 |
|
|
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
|
| 194 |
|
|
-- _____ _____ _____ _____ ____
|
| 195 |
|
|
-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word
|
| 196 |
|
|
-- ___________
|
| 197 |
|
|
-- do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/ \________________... -- 'do_valid_o' goes high at the end of a computation
|
| 198 |
|
|
--
|
| 199 |
|
|
--
|
| 200 |
|
|
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
|
| 201 |
6 |
jdoin |
--
|
| 202 |
|
|
-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
|
| 203 |
|
|
--
|
| 204 |
|
|
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
|
| 205 |
|
|
--
|
| 206 |
|
|
-- Copyright (C) 2016 Jonny Doin
|
| 207 |
|
|
-- -----------------------------
|
| 208 |
|
|
--
|
| 209 |
|
|
-- This source file may be used and distributed without restriction provided that this copyright statement is not
|
| 210 |
|
|
-- removed from the file and that any derivative work contains the original copyright notice and the associated
|
| 211 |
|
|
-- disclaimer.
|
| 212 |
|
|
--
|
| 213 |
|
|
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
|
| 214 |
|
|
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
|
| 215 |
|
|
-- (at your option) any later version.
|
| 216 |
|
|
--
|
| 217 |
|
|
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 218 |
|
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
|
| 219 |
|
|
-- details.
|
| 220 |
|
|
--
|
| 221 |
|
|
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
|
| 222 |
|
|
-- it from http://www.gnu.org/licenses/lgpl.txt
|
| 223 |
|
|
--
|
| 224 |
2 |
jdoin |
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
|
| 225 |
|
|
--
|
| 226 |
|
|
-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
|
| 227 |
|
|
-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification.
|
| 228 |
|
|
-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
|
| 229 |
|
|
-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed.
|
| 230 |
|
|
-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic.
|
| 231 |
|
|
-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
|
| 232 |
|
|
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
|
| 233 |
|
|
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
|
| 234 |
|
|
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
|
| 235 |
|
|
-- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'.
|
| 236 |
|
|
--
|
| 237 |
|
|
-----------------------------------------------------------------------------------------------------------------------
|
| 238 |
|
|
-- TODO
|
| 239 |
|
|
-- ====
|
| 240 |
|
|
--
|
| 241 |
|
|
--
|
| 242 |
|
|
-----------------------------------------------------------------------------------------------------------------------
|
| 243 |
|
|
library ieee;
|
| 244 |
|
|
use ieee.std_logic_1164.all;
|
| 245 |
|
|
use ieee.numeric_std.all;
|
| 246 |
|
|
|
| 247 |
|
|
entity sha256_control is
|
| 248 |
|
|
port (
|
| 249 |
|
|
-- inputs
|
| 250 |
|
|
clk_i : in std_logic := 'U'; -- system clock
|
| 251 |
|
|
ce_i : in std_logic := 'U'; -- core clock enable
|
| 252 |
|
|
start_i : in std_logic := 'U'; -- reset the processor and start a new hash
|
| 253 |
|
|
end_i : in std_logic := 'U'; -- marks end of last block data input
|
| 254 |
|
|
ack_i : in std_logic := 'U'; -- input word hold control
|
| 255 |
|
|
bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word
|
| 256 |
|
|
error_i : in std_logic := 'U'; -- datapath error input from other modules
|
| 257 |
|
|
-- output control signals
|
| 258 |
|
|
bitlen_o : out std_logic_vector (63 downto 0); -- message bit length
|
| 259 |
|
|
words_sel_o : out std_logic_vector (1 downto 0); -- bitlen insertion control
|
| 260 |
|
|
Kt_addr_o : out std_logic_vector (5 downto 0); -- address for the Kt coefficients ROM
|
| 261 |
|
|
sch_ld_o : out std_logic; -- load/recirculate words for message scheduler
|
| 262 |
|
|
core_ld_o : out std_logic; -- load all registers for hash core
|
| 263 |
|
|
oregs_ld_o : out std_logic; -- load output registers
|
| 264 |
|
|
sch_ce_o : out std_logic; -- clock enable for message scheduler logic block
|
| 265 |
|
|
core_ce_o : out std_logic; -- clock enable for hash core logic block
|
| 266 |
|
|
oregs_ce_o : out std_logic; -- clock enable for output regs logic block
|
| 267 |
|
|
bytes_ena_o : out std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block
|
| 268 |
|
|
one_insert_o : out std_logic; -- insert leading '1' in the padding
|
| 269 |
|
|
di_req_o : out std_logic; -- external data request by the 'di_i' port
|
| 270 |
|
|
data_valid_o : out std_logic; -- operation finished. output data is valid
|
| 271 |
|
|
error_o : out std_logic -- operation aborted. output data is not valid
|
| 272 |
|
|
);
|
| 273 |
|
|
end sha256_control;
|
| 274 |
|
|
|
| 275 |
|
|
architecture rtl of sha256_control is
|
| 276 |
|
|
--=============================================================================================
|
| 277 |
|
|
-- Type definitions
|
| 278 |
|
|
--=============================================================================================
|
| 279 |
|
|
-- controller states
|
| 280 |
|
|
type hash_toplevel_control is
|
| 281 |
|
|
( st_reset, -- core reset, initial state
|
| 282 |
|
|
st_sha_data_input, -- sha data input
|
| 283 |
|
|
st_sha_blk_process, -- sha block process
|
| 284 |
|
|
st_sha_blk_nxt, -- sha block next
|
| 285 |
|
|
st_sha_padding, -- sha padding
|
| 286 |
|
|
st_sha_data_valid, -- sha data valid
|
| 287 |
|
|
st_error -- fsm locks on error, exit only by reset
|
| 288 |
|
|
);
|
| 289 |
|
|
|
| 290 |
|
|
--=============================================================================================
|
| 291 |
|
|
-- Signals for state machine control
|
| 292 |
|
|
--=============================================================================================
|
| 293 |
|
|
signal hash_control_st_reg : hash_toplevel_control := st_reset;
|
| 294 |
|
|
signal hash_control_st_next : hash_toplevel_control := st_reset;
|
| 295 |
|
|
|
| 296 |
|
|
--=============================================================================================
|
| 297 |
|
|
-- Signals for internal operation
|
| 298 |
|
|
--=============================================================================================
|
| 299 |
|
|
-- combinational flags: message data input / padding control / block internal process selection
|
| 300 |
|
|
signal reset : std_logic;
|
| 301 |
|
|
signal sha_reset : std_logic;
|
| 302 |
|
|
signal sha_init : std_logic;
|
| 303 |
|
|
signal wait_run_ce : std_logic;
|
| 304 |
|
|
-- registered flags: last block, padding control and hmac processing
|
| 305 |
|
|
signal sha_last_blk_reg : std_logic;
|
| 306 |
|
|
signal sha_last_blk_next : std_logic;
|
| 307 |
|
|
signal padding_reg : std_logic;
|
| 308 |
|
|
signal padding_next : std_logic;
|
| 309 |
|
|
signal pad_one_reg : std_logic;
|
| 310 |
|
|
signal pad_one_next : std_logic;
|
| 311 |
|
|
signal bytes_error_reg : std_logic;
|
| 312 |
|
|
signal bytes_error_next : std_logic;
|
| 313 |
|
|
-- 64 bit message bit counter
|
| 314 |
|
|
signal msg_bit_cnt_reg : unsigned (63 downto 0);
|
| 315 |
|
|
signal msg_bit_cnt_next : unsigned (63 downto 0);
|
| 316 |
|
|
signal bits_to_add : unsigned (5 downto 0);
|
| 317 |
|
|
signal msg_bit_cnt_ce : std_logic;
|
| 318 |
|
|
-- sequencer state counter
|
| 319 |
|
|
signal st_cnt_reg : unsigned (6 downto 0);
|
| 320 |
|
|
signal st_cnt_next : unsigned (6 downto 0);
|
| 321 |
|
|
signal st_cnt_ce : std_logic;
|
| 322 |
|
|
signal st_cnt_clr : std_logic;
|
| 323 |
|
|
|
| 324 |
|
|
--=============================================================================================
|
| 325 |
|
|
-- Output Control Signals
|
| 326 |
|
|
--=============================================================================================
|
| 327 |
|
|
-- unregistered control signals
|
| 328 |
|
|
signal words_sel : std_logic_vector (1 downto 0); -- bitlen insertion control
|
| 329 |
|
|
signal sch_ld : std_logic; -- input data load into message scheduler control
|
| 330 |
|
|
signal core_ld : std_logic; -- hash core load data registers control
|
| 331 |
|
|
signal oregs_ld : std_logic; -- load initial value into output regs control
|
| 332 |
|
|
signal sch_ce : std_logic; -- clock enable for message scheduler logic block
|
| 333 |
|
|
signal core_ce : std_logic; -- clock enable for hash core logic block
|
| 334 |
|
|
signal oregs_ce : std_logic; -- clock enable for output regs logic block
|
| 335 |
|
|
signal bytes_ena : std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block
|
| 336 |
|
|
signal one_insert : std_logic; -- insert leading one in the padding
|
| 337 |
|
|
signal di_req : std_logic; -- data request
|
| 338 |
|
|
signal data_valid : std_logic; -- operation finished. output data is valid
|
| 339 |
|
|
signal core_error : std_logic; -- operation aborted. output data is not valid
|
| 340 |
|
|
signal out_error : std_logic; -- operation aborted. output data is not valid
|
| 341 |
|
|
|
| 342 |
|
|
begin
|
| 343 |
|
|
--=============================================================================================
|
| 344 |
|
|
-- REGISTER TRANSFER PROCESSES
|
| 345 |
|
|
--=============================================================================================
|
| 346 |
|
|
-- control fsm register transfer logic
|
| 347 |
|
|
control_fsm_proc: process (clk_i) is
|
| 348 |
|
|
begin
|
| 349 |
|
|
-- FSM state register: sync RESET on 'reset', and sync PRESET on error_i
|
| 350 |
|
|
if clk_i'event and clk_i = '1' then
|
| 351 |
|
|
if reset = '1' then
|
| 352 |
|
|
-- all registered values are reset on master clear
|
| 353 |
|
|
hash_control_st_reg <= st_reset;
|
| 354 |
|
|
elsif out_error = '1' then
|
| 355 |
|
|
hash_control_st_reg <= st_error;
|
| 356 |
|
|
elsif ce_i = '1' then
|
| 357 |
|
|
-- all registered values are held on master clock enable
|
| 358 |
|
|
hash_control_st_reg <= hash_control_st_next;
|
| 359 |
|
|
end if;
|
| 360 |
|
|
end if;
|
| 361 |
|
|
-- SHA256 registers, RESET on 'sha_init'
|
| 362 |
|
|
if clk_i'event and clk_i = '1' then
|
| 363 |
|
|
if sha_init = '1' then
|
| 364 |
|
|
-- all SHA256 registered values are reset on SHA master clear
|
| 365 |
|
|
sha_last_blk_reg <= '0';
|
| 366 |
|
|
padding_reg <= '0';
|
| 367 |
|
|
elsif ce_i = '1' then
|
| 368 |
|
|
-- all registered values are held on master clock enable
|
| 369 |
|
|
sha_last_blk_reg <= sha_last_blk_next;
|
| 370 |
|
|
padding_reg <= padding_next;
|
| 371 |
|
|
end if;
|
| 372 |
|
|
end if;
|
| 373 |
|
|
-- bytes_i error register: sync RESET on 'reset'
|
| 374 |
|
|
if clk_i'event and clk_i = '1' then
|
| 375 |
|
|
if reset = '1' then
|
| 376 |
|
|
-- all registered values are reset on master clear
|
| 377 |
|
|
bytes_error_reg <= '0';
|
| 378 |
|
|
else
|
| 379 |
|
|
-- all registered values are held on master clock enable
|
| 380 |
|
|
bytes_error_reg <= bytes_error_next;
|
| 381 |
|
|
end if;
|
| 382 |
|
|
end if;
|
| 383 |
|
|
end process control_fsm_proc;
|
| 384 |
|
|
|
| 385 |
|
|
-- bit counter register transfer logic
|
| 386 |
|
|
bit_counter_proc: process (clk_i) is
|
| 387 |
|
|
begin
|
| 388 |
|
|
-- bit counter
|
| 389 |
|
|
if clk_i'event and clk_i = '1' then
|
| 390 |
|
|
if sha_init = '1' then
|
| 391 |
|
|
msg_bit_cnt_reg <= (others => '0');
|
| 392 |
|
|
elsif ce_i = '1' and msg_bit_cnt_ce = '1' then
|
| 393 |
|
|
msg_bit_cnt_reg <= msg_bit_cnt_next;
|
| 394 |
|
|
end if;
|
| 395 |
|
|
end if;
|
| 396 |
|
|
end process bit_counter_proc;
|
| 397 |
|
|
|
| 398 |
|
|
-- state counter register transfer process
|
| 399 |
|
|
state_counter_proc: process (clk_i) is
|
| 400 |
|
|
begin
|
| 401 |
|
|
-- core state counter
|
| 402 |
|
|
if clk_i'event and clk_i = '1' then
|
| 403 |
|
|
if (sha_init = '1') or (st_cnt_clr = '1') then
|
| 404 |
|
|
st_cnt_reg <= (others => '0');
|
| 405 |
|
|
elsif (ce_i = '1') and (st_cnt_ce = '1') then
|
| 406 |
|
|
st_cnt_reg <= st_cnt_next;
|
| 407 |
|
|
end if;
|
| 408 |
|
|
end if;
|
| 409 |
|
|
end process state_counter_proc;
|
| 410 |
|
|
|
| 411 |
|
|
-- one-padding register transfer logic
|
| 412 |
|
|
pad_one_fsm_proc: process (clk_i) is
|
| 413 |
|
|
begin
|
| 414 |
|
|
if clk_i'event and clk_i = '1' then
|
| 415 |
|
|
if sha_init = '1' then
|
| 416 |
|
|
-- all registered values are reset on master clear
|
| 417 |
|
|
pad_one_reg <= '1';
|
| 418 |
|
|
elsif (ce_i = '1') and (sch_ce = '1') then
|
| 419 |
|
|
-- one-padding register is clocked synchronous with the message schedule
|
| 420 |
|
|
pad_one_reg <= pad_one_next;
|
| 421 |
|
|
end if;
|
| 422 |
|
|
end if;
|
| 423 |
|
|
end process pad_one_fsm_proc;
|
| 424 |
|
|
|
| 425 |
|
|
--=============================================================================================
|
| 426 |
|
|
-- COMBINATIONAL NEXT-STATE LOGIC
|
| 427 |
|
|
--=============================================================================================
|
| 428 |
|
|
-- State and control path combinational logic
|
| 429 |
|
|
-- The hash_control_st_reg state register controls the SHA256 algorithm.
|
| 430 |
|
|
control_combi_proc : process ( hash_control_st_reg, sha_last_blk_reg, padding_reg, wait_run_ce,
|
| 431 |
|
|
end_i, st_cnt_reg, sha_last_blk_next, one_insert, sha_reset ) is
|
| 432 |
|
|
begin
|
| 433 |
|
|
-- default logic that applies to all states at each fsm clock --
|
| 434 |
|
|
|
| 435 |
|
|
-- assign default values to all unchanging combinational outputs (avoid latches)
|
| 436 |
|
|
hash_control_st_next <= hash_control_st_reg;
|
| 437 |
|
|
sha_last_blk_next <= sha_last_blk_reg;
|
| 438 |
|
|
padding_next <= padding_reg;
|
| 439 |
|
|
-- handshaking
|
| 440 |
|
|
sha_init <= '0';
|
| 441 |
|
|
core_error <= '0';
|
| 442 |
|
|
words_sel <= b"00";
|
| 443 |
|
|
data_valid <= '0';
|
| 444 |
|
|
di_req <= '0'; -- data request only during data input
|
| 445 |
|
|
-- state counter
|
| 446 |
|
|
st_cnt_clr <= '0'; -- only clear the state counter at the beginning of each block
|
| 447 |
|
|
st_cnt_ce <= '0';
|
| 448 |
|
|
-- message scheduler
|
| 449 |
|
|
sch_ld <= '1'; -- enable pass-thru input through message schedule
|
| 450 |
|
|
sch_ce <= '0'; -- stop message schedule clock
|
| 451 |
|
|
-- hash core
|
| 452 |
|
|
core_ld <= '0'; -- enable internal hash core logic
|
| 453 |
|
|
core_ce <= '0'; -- core computation enabled only for data input and processing
|
| 454 |
|
|
-- output registers
|
| 455 |
|
|
oregs_ld <= '0'; -- defaults for accumulate blk hash
|
| 456 |
|
|
oregs_ce <= '0'; -- only register init values and end of computation
|
| 457 |
|
|
case hash_control_st_reg is
|
| 458 |
|
|
|
| 459 |
|
|
when st_reset => -- master reset: starts a new hash/hmac processing
|
| 460 |
|
|
-- moore outputs
|
| 461 |
|
|
sha_init <= '1'; -- reset SHA256 engine
|
| 462 |
|
|
oregs_ld <= '1'; -- load initial hash values
|
| 463 |
|
|
oregs_ce <= '1'; -- latch initial hash values into output registers
|
| 464 |
|
|
core_ld <= '1'; -- load initial value into core registers
|
| 465 |
|
|
core_ce <= '1'; -- latch initial value into core registers
|
| 466 |
|
|
st_cnt_clr <= '1'; -- reset state counter
|
| 467 |
|
|
-- next state
|
| 468 |
|
|
hash_control_st_next <= st_sha_data_input;
|
| 469 |
|
|
|
| 470 |
|
|
when st_sha_data_input => -- message data words are clocked into the processor
|
| 471 |
|
|
-- moore outputs
|
| 472 |
|
|
di_req <= '1'; -- request message data
|
| 473 |
|
|
sch_ce <= wait_run_ce; -- hold the message scheduler with data hold
|
| 474 |
|
|
st_cnt_ce <= wait_run_ce; -- hold state count with data hold
|
| 475 |
|
|
core_ce <= wait_run_ce; -- hold processing clock with data hold
|
| 476 |
|
|
-- next state
|
| 477 |
|
|
if wait_run_ce = '1' then
|
| 478 |
|
|
if end_i = '1' then
|
| 479 |
|
|
hash_control_st_next <= st_sha_padding; -- pad incomplete blocks
|
| 480 |
|
|
elsif st_cnt_reg = 15 then
|
| 481 |
|
|
hash_control_st_next <= st_sha_blk_process; -- process one more block
|
| 482 |
|
|
end if;
|
| 483 |
|
|
end if;
|
| 484 |
|
|
|
| 485 |
|
|
when st_sha_blk_process => -- internal block hash processing
|
| 486 |
|
|
-- moore outputs
|
| 487 |
|
|
st_cnt_ce <= '1'; -- enable state counter
|
| 488 |
|
|
sch_ld <= '0'; -- recirculate scheduler data
|
| 489 |
|
|
sch_ce <= '1'; -- enable message scheduler clock
|
| 490 |
|
|
core_ce <= '1'; -- enable processing clock
|
| 491 |
|
|
-- next state
|
| 492 |
|
|
if st_cnt_reg = 63 then
|
| 493 |
|
|
hash_control_st_next <= st_sha_blk_nxt;
|
| 494 |
|
|
end if;
|
| 495 |
|
|
|
| 496 |
|
|
when st_sha_blk_nxt => -- prepare for next block
|
| 497 |
|
|
-- moore outputs
|
| 498 |
|
|
st_cnt_clr <= '1'; -- reset state counter at the beginning of each block
|
| 499 |
|
|
sch_ld <= '0';
|
| 500 |
|
|
sch_ce <= '0'; -- stop the message schedule
|
| 501 |
|
|
core_ld <= '1'; -- load previous result value into core registers
|
| 502 |
|
|
core_ce <= '1'; -- latch result value into core registers
|
| 503 |
|
|
oregs_ce <= '1'; -- latch core result into regs accumulator
|
| 504 |
|
|
-- next state
|
| 505 |
|
|
if sha_last_blk_reg = '1' then
|
| 506 |
|
|
hash_control_st_next <= st_sha_data_valid; -- no hmac operation: publish data valid
|
| 507 |
|
|
elsif padding_reg = '1' then
|
| 508 |
|
|
hash_control_st_next <= st_sha_padding; -- additional padding block
|
| 509 |
|
|
else
|
| 510 |
|
|
hash_control_st_next <= st_sha_data_input; -- continue requesting input data
|
| 511 |
|
|
end if;
|
| 512 |
|
|
|
| 513 |
|
|
when st_sha_padding => -- padding of bits on the last message block
|
| 514 |
|
|
-- moore outputs
|
| 515 |
|
|
padding_next <= '1';
|
| 516 |
|
|
if st_cnt_reg = 16 then -- if word 16, data block was full: proceed to process this block
|
| 517 |
|
|
-- pause processing for this cycle
|
| 518 |
|
|
sch_ld <= '0';
|
| 519 |
|
|
sch_ce <= '0';
|
| 520 |
|
|
core_ce <= '0';
|
| 521 |
|
|
st_cnt_ce <= '0';
|
| 522 |
|
|
-- next state
|
| 523 |
|
|
hash_control_st_next <= st_sha_blk_process;
|
| 524 |
|
|
else -- incomplete block: pad words until data block completes
|
| 525 |
|
|
sch_ld <= '1'; -- load padded data into scheduler
|
| 526 |
|
|
sch_ce <= '1'; -- enable message scheduler clock
|
| 527 |
|
|
core_ce <= '1'; -- enable processing clock
|
| 528 |
|
|
st_cnt_ce <= '1'; -- enable state counter
|
| 529 |
|
|
if st_cnt_reg = 15 then -- pad up to word 15
|
| 530 |
|
|
if sha_last_blk_next = '1' then
|
| 531 |
|
|
words_sel <= b"10"; -- insert bitlen lo
|
| 532 |
|
|
end if;
|
| 533 |
|
|
-- next state
|
| 534 |
|
|
hash_control_st_next <= st_sha_blk_process;
|
| 535 |
|
|
elsif (one_insert = '0') and (st_cnt_reg = 14) then
|
| 536 |
|
|
words_sel <= b"01"; -- insert bitlen hi
|
| 537 |
|
|
sha_last_blk_next <= '1'; -- mark this as the last block
|
| 538 |
|
|
elsif st_cnt_reg = 13 then
|
| 539 |
|
|
sha_last_blk_next <= '1'; -- mark this as the last block
|
| 540 |
|
|
end if;
|
| 541 |
|
|
end if;
|
| 542 |
|
|
|
| 543 |
|
|
when st_sha_data_valid => -- process is finished, waiting for begin command
|
| 544 |
|
|
-- moore outputs
|
| 545 |
|
|
data_valid <= '1'; -- output results are valid
|
| 546 |
|
|
-- wait for core reset with 'reset'
|
| 547 |
|
|
|
| 548 |
|
|
when st_error => -- processing or input error: reset with 'reset' = 1
|
| 549 |
|
|
-- moore outputs
|
| 550 |
|
|
core_error <= '1';
|
| 551 |
|
|
st_cnt_clr <= '1'; -- clear state counter
|
| 552 |
|
|
-- wait for core reset with 'reset'
|
| 553 |
|
|
|
| 554 |
|
|
when others => -- internal state machine error
|
| 555 |
|
|
-- next state
|
| 556 |
|
|
hash_control_st_next <= st_error;
|
| 557 |
|
|
|
| 558 |
|
|
end case;
|
| 559 |
|
|
end process control_combi_proc;
|
| 560 |
|
|
|
| 561 |
|
|
|
| 562 |
|
|
--=============================================================================================
|
| 563 |
|
|
-- COMBINATIONAL CONTROL LOGIC
|
| 564 |
|
|
--=============================================================================================
|
| 565 |
|
|
|
| 566 |
|
|
-- controller RESET signal logic
|
| 567 |
|
|
sha_reset_combi_proc: sha_reset <= '1' when start_i = '1' else '0';
|
| 568 |
|
|
reset_combi_proc: reset <= '1' when sha_reset = '1' else '0';
|
| 569 |
|
|
|
| 570 |
|
|
-- pad-one flag register
|
| 571 |
|
|
pad_one_next_combi_proc: process (bytes_ena, sch_ld, pad_one_reg) is
|
| 572 |
|
|
begin
|
| 573 |
|
|
-- after one-insertion, clear the pad-one flag register
|
| 574 |
|
|
if (bytes_ena /= b"1111") and (sch_ld = '1') then
|
| 575 |
|
|
pad_one_next <= '0';
|
| 576 |
|
|
else
|
| 577 |
|
|
pad_one_next <= pad_one_reg;
|
| 578 |
|
|
end if;
|
| 579 |
|
|
end process pad_one_next_combi_proc;
|
| 580 |
|
|
|
| 581 |
|
|
-- padding byte lane selectors
|
| 582 |
|
|
bytes_ena_combi_proc: process (bytes_i, padding_next, di_req, one_insert, end_i) is
|
| 583 |
|
|
begin
|
| 584 |
|
|
if di_req = '1' and end_i /= '1' then
|
| 585 |
|
|
-- accept only full words before last word
|
| 586 |
|
|
bytes_ena <= b"1111";
|
| 587 |
|
|
elsif di_req = '1' and end_i = '1' then
|
| 588 |
|
|
-- user data: bytes controlled by 'bytes_i'
|
| 589 |
|
|
case bytes_i is
|
| 590 |
|
|
when b"01" => bytes_ena <= b"0001";
|
| 591 |
|
|
when b"10" => bytes_ena <= b"0011";
|
| 592 |
|
|
when b"11" => bytes_ena <= b"0111";
|
| 593 |
|
|
when others => bytes_ena <= b"1111";
|
| 594 |
|
|
end case;
|
| 595 |
|
|
else
|
| 596 |
|
|
-- no data input: force zero bits valid
|
| 597 |
|
|
bytes_ena <= b"0000";
|
| 598 |
|
|
end if;
|
| 599 |
|
|
end process bytes_ena_combi_proc;
|
| 600 |
|
|
|
| 601 |
|
|
-- bit counter next logic
|
| 602 |
|
|
msg_bit_cnt_next_combi_proc: process (bytes_ena, msg_bit_cnt_reg, bits_to_add) is
|
| 603 |
|
|
begin
|
| 604 |
|
|
case bytes_ena is
|
| 605 |
|
|
when b"0001" => bits_to_add <= to_unsigned( 8, 6);
|
| 606 |
|
|
when b"0011" => bits_to_add <= to_unsigned(16, 6);
|
| 607 |
|
|
when b"0111" => bits_to_add <= to_unsigned(24, 6);
|
| 608 |
|
|
when b"1111" => bits_to_add <= to_unsigned(32, 6);
|
| 609 |
|
|
when others => bits_to_add <= to_unsigned( 0, 6);
|
| 610 |
|
|
end case;
|
| 611 |
|
|
msg_bit_cnt_next <= msg_bit_cnt_reg + bits_to_add;
|
| 612 |
|
|
end process msg_bit_cnt_next_combi_proc;
|
| 613 |
|
|
|
| 614 |
|
|
-- data input wait/run: insert wait states during data input for 'ack_i' = '0'
|
| 615 |
|
|
wait_run_proc: wait_run_ce <= '1' when di_req = '1' and ack_i = '1' else '0';
|
| 616 |
|
|
|
| 617 |
|
|
-- padding one-insertion control
|
| 618 |
|
|
one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0';
|
| 619 |
|
|
|
| 620 |
|
|
-- bit counter clock enable
|
| 621 |
|
|
msg_bit_cnt_ce_proc : msg_bit_cnt_ce <= '1' when wait_run_ce = '1' else '0';
|
| 622 |
|
|
|
| 623 |
|
|
-- state counter next logic
|
| 624 |
|
|
st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1;
|
| 625 |
|
|
|
| 626 |
|
|
-- bytes_i error logic
|
| 627 |
|
|
bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and ack_i = '1' else bytes_error_reg;
|
| 628 |
|
|
|
| 629 |
|
|
-- error detection logic
|
| 630 |
|
|
out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' else '0';
|
| 631 |
|
|
|
| 632 |
|
|
--=============================================================================================
|
| 633 |
|
|
-- OUTPUT LOGIC PROCESSES
|
| 634 |
|
|
--=============================================================================================
|
| 635 |
|
|
|
| 636 |
|
|
bitlen_o_proc : bitlen_o <= std_logic_vector(msg_bit_cnt_reg);
|
| 637 |
|
|
bytes_ena_o_proc : bytes_ena_o <= bytes_ena;
|
| 638 |
|
|
one_insert_o_proc : one_insert_o <= one_insert;
|
| 639 |
|
|
words_sel_o_proc : words_sel_o <= words_sel;
|
| 640 |
|
|
sch_ce_o_proc : sch_ce_o <= sch_ce;
|
| 641 |
|
|
sch_ld_o_proc : sch_ld_o <= sch_ld;
|
| 642 |
|
|
core_ce_o_proc : core_ce_o <= core_ce;
|
| 643 |
|
|
core_ld_o_proc : core_ld_o <= core_ld;
|
| 644 |
|
|
oregs_ce_o_proc : oregs_ce_o <= oregs_ce;
|
| 645 |
|
|
oregs_ld_o_proc : oregs_ld_o <= oregs_ld;
|
| 646 |
|
|
Kt_addr_o_proc : Kt_addr_o <= std_logic_vector(st_cnt_reg(5 downto 0));
|
| 647 |
|
|
di_req_o_proc : di_req_o <= di_req;
|
| 648 |
|
|
data_valid_o_proc : data_valid_o <= data_valid;
|
| 649 |
|
|
error_o_proc : error_o <= out_error;
|
| 650 |
|
|
|
| 651 |
|
|
end rtl;
|
| 652 |
|
|
|
