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[/] [signed_integer_divider/] [trunk/] [divider_tb.v] - Blame information for rev 2

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module  divider_tb();
 
reg     clk=0,rst=0;
always #1 clk=~clk;
 
initial #10 rst=1;
 
/// driver
reg     [31:0]dividend=0,divisor=0;
reg     start=0;
wire    ready;
reg     state_driver=0;
always@(posedge clk)
        if(rst)begin
                case(state_driver)
                        0:begin
                                start<=1;
                                state_driver<=1;
                                dividend<=$random;
                                divisor<=$random;
                        end
                        1:if(ready)begin
                                start<=0;
                                state_driver<=0;
                        end
                endcase
        end
 
///
 
/// monitor
wire    [31:0]quotient,remainder;
reg     state_m=0;
 
always@(posedge clk)
        if(rst)begin
                case(state_m)
                        0:if(start)begin
                                if(dividend[31])$write("%6d     dividend=-%d",$time,(~dividend)+1);
                                else    $write("%6d     dividend=%d",$time,dividend);
                                if(divisor[31])$write(" divisor=-%d\n",(~divisor)+1);
                                else    $write("        divisor=%d\n",divisor);
                                state_m<=1;
                        end
                        1:if(ready)begin
                                state_m<=0;
                                if(quotient[31])$write("%6d     quotient=-%d",$time,(~quotient)+1);
                                else    $write("%6d     quotient=%d",$time,quotient);
                                if(remainder[31])$write("       remainder=-%d\n",(~remainder)+1);
                                else    $write("        remainder=%d\n",remainder);
                        end
                endcase
        end
///
 
 
/// score board
 
// test vector record
integer DD_FH,DR_FH,Q_FH,R_FH;
initial begin
        DD_FH=$fopen("F:/work/divider/test pattern/dividend.txt");
        DR_FH=$fopen("F:/work/divider/test pattern/divisor.txt");
        Q_FH=$fopen("F:/work/divider/test pattern/quotient.txt");
        R_FH=$fopen("F:/work/divider/test pattern/remainder.txt");
end
//
wire    sign_q,sign_r;
assign  sign_q=dividend[31]^divisor[31];
assign  sign_r=dividend[31];
 
reg     [62:0]PR=0;
wire    [31:0]DR;
assign  DR=divisor[31]?(~divisor)+1:divisor;
 
reg     [31:0]q_tb=0,r_tb=0;
integer i;
always@* begin
        PR={31'd0,dividend[31]?(~dividend)+1:dividend};
        for(i=31;i>=0;i=i-1)begin
                if(PR[62:31]>=DR)begin
                        PR[62:31]=PR[62:31]-DR;
                        if(i!=0)PR=PR<<1;
                        q_tb[i]=1;
                end
                else begin
                        q_tb[i]=0;
                        if(i!=0)PR=PR<<1;
                end
        end
        q_tb=sign_q?(~q_tb)+1:q_tb;
        r_tb=sign_r?(~PR[62:31])+1:PR[62:31];
        $fwrite(DD_FH,",0x%h",dividend);
        $fwrite(DR_FH,",0x%h",divisor);
        $fwrite(Q_FH,",0x%h",q_tb);
        $fwrite(R_FH,",0x%h",r_tb);
end
///
 
/// checker
always@(posedge clk)
        if(rst)begin
                if(ready)begin
                        if(quotient==q_tb)$write("quotient match");
                        else begin
                                $write("quotient mismatch");
                                if(q_tb[31])$write(" q_tb=-%d",(~q_tb)+1);
                                else $write(" q_tb=%d",q_tb);
                        end
                        if(remainder==r_tb)$write("     remainder match\n");
                        else begin
                                $write("        remainder mismatch");
                                if(r_tb[31])$write(" r_tb=-%d\n",(~r_tb)+1);
                                else $write(" r_tb=%d\n",r_tb);
                        end
                end
        end
///
 
 
///DUT
divider_dshift  divider_0(
clk,
rst,
dividend,
divisor,
start,
ready,
quotient,
remainder
);
 
 
///
endmodule

Line No.	Rev	Author	Line
1	2	m99	`module divider_tb();`
2
3			`reg clk=0,rst=0;`
4			`always #1 clk=~clk;`
5
6			`initial #10 rst=1;`
7
8			`/// driver`
9			`reg [31:0]dividend=0,divisor=0;`
10			`reg start=0;`
11			`wire ready;`
12			`reg state_driver=0;`
13			`always@(posedge clk)`
14			`if(rst)begin`
15			`case(state_driver)`
16			`0:begin`
17			`start<=1;`
18			`state_driver<=1;`
19			`dividend<=$random;`
20			`divisor<=$random;`
21			`end`
22			`1:if(ready)begin`
23			`start<=0;`
24			`state_driver<=0;`
25			`end`
26			`endcase`
27			`end`
28
29			`///`
30
31			`/// monitor`
32			`wire [31:0]quotient,remainder;`
33			`reg state_m=0;`
34
35			`always@(posedge clk)`
36			`if(rst)begin`
37			`case(state_m)`
38			`0:if(start)begin`
39			`if(dividend[31])$write("%6d dividend=-%d",$time,(~dividend)+1);`
40			`else $write("%6d dividend=%d",$time,dividend);`
41			`if(divisor[31])$write(" divisor=-%d\n",(~divisor)+1);`
42			`else $write(" divisor=%d\n",divisor);`
43			`state_m<=1;`
44			`end`
45			`1:if(ready)begin`
46			`state_m<=0;`
47			`if(quotient[31])$write("%6d quotient=-%d",$time,(~quotient)+1);`
48			`else $write("%6d quotient=%d",$time,quotient);`
49			`if(remainder[31])$write(" remainder=-%d\n",(~remainder)+1);`
50			`else $write(" remainder=%d\n",remainder);`
51			`end`
52			`endcase`
53			`end`
54			`///`
55
56
57			`/// score board`
58
59			`// test vector record`
60			`integer DD_FH,DR_FH,Q_FH,R_FH;`
61			`initial begin`
62			`DD_FH=$fopen("F:/work/divider/test pattern/dividend.txt");`
63			`DR_FH=$fopen("F:/work/divider/test pattern/divisor.txt");`
64			`Q_FH=$fopen("F:/work/divider/test pattern/quotient.txt");`
65			`R_FH=$fopen("F:/work/divider/test pattern/remainder.txt");`
66			`end`
67			`//`
68			`wire sign_q,sign_r;`
69			`assign sign_q=dividend[31]^divisor[31];`
70			`assign sign_r=dividend[31];`
71
72			`reg [62:0]PR=0;`
73			`wire [31:0]DR;`
74			`assign DR=divisor[31]?(~divisor)+1:divisor;`
75
76			`reg [31:0]q_tb=0,r_tb=0;`
77			`integer i;`
78			`always@* begin`
79			`PR={31'd0,dividend[31]?(~dividend)+1:dividend};`
80			`for(i=31;i>=0;i=i-1)begin`
81			`if(PR[62:31]>=DR)begin`
82			`PR[62:31]=PR[62:31]-DR;`
83			`if(i!=0)PR=PR<<1;`
84			`q_tb[i]=1;`
85			`end`
86			`else begin`
87			`q_tb[i]=0;`
88			`if(i!=0)PR=PR<<1;`
89			`end`
90			`end`
91			`q_tb=sign_q?(~q_tb)+1:q_tb;`
92			`r_tb=sign_r?(~PR[62:31])+1:PR[62:31];`
93			`$fwrite(DD_FH,",0x%h",dividend);`
94			`$fwrite(DR_FH,",0x%h",divisor);`
95			`$fwrite(Q_FH,",0x%h",q_tb);`
96			`$fwrite(R_FH,",0x%h",r_tb);`
97			`end`
98			`///`
99
100			`/// checker`
101			`always@(posedge clk)`
102			`if(rst)begin`
103			`if(ready)begin`
104			`if(quotient==q_tb)$write("quotient match");`
105			`else begin`
106			`$write("quotient mismatch");`
107			`if(q_tb[31])$write(" q_tb=-%d",(~q_tb)+1);`
108			`else $write(" q_tb=%d",q_tb);`
109			`end`
110			`if(remainder==r_tb)$write(" remainder match\n");`
111			`else begin`
112			`$write(" remainder mismatch");`
113			`if(r_tb[31])$write(" r_tb=-%d\n",(~r_tb)+1);`
114			`else $write(" r_tb=%d\n",r_tb);`
115			`end`
116			`end`
117			`end`
118			`///`
119
120
121			`///DUT`
122			`divider_dshift divider_0(`
123			`clk,`
124			`rst,`
125			`dividend,`
126			`divisor,`
127			`start,`
128			`ready,`
129			`quotient,`
130			`remainder`
131			`);`
132
133
134			`///`
135			`endmodule`

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[/] [signed_integer_divider/] [trunk/] [divider_tb.v] - Blame information for rev 2