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[/] [signed_unsigned_multiplier_and_divider/] [trunk/] [bin2bcd.vhd] - Blame information for rev 2

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1 2 zpekic 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    18:02:11 03/25/2018
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-- Design Name:
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-- Module Name:    bin2bcd - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity bin2bcd is
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    Port ( reset : in  STD_LOGIC;               -- Initialize when high, note that it will drive ready low
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           clk : in  STD_LOGIC;                 -- Drives the FSM
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           start : in  STD_LOGIC;               -- Keep high for at least 1 clock cycle to start conversion
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           bin : in  STD_LOGIC_VECTOR (15 downto 0);             -- 16-bit unsigned binary input value
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                          ready : out  STD_LOGIC;               -- pulse high when conversion is done
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           bcd : buffer STD_LOGIC_VECTOR (23 downto 0);  -- 6 BCD digits output
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                          debug: out STD_LOGIC_VECTOR(3 downto 0));              -- debug port, leave open
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end bin2bcd;
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architecture Behavioral of bin2bcd is
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component bcddigitadder is
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    Port ( ci : in  STD_LOGIC;
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           a : in  STD_LOGIC_VECTOR (3 downto 0);
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           b : in  STD_LOGIC_VECTOR (3 downto 0);
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           y : out  STD_LOGIC_VECTOR (3 downto 0);
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           cout : out  STD_LOGIC);
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end component;
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type state is (st_reset, st_readytostart, st_loadbinval, st_checkzero,
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                                        st_delay, st_update,
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                                        st_shiftdown, st_done);
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type rom24x16 is array(0 to 15) of std_logic_vector(23 downto 0);
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constant bcd_lookup: rom24x16 := (
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        1 =>    X"000002",
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        2 =>    X"000004",
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        3 =>    X"000008",
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        4 =>    X"000016",
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        5 =>    X"000032",
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        6 =>    X"000064",
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        7 =>    X"000128",
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        8 =>    X"000256",
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        9 =>    X"000512",
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        10 =>   X"001024",
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        11 => X"002048",
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        12 =>   X"004096",
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        13 =>   X"008192",
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        14 =>   X"016384",
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        15 =>   X"032768"
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);
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signal state_current, state_next: state;
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signal power: integer range 0 to 15;     -- index to bcd lookup table (2^power in bcd format)
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signal zero: std_logic;
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signal ripple_carry: std_logic_vector(6 downto 0);
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signal bin_val: std_logic_vector(15 downto 0);
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signal power_val: std_logic_vector(23 downto 0);
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signal bcd_plus_power: std_logic_vector(23 downto 0);
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begin
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debug <= std_logic_vector(to_unsigned(power, 4));
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power_val <= bcd_lookup(power);
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ripple_carry(0) <= '0';
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zero <= '1' when bin_val = X"0000" else '0';
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gen_digit_adders: for i in 0 to 5 generate -- six output digits
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        digadd: bcddigitadder port map
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                                (
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                                        ci => ripple_carry(i),
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                                        a => bcd(3 + 4 * i downto 4 * i),
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                                        b => power_val(3 + 4 * i downto 4 * i),
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                                        y => bcd_plus_power(3 + 4 * i downto 4 * i),
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                                        cout => ripple_carry(i + 1)
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                                );
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end generate;
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-- FSM
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drive: process(reset, clk, state_next)
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begin
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        if (reset = '1') then
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                state_current <= st_reset;
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        else
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                if (rising_edge(clk)) then
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                        state_current <= state_next;
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                end if;
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        end if;
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end process;
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execute: process(clk, state_current)
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begin
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        if (rising_edge(clk)) then
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                case state_current is
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                        when st_reset =>
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                                ready <= '0';
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                        when st_readytostart =>
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                                ready <= '1';
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                                power <= 0;
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                        when st_loadbinval =>
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                                ready <= '0';
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                                bin_val <= bin;
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                                bcd <= X"000000";
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                        when st_checkzero =>
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                        when st_delay =>
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                        when st_update =>
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                                bcd <= bcd_plus_power;
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                        when st_shiftdown =>
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                                bin_val <= '0' & bin_val(15 downto 1);
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                                power <= power + 1;
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                        when st_done =>
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                                ready <= '1';
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                        when others =>
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                                null;
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                end case;
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        end if;
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end process;
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sequence: process(state_current, zero, bin_val)
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begin
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        case state_current is
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                when st_reset =>
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                        state_next <= st_readytostart;
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                when st_readytostart =>
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                        if (start = '1') then
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                                state_next <= st_loadbinval;
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                        else
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                                state_next <= st_readytostart; -- continue waiting for start
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                        end if;
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                when st_loadbinval =>
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                        state_next <= st_checkzero;
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                when st_checkzero =>
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                        if (zero = '1') then
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                                state_next <= st_done;
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                        else
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                                if (bin_val(0) = '1') then
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                                        state_next <= st_delay;
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                                else
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                                        state_next <= st_shiftdown;
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                                end if;
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                        end if;
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                when st_delay =>
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                        state_next <= st_update;
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                when st_update =>
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                        state_next <= st_shiftdown;
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                when st_shiftdown =>
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                        state_next <= st_checkzero;
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                when st_done =>
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                        state_next <= st_readytostart;
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                when others =>
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                        null;
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        end case;
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end process;
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end Behavioral;
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