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zpekic |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 03/04/2018 05:14:44 PM
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-- Design Name:
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-- Module Name: rom32x32 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.sys_primegen_package.all;
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entity rom32x32 is
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Port ( nCS : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR (4 downto 0);
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d : out STD_LOGIC_VECTOR (31 downto 0));
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end rom32x32;
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architecture Behavioral of rom32x32 is
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--signal a_int: std_logic_vector(7 downto 0);
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--signal d_int: std_logic_vector(31 downto 0);
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type rom is array(0 to 31) of std_logic_vector(31 downto 0);
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constant ucode: rom := (
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X"2A" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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1 => -- WaitForStart: i = 0; IF (buttonstart != 1) THEN GOTO WaitForStart
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X"00" & muxa_m & muxb_m & alu_sbc & ci_one & i_load & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_repeat & cond_buttonstart,
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2 => -- n = Arg0;
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X"00" & muxa_arg0 & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_load & mode_umul & muldiv_nop & uart_nop & if_next_else_next & cond_true,
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3 => -- LoopN: IF (n > Arg1) THEN GOTO WaitForStart
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X"01" & muxa_n & muxb_arg1 & alu_sbc & ci_one & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_goto_else_next & cond_alugreaterthan,
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4 => -- IF (n < 2) THEN GOTO NextN
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X"10" & muxa_n & muxb_two & alu_sbc & ci_one & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_goto_else_next & cond_alulessthan,
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5 => -- IF (n < 4) THEN GOTO FoundPrime
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X"0F" & muxa_n & muxb_four & alu_sbc & ci_one & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_goto_else_next & cond_alulessthan,
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6 => -- m = 1;
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X"01" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_load & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_next & cond_true,
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7 => -- NextM: m = m + 1;
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X"00" & muxa_zero & muxb_m & alu_adc & ci_one & i_nop & m_load & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_next & cond_true,
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8 => -- kick off division n / m, note that n must be presented as dividend, divisor is hard coded to m. Keep the start signal on until unit responds with not ready
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X"00" & muxa_n & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_udiv & muldiv_start & uart_nop & if_next_else_repeat & cond_muldivnotready,
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9 => -- wait for division to finish
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X"00" & muxa_n & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_udiv & muldiv_nop & uart_nop & if_next_else_repeat & cond_muldivready,
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10 => -- IF (n // m = 0) THEN GOTO NextN
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X"10" & muxa_zero & muxb_modulo & alu_sbc & ci_one & i_nop & m_nop & n_nop & mode_udiv & muldiv_nop & uart_nop & if_goto_else_next & cond_aluzero,
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11 => -- kick off multiplication m * m, note that m must be presented as factor0, factor1 is hard coded to m. Keep the start signal on until unit responds with not ready
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X"00" & muxa_m & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_start & uart_nop & if_next_else_repeat & cond_muldivnotready,
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12 => -- wait for multiplication to finish
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X"00" & muxa_m & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_repeat & cond_muldivready,
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13 => -- IF (m * m >= n) THEN GOTO FoundPrime
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X"0F" & muxa_prod & muxb_n & alu_sbc & ci_one & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_goto_else_next & cond_alugreaterorequal,
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14 => -- GOTO NextM
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X"07" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_goto_else_next & cond_true,
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15 => -- FoundPrime: GOSUB PrintIandN
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X"11" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_gosub_else_repeat & cond_ibcdready,
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16 => -- NextN: n = n + 1; IF (n != 0) GOTO LoopN else GOTO Start
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X"03" & muxa_zero & muxb_n & alu_adc & ci_one & i_nop & m_nop & n_load & mode_umul & muldiv_nop & uart_nop & if_goto_else_start & cond_alunotzero,
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17 => -- PrintIandN: i = i + 1
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X"00" & muxa_zero & muxb_i & alu_adc & ci_one & i_load & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_next & cond_true,
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18 => -- PRINT "<CR>"
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X"0D" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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19 => -- PRINT ASC(BCD(i) >> 12 AND 0x000F)
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X"00" & muxa_ibcd & muxb_const & alu_asc3 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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20 => -- PRINT ASC(BCD(i) >> 8 AND 0x000F)
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X"00" & muxa_ibcd & muxb_const & alu_asc2 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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21 => -- PRINT ASC(BCD(i) >> 4 AND 0x000F)
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X"00" & muxa_ibcd & muxb_const & alu_asc1 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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22 => -- PRINT ASC(BCD(i) >> 0 AND 0x000F)
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X"00" & muxa_ibcd & muxb_const & alu_asc0 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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23 => -- PRINT " "
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X"20" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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24 => -- Wait for BCD(n) ready
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X"00" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_repeat & cond_nbcdready,
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25 => -- PRINT ASC(BCD(n) >> 0 AND 0x000F)
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X"00" & muxa_nbcdh & muxb_const & alu_asc0 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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26 => -- PRINT ASC(BCD(n) >> 12 AND 0x000F)
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X"00" & muxa_nbcdl & muxb_const & alu_asc3 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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27 => -- PRINT ASC(BCD(n) >> 8 AND 0x000F)
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X"00" & muxa_nbcdl & muxb_const & alu_asc2 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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28 => -- PRINT ASC(BCD(n) >> 4 AND 0x000F)
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X"00" & muxa_nbcdl & muxb_const & alu_asc1 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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29 => -- PRINT ASC(BCD(n) >> 0 AND 0x000F)
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X"00" & muxa_nbcdl & muxb_const & alu_asc0 & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_send & if_next_else_repeat & cond_uartready,
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30 => -- RETURN
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X"00" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_return_else_next & cond_true,
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------------------------
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others => -- HALT
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X"00" & muxa_zero & muxb_const & alu_adc & ci_zero & i_nop & m_nop & n_nop & mode_umul & muldiv_nop & uart_nop & if_next_else_repeat & cond_false
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);
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begin
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d <= ucode(to_integer(unsigned(a))) when (nCS = '0') else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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end Behavioral;
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