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martin |
--
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-- This file is part of JOP, the Java Optimized Processor
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--
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-- Copyright (C) 2007,2008, Christof Pitter
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- 150407: first working version with records
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-- 170407: produce number of registers depending on the cpu_cnt
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-- 110507: * arbiter that can be used with prefered number of masters
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-- * full functional arbiter with two masters
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-- * short modelsim test with 3 masters carried out
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-- 190607: Problem found: Both CPU1 and CPU2 start to read cache line!!!
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-- 030707: Several bugs are fixed now. CMP with 3 running masters functions!
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-- 150108: Quasi Round Robin Arbiter -- added sync signal to arbiter
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-- 160108: First tests running with new Round Robin Arbiter
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-- 250408: Renaming of this_state to mode, follow_state to next_mode, reg_in to reg_out
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-- 240708: added data_reg for each CPU in arbiter
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-- 070808: removed combinatorial loop (pipelined bug)
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-- 210808: - reg_in_rd_data(i) also gets loaded when rdy_cnt = 3 using pipelined access
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-- - arb_in(i).rd_data gets mem_in.rd_data when rdy_cnt 3 using pipelined access
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-- Functioning: See description of SIES08 paper
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.sc_pack.all;
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use work.sc_arbiter_pack.all;
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use work.jop_types.all;
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entity arbiter is
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generic(
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addr_bits : integer;
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cpu_cnt : integer); -- number of masters for the arbiter
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port (
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clk, reset : in std_logic;
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arb_out : in arb_out_type(0 to cpu_cnt-1);
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arb_in : out arb_in_type(0 to cpu_cnt-1);
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mem_out : out sc_out_type;
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mem_in : in sc_in_type
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);
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end arbiter;
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architecture rtl of arbiter is
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-- stores the signals in a register of each master
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type reg_type is record
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rd : std_logic;
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wr : std_logic;
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wr_data : std_logic_vector(31 downto 0);
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address : std_logic_vector(addr_bits-1 downto 0);
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end record;
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type reg_out_type is array (0 to cpu_cnt-1) of reg_type;
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signal reg_out : reg_out_type;
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-- register to CPU for rd_data
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type reg_in_type is array (0 to cpu_cnt-1) of std_logic_vector(31 downto 0);
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signal reg_in_rd_data : reg_in_type;
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-- one fsm for each CPU
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type state_type is (idle, read, write, waitingR, sendR,
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waitingW, sendW);
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type state_array is array (0 to cpu_cnt-1) of state_type;
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signal state : state_array;
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signal next_state : state_array;
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-- one fsm for each serve
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type serve_type is (idl, servR, servW);
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type serve_array is array (0 to cpu_cnt-1) of serve_type;
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signal mode : serve_array;
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signal next_mode : serve_array;
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-- arbiter
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type set_type is array (0 to cpu_cnt-1) of std_logic_vector(1 downto 0);
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signal set : set_type;
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type pipelined_type is array (0 to cpu_cnt-1) of std_logic;
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signal pipelined : pipelined_type;
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signal next_pipelined : pipelined_type;
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-- counter
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signal counter : integer;
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type slot_type is array (0 to cpu_cnt-1) of std_logic;
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signal slot : slot_type; -- defines which CPU is on turn
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begin
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-- Generates the input register and saves incoming data for each master
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gen_register: for i in 0 to cpu_cnt-1 generate
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process(clk, reset)
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begin
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if reset = '1' then
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reg_out(i).rd <= '0';
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reg_out(i).wr <= '0';
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reg_out(i).wr_data <= (others => '0');
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reg_out(i).address <= (others => '0');
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elsif rising_edge(clk) then
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if arb_out(i).rd = '1' or arb_out(i).wr = '1' then
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reg_out(i).rd <= arb_out(i).rd;
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reg_out(i).wr <= arb_out(i).wr;
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reg_out(i).address <= arb_out(i).address;
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reg_out(i).wr_data <= arb_out(i).wr_data;
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end if;
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end if;
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end process;
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end generate;
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-- Generate Counter
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process(clk, reset)
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begin
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if reset = '1' then
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counter <= 0;
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elsif rising_edge(clk) then
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counter <= counter + 1;
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for i in 0 to cpu_cnt-1 loop
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if next_mode(i) = servR or next_mode(i) = servW then
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if mem_in.rdy_cnt = 1 and arb_out(i).rd = '0' then
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if counter = cpu_cnt-1 then
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counter <= 0;
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else
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counter <= counter+1;
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end if;
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exit;
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else
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counter <= counter;
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exit;
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end if;
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elsif counter = cpu_cnt-1 then
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counter <= 0;
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end if;
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end loop;
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end if;
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end process;
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-- The slot is assigned depending on the counter
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process(counter)
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begin
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for j in 0 to cpu_cnt-1 loop
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if j = counter then
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slot(j) <= '1';
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else
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slot(j) <= '0';
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end if;
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end loop;
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end process;
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-- Generates next state of the FSM for each master
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gen_next_state: for i in 0 to cpu_cnt-1 generate
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process(state, mode, slot, mem_in, arb_out, pipelined)
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begin
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next_state(i) <= state(i);
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case state(i) is
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when idle =>
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next_pipelined(i) <= '0';
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-- is CPU allowed to access
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if (slot(i) = '1') then
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-- pipelined read access
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if (mode(i) = servR) and (mem_in.rdy_cnt = 1) and (arb_out(i).rd = '1') then
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next_state(i) <= read;
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next_pipelined(i) <= '1';
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elsif (mode(i) = servR) and (mem_in.rdy_cnt = 0) then
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if arb_out(i).rd = '1' then
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next_state(i) <= read;
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elsif arb_out(i).wr = '1' then
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next_state(i) <= write;
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end if;
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elsif (mode(i) = servW) and (mem_in.rdy_cnt = 0) then
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if arb_out(i).rd = '1' then
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next_state(i) <= read;
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elsif arb_out(i).wr = '1' then
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next_state(i) <= write;
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end if;
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elsif (mode(i) = idl) and (mem_in.rdy_cnt = 0) then
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if arb_out(i).rd = '1' then
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next_state(i) <= read;
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elsif arb_out(i).wr = '1' then
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next_state(i) <= write;
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end if;
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-- all other kinds (can that happen at all?)
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else
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if arb_out(i).rd = '1' then
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next_state(i) <= waitingR;
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elsif arb_out(i).wr = '1' then
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next_state(i) <= waitingW;
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end if;
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end if;
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-- CPU is not allowed to access
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else
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if arb_out(i).rd = '1' then
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next_state(i) <= waitingR;
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elsif arb_out(i).wr = '1' then
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next_state(i) <= waitingW;
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end if;
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end if;
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when read =>
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next_state(i) <= idle;
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next_pipelined(i) <= '0';
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if pipelined(i) = '1' then
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next_pipelined(i) <= '1';
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end if;
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when write =>
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next_state(i) <= idle;
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next_pipelined(i) <= '0';
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when waitingR =>
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next_pipelined(i) <= '0';
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if ((mem_in.rdy_cnt = 0) and (slot(i) = '1')) then
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next_state(i) <= sendR;
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else
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next_state(i) <= waitingR;
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end if;
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when sendR =>
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next_state(i) <= idle;
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next_pipelined(i) <= '0';
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when waitingW =>
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next_pipelined(i) <= '0';
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if ((mem_in.rdy_cnt = 0) and (slot(i) = '1')) then
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next_state(i) <= sendW;
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else
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next_state(i) <= waitingW;
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end if;
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when sendW =>
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next_state(i) <= idle;
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next_pipelined(i) <= '0';
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end case;
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end process;
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end generate;
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-- Generates the FSM state for each master
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gen_state: for i in 0 to cpu_cnt-1 generate
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process (clk, reset)
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begin
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if (reset = '1') then
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state(i) <= idle;
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pipelined(i) <= '0';
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elsif (rising_edge(clk)) then
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state(i) <= next_state(i);
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pipelined(i) <= next_pipelined(i);
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end if;
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end process;
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end generate;
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-- The arbiter output
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process (arb_out, reg_out, next_state)
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begin
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mem_out.rd <= '0';
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mem_out.wr <= '0';
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mem_out.address <= (others => '0');
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mem_out.wr_data <= (others => '0');
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mem_out.atomic <= '0';
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for i in 0 to cpu_cnt-1 loop
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set(i) <= "00";
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case next_state(i) is
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when idle =>
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when read =>
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set(i) <= "01";
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mem_out.rd <= arb_out(i).rd;
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mem_out.address <= arb_out(i).address;
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when write =>
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set(i) <= "10";
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mem_out.wr <= arb_out(i).wr;
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mem_out.address <= arb_out(i).address;
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mem_out.wr_data <= arb_out(i).wr_data;
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when waitingR =>
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when sendR =>
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set(i) <= "01";
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mem_out.rd <= reg_out(i).rd;
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mem_out.address <= reg_out(i).address;
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when waitingW =>
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when sendW =>
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set(i) <= "10";
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mem_out.wr <= reg_out(i).wr;
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mem_out.address <= reg_out(i).address;
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mem_out.wr_data <= reg_out(i).wr_data;
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end case;
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end loop;
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end process;
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-- generation of next_mode
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gen_serve: for i in 0 to cpu_cnt-1 generate
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process(mem_in, set, mode)
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begin
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case mode(i) is
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when idl =>
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next_mode(i) <= idl;
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if set(i) = "01" then
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next_mode(i) <= servR;
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elsif set(i) = "10" then
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next_mode(i) <= servW;
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end if;
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when servR =>
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next_mode(i) <= servR;
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if mem_in.rdy_cnt = 0 and set(i) = "00" then
|
| 350 |
|
|
next_mode(i) <= idl;
|
| 351 |
|
|
end if;
|
| 352 |
|
|
when servW =>
|
| 353 |
|
|
next_mode(i) <= servW;
|
| 354 |
|
|
if mem_in.rdy_cnt = 0 and set(i) = "00" then
|
| 355 |
|
|
next_mode(i) <= idl;
|
| 356 |
|
|
end if;
|
| 357 |
|
|
end case;
|
| 358 |
|
|
end process;
|
| 359 |
|
|
end generate;
|
| 360 |
|
|
|
| 361 |
|
|
gen_serve2: for i in 0 to cpu_cnt-1 generate
|
| 362 |
|
|
process (clk, reset)
|
| 363 |
|
|
begin
|
| 364 |
|
|
if (reset = '1') then
|
| 365 |
|
|
mode(i) <= idl;
|
| 366 |
|
|
elsif (rising_edge(clk)) then
|
| 367 |
|
|
mode(i) <= next_mode(i);
|
| 368 |
|
|
end if;
|
| 369 |
|
|
end process;
|
| 370 |
|
|
end generate;
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
-- Registers rd_data for each CPU
|
| 375 |
|
|
gen_reg_in: for i in 0 to cpu_cnt-1 generate
|
| 376 |
|
|
process(clk, reset)
|
| 377 |
|
|
begin
|
| 378 |
|
|
if reset = '1' then
|
| 379 |
|
|
reg_in_rd_data(i) <= (others => '0');
|
| 380 |
|
|
elsif rising_edge(clk) then
|
| 381 |
|
|
if mode(i) = servR then
|
| 382 |
|
|
if mem_in.rdy_cnt = 0 then
|
| 383 |
|
|
reg_in_rd_data(i) <= mem_in.rd_data;
|
| 384 |
|
|
|
| 385 |
|
|
-- added mem_in.rdy_cnt = 3.
|
| 386 |
|
|
-- More correct would be: ((mem_in.rdy_cnt = ram_cnt) or (mem_in.rdy_cnt = 3))
|
| 387 |
|
|
elsif ((( mem_in.rdy_cnt = 2 ) or ( mem_in.rdy_cnt = 3 )) and (next_pipelined(i) = '1')) then
|
| 388 |
|
|
reg_in_rd_data(i) <= mem_in.rd_data;
|
| 389 |
|
|
end if;
|
| 390 |
|
|
end if;
|
| 391 |
|
|
end if;
|
| 392 |
|
|
end process;
|
| 393 |
|
|
end generate;
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
-- Generates rdy_cnt and rd_data for all CPUs
|
| 398 |
|
|
gen_rdy_cnt: for i in 0 to cpu_cnt-1 generate
|
| 399 |
|
|
process (mem_in, state, mode, reg_in_rd_data, next_pipelined)
|
| 400 |
|
|
begin
|
| 401 |
|
|
|
| 402 |
|
|
arb_in(i).rd_data <= reg_in_rd_data(i);
|
| 403 |
|
|
arb_in(i).rdy_cnt <= mem_in.rdy_cnt;
|
| 404 |
|
|
|
| 405 |
|
|
case state(i) is
|
| 406 |
|
|
when idle =>
|
| 407 |
|
|
if (mode(i) = idl) then
|
| 408 |
|
|
arb_in(i).rdy_cnt <= "00";
|
| 409 |
|
|
elsif (mode(i) = servR) and (mem_in.rdy_cnt = 0) then
|
| 410 |
|
|
arb_in(i).rd_data <= mem_in.rd_data;
|
| 411 |
|
|
end if;
|
| 412 |
|
|
|
| 413 |
|
|
when read =>
|
| 414 |
|
|
if (mode(i) = servR) then
|
| 415 |
|
|
if (mem_in.rdy_cnt = 0) then
|
| 416 |
|
|
arb_in(i).rd_data <= mem_in.rd_data;
|
| 417 |
|
|
-- added mem_in.rdy_cnt = 3
|
| 418 |
|
|
elsif ((( mem_in.rdy_cnt = 2 ) or ( mem_in.rdy_cnt = 3 )) and (next_pipelined(i) = '1')) then
|
| 419 |
|
|
arb_in(i).rd_data <= mem_in.rd_data;
|
| 420 |
|
|
end if;
|
| 421 |
|
|
end if;
|
| 422 |
|
|
|
| 423 |
|
|
when write =>
|
| 424 |
|
|
|
| 425 |
|
|
when waitingR =>
|
| 426 |
|
|
arb_in(i).rdy_cnt <= "11";
|
| 427 |
|
|
if mode(i) = servR then
|
| 428 |
|
|
arb_in(i).rd_data <= mem_in.rd_data;
|
| 429 |
|
|
end if;
|
| 430 |
|
|
|
| 431 |
|
|
when sendR =>
|
| 432 |
|
|
|
| 433 |
|
|
when waitingW =>
|
| 434 |
|
|
arb_in(i).rdy_cnt <= "11";
|
| 435 |
|
|
|
| 436 |
|
|
when sendW =>
|
| 437 |
|
|
|
| 438 |
|
|
end case;
|
| 439 |
|
|
end process;
|
| 440 |
|
|
end generate;
|
| 441 |
|
|
|
| 442 |
|
|
end rtl;
|
