Subversion Repositories simpcon

--

--

--  This file is a part of JOP, the Java Optimized Processor

--

--  Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)

--

--  This program is free software: you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation, either version 3 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

--

--

--      scio_test_top.vhd

--

--      The top level to test SimpCon IO devices.

--      Do the address decoding here for the various slaves.

--      

--      Author: Martin Schoeberl        martin@jopdesign.com

--

--

--      2005-11-30      first version with two simple test slaves

--

--

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.jop_types.all;

entity scio is

generic (addr_bits : integer);

port (

        clk             : in std_logic;

        reset   : in std_logic;

-- SimpCon interface

        address         : in std_logic_vector(addr_bits-1 downto 0);

        wr_data         : in std_logic_vector(31 downto 0);

        rd, wr          : in std_logic;

        rd_data         : out std_logic_vector(31 downto 0);

        rdy_cnt         : out unsigned(1 downto 0)

);

end scio;

architecture rtl of scio is

        constant SLAVE_CNT : integer := 4;

        -- SLAVE_CNT <= 2**DECODE_BITS

        constant DECODE_BITS : integer := 2;

        -- number of bits that can be used inside the slave

        constant SLAVE_ADDR_BITS : integer := 4;

        type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;

        signal sc_rd, sc_wr             : slave_bit;

        type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0);

        signal sc_dout                  : slave_dout;

        type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);

        signal sc_rdy_cnt               : slave_rdy_cnt;

        signal sel, sel_reg             : integer range 0 to 2**DECODE_BITS-1;

begin

        assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";

        sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));

        -- What happens when sel_reg > SLAVE_CNT-1??

        rd_data <= sc_dout(sel_reg);

        rdy_cnt <= sc_rdy_cnt(sel_reg);

        --

        -- Connect SLAVE_CNT simple test slaves

        --

        gsl: for i in 0 to SLAVE_CNT-1 generate

                sc_rd(i) <= rd when i=sel else '0';

                sc_wr(i) <= wr when i=sel else '0';

                scsl: entity work.sc_test_slave

                        generic map (

                                -- shall we use less address bits inside the slaves?

                                addr_bits => SLAVE_ADDR_BITS

                        )

                        port map (

                                clk => clk,

                                reset => reset,

                                address => address(SLAVE_ADDR_BITS-1 downto 0),

                                wr_data => wr_data,

                                rd => sc_rd(i),

                                wr => sc_wr(i),

                                rd_data => sc_dout(i),

                                rdy_cnt => sc_rdy_cnt(i)

                );

        end generate;

        --

        --      Register read mux selector

        --

        process(clk, reset)

        begin

                if (reset='1') then

                        sel_reg <= 0;

                elsif rising_edge(clk) then

                        if rd='1' then

                                sel_reg <= sel;

                        end if;

                end if;

        end process;

end rtl;