Subversion Repositories simple_fm_receiver

-- $Id: fulladder.vhdl,v 1.3 2005-03-04 08:06:19 arif_endro Exp $

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-- Title       : Full Adder component

-- Project     : FM Receiver

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-- File        : fulladder.vhdl

-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>

-- Created     : 2004/12/01

-- Last update : 

-- Simulators  : 

-- Synthesizers: 

-- Target      : 

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-- Description : Simple one bit adder with carry

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-- Copyright (C) 2004 Arif Endro Nugroho

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-- 

--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION

-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT

-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE

-- ASSOCIATED DISCLAIMER.

-- 

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-- 

--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR

-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO

-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;

-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR

-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- 

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is

   port (

     addend   : in   bit;

     augend   : in   bit;

     carry_in : in   bit;

     sum      : out  bit;

     carry    : out  bit

     );

end fulladder;

architecture data_flow of fulladder is

begin

     sum    <= ((addend xor augend) xor carry_in);

     carry  <= ((addend and augend) or (carry_in and (addend or augend)));

end data_flow;