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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [adv_debug_sys/] [01_adv_debug_sys.yaml] - Blame information for rev 10

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SOCM_CORE
name: Advanced Debug System
description: Advanced Debug System
id: adv_debug_sys,ads_3
license: LGPL
licensefile:
author:
authormail:
vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
toplevel: adbg_top
 
interfaces:
 
 
 
  :jtag: SOCM_IFC
    name: jtag_tap
    dir: 1
    id: jtag_tap,1
    ports:
      :tck_i: SOCM_PORT
        len: 1
        defn: tck
      :tdi_i: SOCM_PORT
        len: 1
        defn: tdi
      :tdo_o: SOCM_PORT
        len: 1
        defn: tdo
      :rst_i: SOCM_PORT
        len: 1
        defn: rst
 
      :shift_dr_i: SOCM_PORT
        len: 1
        defn: shift
      :pause_dr_i: SOCM_PORT
        len: 1
        defn: pause
      :update_dr_i: SOCM_PORT
        len: 1
        defn: update
      :capture_dr_i: SOCM_PORT
        len: 1
        defn: capture
      :debug_select_i: SOCM_PORT
        len: 1
        defn: select
 
 
 
 
  :wb_ifc: SOCM_IFC
    name: wishbone_ma
    dir: 1
    id: wishbone_ma,b3
    ports:
      :wb_clk_i: SOCM_PORT
        len: 1
        defn: clk
      :wb_rst_i: SOCM_PORT
        len: 1
        defn: rst
      :wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :wb_dat_i: SOCM_PORT
        defn: dat_o
        len:  32
      :wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :wb_cab_o: SOCM_PORT
        defn: cab
        len:  1
      :wb_err_i: SOCM_PORT
        defn: err
        len:  1
      :wb_cti_o: SOCM_PORT
        defn: cti
        len:  3
      :wb_bte_o: SOCM_PORT
        defn: bte
        len:  2
 
  :cpu0_dbg_clk: SOCM_IFC
    name: clk
    dir: 1
    id: clk,1
    ports:
      :cpu0_clk_i: SOCM_PORT
        len: 1
        defn: clk
 
  :cpu0_dbg_rst: SOCM_IFC
    name: rst
    dir: 0
    id: rst,1
    ports:
      :cpu0_rst_o: SOCM_PORT
        len: 1
        defn: rst
 
  :cpu0_dbg: SOCM_IFC
    name: debug
    dir: 0
    id: debug,1
    ports:
      :cpu0_addr_o: SOCM_PORT
        len: 32
        defn: dbg_adr
      :cpu0_data_o: SOCM_PORT
        len: 32
        defn: dbg_dat_o
      :cpu0_data_i: SOCM_PORT
        len: 32
        defn: dbg_dat_i
      :cpu0_bp_i: SOCM_PORT
        len: 1
        defn: dbg_bpo
      :cpu0_stall_o: SOCM_PORT
        defn: dbg_stall
        len: 1
      :cpu0_stb_o: SOCM_PORT
        len: 1
        defn: dbg_stb
      :cpu0_we_o: SOCM_PORT
        len: 1
        defn: dbg_we
      :cpu0_ack_i: SOCM_PORT
        len: 1
        defn: dbg_ack
 
#     :dbg_ewt_i: SOCM_PORT
#       len: 1
#       defn: dbg_ewt
#     :dbg_lss_o: SOCM_PORT
#       len: 4
#       defn: dbg_lss
#     :dbg_is_o: SOCM_PORT
#       len: 2
#       defn: dbg_iso
#     :dbg_wp_o: SOCM_PORT
#       len: 11
#       defn: dbg_wpo
 
 
hdlfiles:
  :adbg_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_top.v
 
  :adbg_crc32: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_crc32.v
  :adbg_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_defines.v
  :adbg_jsp_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_jsp_biu.v
  :adbg_jsp_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_jsp_module.v
  :adbg_or1k_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_biu.v
  :adbg_or1k_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_defines.v
  :adbg_or1k_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_module.v
  :adbg_or1k_status_reg: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_status_reg.v
  :adbg_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_top.v
  :adbg_wb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_biu.v
  :adbg_wb_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_defines.v
  :adbg_wb_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_module.v
  :bytefifo: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/bytefifo.v
  :syncflow: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/syncflop.v
  :syncreg: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/syncreg.v
 

Line No.	Rev	Author	Line
1	7	feddischso	`SOCM_CORE`
2	10	feddischso	`name: Advanced Debug System`
3	7	feddischso	`description: Advanced Debug System`
4	10	feddischso	`id: adv_debug_sys,ads_3`
5	7	feddischso	`license: LGPL`
6			`licensefile:`
7			`author:`
8			`authormail:`
9			`vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl`
10			`toplevel: adbg_top`
11
12			`interfaces:`
13
14
15
16			`:jtag: SOCM_IFC`
17			`name: jtag_tap`
18			`dir: 1`
19	10	feddischso	`id: jtag_tap,1`
20	7	feddischso	`ports:`
21			`:tck_i: SOCM_PORT`
22			`len: 1`
23			`defn: tck`
24			`:tdi_i: SOCM_PORT`
25			`len: 1`
26			`defn: tdi`
27			`:tdo_o: SOCM_PORT`
28			`len: 1`
29			`defn: tdo`
30			`:rst_i: SOCM_PORT`
31			`len: 1`
32			`defn: rst`
33
34			`:shift_dr_i: SOCM_PORT`
35			`len: 1`
36			`defn: shift`
37			`:pause_dr_i: SOCM_PORT`
38			`len: 1`
39			`defn: pause`
40			`:update_dr_i: SOCM_PORT`
41			`len: 1`
42			`defn: update`
43			`:capture_dr_i: SOCM_PORT`
44			`len: 1`
45			`defn: capture`
46			`:debug_select_i: SOCM_PORT`
47			`len: 1`
48			`defn: select`
49
50
51
52
53			`:wb_ifc: SOCM_IFC`
54			`name: wishbone_ma`
55			`dir: 1`
56	10	feddischso	`id: wishbone_ma,b3`
57	7	feddischso	`ports:`
58			`:wb_clk_i: SOCM_PORT`
59			`len: 1`
60			`defn: clk`
61			`:wb_rst_i: SOCM_PORT`
62			`len: 1`
63			`defn: rst`
64			`:wb_adr_o: SOCM_PORT`
65			`defn: adr`
66			`len: 32`
67			`:wb_dat_o: SOCM_PORT`
68			`defn: dat_i`
69			`len: 32`
70			`:wb_dat_i: SOCM_PORT`
71			`defn: dat_o`
72			`len: 32`
73			`:wb_cyc_o: SOCM_PORT`
74			`defn: cyc`
75			`len: 1`
76			`:wb_stb_o: SOCM_PORT`
77			`defn: stb`
78			`len: 1`
79			`:wb_sel_o: SOCM_PORT`
80			`defn: sel`
81			`len: 4`
82			`:wb_we_o: SOCM_PORT`
83			`defn: we`
84			`len: 1`
85			`:wb_ack_i: SOCM_PORT`
86			`defn: ack`
87			`len: 1`
88			`:wb_cab_o: SOCM_PORT`
89			`defn: cab`
90			`len: 1`
91			`:wb_err_i: SOCM_PORT`
92			`defn: err`
93			`len: 1`
94			`:wb_cti_o: SOCM_PORT`
95			`defn: cti`
96			`len: 3`
97			`:wb_bte_o: SOCM_PORT`
98			`defn: bte`
99			`len: 2`
100
101			`:cpu0_dbg_clk: SOCM_IFC`
102			`name: clk`
103			`dir: 1`
104	10	feddischso	`id: clk,1`
105	7	feddischso	`ports:`
106			`:cpu0_clk_i: SOCM_PORT`
107			`len: 1`
108			`defn: clk`
109
110			`:cpu0_dbg_rst: SOCM_IFC`
111			`name: rst`
112			`dir: 0`
113	10	feddischso	`id: rst,1`
114	7	feddischso	`ports:`
115			`:cpu0_rst_o: SOCM_PORT`
116			`len: 1`
117			`defn: rst`
118
119			`:cpu0_dbg: SOCM_IFC`
120			`name: debug`
121			`dir: 0`
122	10	feddischso	`id: debug,1`
123	7	feddischso	`ports:`
124			`:cpu0_addr_o: SOCM_PORT`
125			`len: 32`
126			`defn: dbg_adr`
127			`:cpu0_data_o: SOCM_PORT`
128			`len: 32`
129			`defn: dbg_dat_o`
130			`:cpu0_data_i: SOCM_PORT`
131			`len: 32`
132			`defn: dbg_dat_i`
133			`:cpu0_bp_i: SOCM_PORT`
134			`len: 1`
135			`defn: dbg_bpo`
136			`:cpu0_stall_o: SOCM_PORT`
137			`defn: dbg_stall`
138			`len: 1`
139			`:cpu0_stb_o: SOCM_PORT`
140			`len: 1`
141			`defn: dbg_stb`
142			`:cpu0_we_o: SOCM_PORT`
143			`len: 1`
144			`defn: dbg_we`
145			`:cpu0_ack_i: SOCM_PORT`
146			`len: 1`
147			`defn: dbg_ack`
148
149			`# :dbg_ewt_i: SOCM_PORT`
150			`# len: 1`
151			`# defn: dbg_ewt`
152			`# :dbg_lss_o: SOCM_PORT`
153			`# len: 4`
154			`# defn: dbg_lss`
155			`# :dbg_is_o: SOCM_PORT`
156			`# len: 2`
157			`# defn: dbg_iso`
158			`# :dbg_wp_o: SOCM_PORT`
159			`# len: 11`
160			`# defn: dbg_wpo`
161
162
163			`hdlfiles:`
164			`:adbg_top: SOCM_HDL_FILE`
165			`use_syn: true`
166			`use_sim: true`
167			`type: verilog`
168			`path: rtl/verilog/adbg_top.v`
169
170			`:adbg_crc32: SOCM_HDL_FILE`
171			`use_syn: true`
172			`use_sim: true`
173			`type: verilog`
174			`path: rtl/verilog/adbg_crc32.v`
175			`:adbg_defines: SOCM_HDL_FILE`
176			`use_syn: true`
177			`use_sim: true`
178			`type: verilog`
179			`path: rtl/verilog/adbg_defines.v`
180			`:adbg_jsp_biu: SOCM_HDL_FILE`
181			`use_syn: true`
182			`use_sim: true`
183			`type: verilog`
184			`path: rtl/verilog/adbg_jsp_biu.v`
185			`:adbg_jsp_module: SOCM_HDL_FILE`
186			`use_syn: true`
187			`use_sim: true`
188			`type: verilog`
189			`path: rtl/verilog/adbg_jsp_module.v`
190			`:adbg_or1k_biu: SOCM_HDL_FILE`
191			`use_syn: true`
192			`use_sim: true`
193			`type: verilog`
194			`path: rtl/verilog/adbg_or1k_biu.v`
195			`:adbg_or1k_defines: SOCM_HDL_FILE`
196			`use_syn: true`
197			`use_sim: true`
198			`type: verilog`
199			`path: rtl/verilog/adbg_or1k_defines.v`
200			`:adbg_or1k_module: SOCM_HDL_FILE`
201			`use_syn: true`
202			`use_sim: true`
203			`type: verilog`
204			`path: rtl/verilog/adbg_or1k_module.v`
205			`:adbg_or1k_status_reg: SOCM_HDL_FILE`
206			`use_syn: true`
207			`use_sim: true`
208			`type: verilog`
209			`path: rtl/verilog/adbg_or1k_status_reg.v`
210			`:adbg_top: SOCM_HDL_FILE`
211			`use_syn: true`
212			`use_sim: true`
213			`type: verilog`
214			`path: rtl/verilog/adbg_top.v`
215			`:adbg_wb_biu: SOCM_HDL_FILE`
216			`use_syn: true`
217			`use_sim: true`
218			`type: verilog`
219			`path: rtl/verilog/adbg_wb_biu.v`
220			`:adbg_wb_defines: SOCM_HDL_FILE`
221			`use_syn: true`
222			`use_sim: true`
223			`type: verilog`
224			`path: rtl/verilog/adbg_wb_defines.v`
225			`:adbg_wb_module: SOCM_HDL_FILE`
226			`use_syn: true`
227			`use_sim: true`
228			`type: verilog`
229			`path: rtl/verilog/adbg_wb_module.v`
230			`:bytefifo: SOCM_HDL_FILE`
231			`use_syn: true`
232			`use_sim: true`
233			`type: verilog`
234			`path: rtl/verilog/bytefifo.v`
235			`:syncflow: SOCM_HDL_FILE`
236			`use_syn: true`
237			`use_sim: true`
238			`type: verilog`
239			`path: rtl/verilog/syncflop.v`
240			`:syncreg: SOCM_HDL_FILE`
241			`use_syn: true`
242			`use_sim: true`
243			`type: verilog`
244			`path: rtl/verilog/syncreg.v`
245

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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [adv_debug_sys/] [01_adv_debug_sys.yaml] - Blame information for rev 10