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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [wb_connect/] [wb_connect.yaml] - Blame information for rev 10

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SOCM_CORE
name: wb_connect
description: A block to connect RISC and peripheral controllers together
id: wb_connect,1
license: LGPL
licensefile:
author: Damjan Lampret
authormail: lampret@opencores.org
toplevel: minsoc_tc_top
interfaces:
 
 
  :clk: SOCM_IFC
    name: clk
    dir: 1
    id: clk,1
    ports:
      :wb_clk_i: SOCM_PORT
        len: 1
        defn: clk
 
  :rst: SOCM_IFC
    name: rst
    dir: 1
    id: rst,1
    ports:
      :wb_rst_i: SOCM_PORT
        len: 1
        defn: rst
 
 
 
  :i0: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i0_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i0_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i0_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i0_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i0_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i0_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i0_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i0_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i0_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i0_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i1: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i1_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i1_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i1_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i1_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i1_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i1_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i1_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i1_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i1_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i1_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i2: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i2_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i2_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i2_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i2_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i2_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i2_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i2_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i2_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i2_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i2_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i3: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i3_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i3_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i3_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i3_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i3_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i3_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i3_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i3_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i3_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i3_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i4: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i4_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i4_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i4_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i4_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i4_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i4_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i4_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i4_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i4_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i4_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i5: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i5_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i5_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i5_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i5_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i5_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i5_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i5_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i5_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i5_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i5_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i6: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i6_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i6_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i6_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i6_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i6_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i6_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i6_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i6_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i6_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i6_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i7: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i7_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i7_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i7_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i7_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i7_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i7_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i7_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i7_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i7_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i7_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :t0: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t0_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t0_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t0_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t0_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t0_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t0_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t0_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t0_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t0_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t0_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t1: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t1_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t1_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t1_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t1_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t1_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t1_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t1_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t1_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t1_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t1_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t2: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t2_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t2_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t2_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t2_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t2_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t2_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t2_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t2_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t2_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t2_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t3: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t3_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t3_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t3_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t3_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t3_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t3_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t3_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t3_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t3_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t3_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t4: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t4_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t4_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t4_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t4_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t4_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t4_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t4_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t4_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t4_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t4_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t5: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t5_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t5_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t5_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t5_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t5_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t5_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t5_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t5_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t5_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t5_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t6: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t6_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t6_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t6_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t6_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t6_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t6_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t6_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t6_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t6_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t6_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t7: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t7_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t7_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t7_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t7_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t7_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t7_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t7_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t7_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t7_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t7_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t8: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t8_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t8_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t8_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t8_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t8_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t8_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t8_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t8_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t8_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t8_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t8_wb_err_i: SOCM_PORT
        defn: err
        len:  1
 
 
 
 
hdlfiles:
  :minsoc_tc_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: minsoc_tc_top.v

Line No.	Rev	Author	Line
1	5	feddischso	`SOCM_CORE`
2			`name: wb_connect`
3			`description: A block to connect RISC and peripheral controllers together`
4	10	feddischso	`id: wb_connect,1`
5	5	feddischso	`license: LGPL`
6			`licensefile:`
7			`author: Damjan Lampret`
8			`authormail: lampret@opencores.org`
9			`toplevel: minsoc_tc_top`
10			`interfaces:`
11	7	feddischso
12
13			`:clk: SOCM_IFC`
14			`name: clk`
15			`dir: 1`
16	10	feddischso	`id: clk,1`
17	7	feddischso	`ports:`
18			`:wb_clk_i: SOCM_PORT`
19			`len: 1`
20			`defn: clk`
21
22			`:rst: SOCM_IFC`
23			`name: rst`
24			`dir: 1`
25	10	feddischso	`id: rst,1`
26	7	feddischso	`ports:`
27			`:wb_rst_i: SOCM_PORT`
28			`len: 1`
29			`defn: rst`
30
31
32
33	5	feddischso	`:i0: SOCM_IFC`
34			`name: wishbone_ma`
35	7	feddischso	`dir: 0`
36	10	feddischso	`id: wishbone_ma,b3`
37	5	feddischso	`ports:`
38	7	feddischso	`:i0_wb_clk_o: SOCM_PORT`
39			`defn: clk`
40			`len: 1`
41			`:i0_wb_rst_o: SOCM_PORT`
42			`defn: rst`
43			`len: 1`
44	5	feddischso	`:i0_wb_cyc_i: SOCM_PORT`
45			`defn: cyc`
46			`len: 1`
47			`:i0_wb_stb_i: SOCM_PORT`
48			`defn: stb`
49			`len: 1`
50			`:i0_wb_adr_i: SOCM_PORT`
51			`defn: adr`
52			`len: 32`
53			`:i0_wb_sel_i: SOCM_PORT`
54			`defn: sel`
55	7	feddischso	`len: 4`
56	5	feddischso	`:i0_wb_we_i: SOCM_PORT`
57			`defn: we`
58			`len: 1`
59			`:i0_wb_dat_i: SOCM_PORT`
60			`defn: dat_i`
61			`len: 32`
62			`:i0_wb_dat_o: SOCM_PORT`
63			`defn: dat_o`
64			`len: 32`
65			`:i0_wb_ack_o: SOCM_PORT`
66			`defn: ack`
67			`len: 1`
68			`:i0_wb_err_o: SOCM_PORT`
69			`defn: err`
70			`len: 1`
71			`:i1: SOCM_IFC`
72			`name: wishbone_ma`
73	7	feddischso	`dir: 0`
74	10	feddischso	`id: wishbone_ma,b3`
75	5	feddischso	`ports:`
76	7	feddischso	`:i1_wb_clk_o: SOCM_PORT`
77			`defn: clk`
78			`len: 1`
79			`:i1_wb_rst_o: SOCM_PORT`
80			`defn: rst`
81			`len: 1`
82	5	feddischso	`:i1_wb_cyc_i: SOCM_PORT`
83			`defn: cyc`
84			`len: 1`
85			`:i1_wb_stb_i: SOCM_PORT`
86			`defn: stb`
87			`len: 1`
88			`:i1_wb_adr_i: SOCM_PORT`
89			`defn: adr`
90			`len: 32`
91			`:i1_wb_sel_i: SOCM_PORT`
92			`defn: sel`
93	7	feddischso	`len: 4`
94	5	feddischso	`:i1_wb_we_i: SOCM_PORT`
95			`defn: we`
96			`len: 1`
97			`:i1_wb_dat_i: SOCM_PORT`
98			`defn: dat_i`
99			`len: 32`
100			`:i1_wb_dat_o: SOCM_PORT`
101			`defn: dat_o`
102			`len: 32`
103			`:i1_wb_ack_o: SOCM_PORT`
104			`defn: ack`
105			`len: 1`
106			`:i1_wb_err_o: SOCM_PORT`
107			`defn: err`
108			`len: 1`
109			`:i2: SOCM_IFC`
110			`name: wishbone_ma`
111	7	feddischso	`dir: 0`
112	10	feddischso	`id: wishbone_ma,b3`
113	5	feddischso	`ports:`
114	7	feddischso	`:i2_wb_clk_o: SOCM_PORT`
115			`defn: clk`
116			`len: 1`
117			`:i2_wb_rst_o: SOCM_PORT`
118			`defn: rst`
119			`len: 1`
120	5	feddischso	`:i2_wb_cyc_i: SOCM_PORT`
121			`defn: cyc`
122			`len: 1`
123			`:i2_wb_stb_i: SOCM_PORT`
124			`defn: stb`
125			`len: 1`
126			`:i2_wb_adr_i: SOCM_PORT`
127			`defn: adr`
128			`len: 32`
129			`:i2_wb_sel_i: SOCM_PORT`
130			`defn: sel`
131	7	feddischso	`len: 4`
132	5	feddischso	`:i2_wb_we_i: SOCM_PORT`
133			`defn: we`
134			`len: 1`
135			`:i2_wb_dat_i: SOCM_PORT`
136			`defn: dat_i`
137			`len: 32`
138			`:i2_wb_dat_o: SOCM_PORT`
139			`defn: dat_o`
140			`len: 32`
141			`:i2_wb_ack_o: SOCM_PORT`
142			`defn: ack`
143			`len: 1`
144			`:i2_wb_err_o: SOCM_PORT`
145			`defn: err`
146			`len: 1`
147			`:i3: SOCM_IFC`
148			`name: wishbone_ma`
149	7	feddischso	`dir: 0`
150	10	feddischso	`id: wishbone_ma,b3`
151	5	feddischso	`ports:`
152	7	feddischso	`:i3_wb_clk_o: SOCM_PORT`
153			`defn: clk`
154			`len: 1`
155			`:i3_wb_rst_o: SOCM_PORT`
156			`defn: rst`
157			`len: 1`
158	5	feddischso	`:i3_wb_cyc_i: SOCM_PORT`
159			`defn: cyc`
160			`len: 1`
161			`:i3_wb_stb_i: SOCM_PORT`
162			`defn: stb`
163			`len: 1`
164			`:i3_wb_adr_i: SOCM_PORT`
165			`defn: adr`
166			`len: 32`
167			`:i3_wb_sel_i: SOCM_PORT`
168			`defn: sel`
169	7	feddischso	`len: 4`
170	5	feddischso	`:i3_wb_we_i: SOCM_PORT`
171			`defn: we`
172			`len: 1`
173			`:i3_wb_dat_i: SOCM_PORT`
174			`defn: dat_i`
175			`len: 32`
176			`:i3_wb_dat_o: SOCM_PORT`
177			`defn: dat_o`
178			`len: 32`
179			`:i3_wb_ack_o: SOCM_PORT`
180			`defn: ack`
181			`len: 1`
182			`:i3_wb_err_o: SOCM_PORT`
183			`defn: err`
184			`len: 1`
185			`:i4: SOCM_IFC`
186			`name: wishbone_ma`
187	7	feddischso	`dir: 0`
188	10	feddischso	`id: wishbone_ma,b3`
189	5	feddischso	`ports:`
190	7	feddischso	`:i4_wb_clk_o: SOCM_PORT`
191			`defn: clk`
192			`len: 1`
193			`:i4_wb_rst_o: SOCM_PORT`
194			`defn: rst`
195			`len: 1`
196	5	feddischso	`:i4_wb_cyc_i: SOCM_PORT`
197			`defn: cyc`
198			`len: 1`
199			`:i4_wb_stb_i: SOCM_PORT`
200			`defn: stb`
201			`len: 1`
202			`:i4_wb_adr_i: SOCM_PORT`
203			`defn: adr`
204			`len: 32`
205			`:i4_wb_sel_i: SOCM_PORT`
206			`defn: sel`
207	7	feddischso	`len: 4`
208	5	feddischso	`:i4_wb_we_i: SOCM_PORT`
209			`defn: we`
210			`len: 1`
211			`:i4_wb_dat_i: SOCM_PORT`
212			`defn: dat_i`
213			`len: 32`
214			`:i4_wb_dat_o: SOCM_PORT`
215			`defn: dat_o`
216			`len: 32`
217			`:i4_wb_ack_o: SOCM_PORT`
218			`defn: ack`
219			`len: 1`
220			`:i4_wb_err_o: SOCM_PORT`
221			`defn: err`
222			`len: 1`
223			`:i5: SOCM_IFC`
224			`name: wishbone_ma`
225	7	feddischso	`dir: 0`
226	10	feddischso	`id: wishbone_ma,b3`
227	5	feddischso	`ports:`
228	7	feddischso	`:i5_wb_clk_o: SOCM_PORT`
229			`defn: clk`
230			`len: 1`
231			`:i5_wb_rst_o: SOCM_PORT`
232			`defn: rst`
233			`len: 1`
234	5	feddischso	`:i5_wb_cyc_i: SOCM_PORT`
235			`defn: cyc`
236			`len: 1`
237			`:i5_wb_stb_i: SOCM_PORT`
238			`defn: stb`
239			`len: 1`
240			`:i5_wb_adr_i: SOCM_PORT`
241			`defn: adr`
242			`len: 32`
243			`:i5_wb_sel_i: SOCM_PORT`
244			`defn: sel`
245	7	feddischso	`len: 4`
246	5	feddischso	`:i5_wb_we_i: SOCM_PORT`
247			`defn: we`
248			`len: 1`
249			`:i5_wb_dat_i: SOCM_PORT`
250			`defn: dat_i`
251			`len: 32`
252			`:i5_wb_dat_o: SOCM_PORT`
253			`defn: dat_o`
254			`len: 32`
255			`:i5_wb_ack_o: SOCM_PORT`
256			`defn: ack`
257			`len: 1`
258			`:i5_wb_err_o: SOCM_PORT`
259			`defn: err`
260			`len: 1`
261			`:i6: SOCM_IFC`
262			`name: wishbone_ma`
263	7	feddischso	`dir: 0`
264	10	feddischso	`id: wishbone_ma,b3`
265	5	feddischso	`ports:`
266	7	feddischso	`:i6_wb_clk_o: SOCM_PORT`
267			`defn: clk`
268			`len: 1`
269			`:i6_wb_rst_o: SOCM_PORT`
270			`defn: rst`
271			`len: 1`
272	5	feddischso	`:i6_wb_cyc_i: SOCM_PORT`
273			`defn: cyc`
274			`len: 1`
275			`:i6_wb_stb_i: SOCM_PORT`
276			`defn: stb`
277			`len: 1`
278			`:i6_wb_adr_i: SOCM_PORT`
279			`defn: adr`
280			`len: 32`
281			`:i6_wb_sel_i: SOCM_PORT`
282			`defn: sel`
283	7	feddischso	`len: 4`
284	5	feddischso	`:i6_wb_we_i: SOCM_PORT`
285			`defn: we`
286			`len: 1`
287			`:i6_wb_dat_i: SOCM_PORT`
288			`defn: dat_i`
289			`len: 32`
290			`:i6_wb_dat_o: SOCM_PORT`
291			`defn: dat_o`
292			`len: 32`
293			`:i6_wb_ack_o: SOCM_PORT`
294			`defn: ack`
295			`len: 1`
296			`:i6_wb_err_o: SOCM_PORT`
297			`defn: err`
298			`len: 1`
299			`:i7: SOCM_IFC`
300			`name: wishbone_ma`
301	7	feddischso	`dir: 0`
302	10	feddischso	`id: wishbone_ma,b3`
303	5	feddischso	`ports:`
304	7	feddischso	`:i7_wb_clk_o: SOCM_PORT`
305			`defn: clk`
306			`len: 1`
307			`:i7_wb_rst_o: SOCM_PORT`
308			`defn: rst`
309			`len: 1`
310	5	feddischso	`:i7_wb_cyc_i: SOCM_PORT`
311			`defn: cyc`
312			`len: 1`
313			`:i7_wb_stb_i: SOCM_PORT`
314			`defn: stb`
315			`len: 1`
316			`:i7_wb_adr_i: SOCM_PORT`
317			`defn: adr`
318			`len: 32`
319			`:i7_wb_sel_i: SOCM_PORT`
320			`defn: sel`
321	7	feddischso	`len: 4`
322	5	feddischso	`:i7_wb_we_i: SOCM_PORT`
323			`defn: we`
324			`len: 1`
325			`:i7_wb_dat_i: SOCM_PORT`
326			`defn: dat_i`
327			`len: 32`
328			`:i7_wb_dat_o: SOCM_PORT`
329			`defn: dat_o`
330			`len: 32`
331			`:i7_wb_ack_o: SOCM_PORT`
332			`defn: ack`
333			`len: 1`
334			`:i7_wb_err_o: SOCM_PORT`
335			`defn: err`
336			`len: 1`
337			`:t0: SOCM_IFC`
338			`name: wishbone_sl`
339	7	feddischso	`dir: 0`
340	10	feddischso	`id: wishbone_sl,b3`
341	5	feddischso	`ports:`
342	7	feddischso	`:t0_wb_clk_o: SOCM_PORT`
343			`defn: clk`
344			`len: 1`
345			`:t0_wb_rst_o: SOCM_PORT`
346			`defn: rst`
347			`len: 1`
348	5	feddischso	`:t0_wb_cyc_o: SOCM_PORT`
349			`defn: cyc`
350			`len: 1`
351			`:t0_wb_stb_o: SOCM_PORT`
352			`defn: stb`
353			`len: 1`
354			`:t0_wb_adr_o: SOCM_PORT`
355			`defn: adr`
356			`len: 32`
357			`:t0_wb_sel_o: SOCM_PORT`
358			`defn: sel`
359	7	feddischso	`len: 4`
360	5	feddischso	`:t0_wb_we_o: SOCM_PORT`
361			`defn: we`
362			`len: 1`
363			`:t0_wb_dat_o: SOCM_PORT`
364	7	feddischso	`defn: dat_o`
365	5	feddischso	`len: 32`
366			`:t0_wb_dat_i: SOCM_PORT`
367			`defn: dat_i`
368			`len: 32`
369			`:t0_wb_ack_i: SOCM_PORT`
370			`defn: ack`
371			`len: 1`
372			`:t0_wb_err_i: SOCM_PORT`
373			`defn: err`
374			`len: 1`
375			`:t1: SOCM_IFC`
376			`name: wishbone_sl`
377	7	feddischso	`dir: 0`
378	10	feddischso	`id: wishbone_sl,b3`
379	5	feddischso	`ports:`
380	7	feddischso	`:t1_wb_clk_o: SOCM_PORT`
381			`defn: clk`
382			`len: 1`
383			`:t1_wb_rst_o: SOCM_PORT`
384			`defn: rst`
385			`len: 1`
386	5	feddischso	`:t1_wb_cyc_o: SOCM_PORT`
387			`defn: cyc`
388			`len: 1`
389			`:t1_wb_stb_o: SOCM_PORT`
390			`defn: stb`
391			`len: 1`
392			`:t1_wb_adr_o: SOCM_PORT`
393			`defn: adr`
394			`len: 32`
395			`:t1_wb_sel_o: SOCM_PORT`
396			`defn: sel`
397	7	feddischso	`len: 4`
398	5	feddischso	`:t1_wb_we_o: SOCM_PORT`
399			`defn: we`
400			`len: 1`
401			`:t1_wb_dat_o: SOCM_PORT`
402	7	feddischso	`defn: dat_o`
403	5	feddischso	`len: 32`
404			`:t1_wb_dat_i: SOCM_PORT`
405			`defn: dat_i`
406			`len: 32`
407			`:t1_wb_ack_i: SOCM_PORT`
408			`defn: ack`
409			`len: 1`
410			`:t1_wb_err_i: SOCM_PORT`
411			`defn: err`
412			`len: 1`
413			`:t2: SOCM_IFC`
414			`name: wishbone_sl`
415	7	feddischso	`dir: 0`
416	10	feddischso	`id: wishbone_sl,b3`
417	5	feddischso	`ports:`
418	7	feddischso	`:t2_wb_clk_o: SOCM_PORT`
419			`defn: clk`
420			`len: 1`
421			`:t2_wb_rst_o: SOCM_PORT`
422			`defn: rst`
423			`len: 1`
424	5	feddischso	`:t2_wb_cyc_o: SOCM_PORT`
425			`defn: cyc`
426			`len: 1`
427			`:t2_wb_stb_o: SOCM_PORT`
428			`defn: stb`
429			`len: 1`
430			`:t2_wb_adr_o: SOCM_PORT`
431			`defn: adr`
432			`len: 32`
433			`:t2_wb_sel_o: SOCM_PORT`
434			`defn: sel`
435	7	feddischso	`len: 4`
436	5	feddischso	`:t2_wb_we_o: SOCM_PORT`
437			`defn: we`
438			`len: 1`
439			`:t2_wb_dat_o: SOCM_PORT`
440	7	feddischso	`defn: dat_o`
441	5	feddischso	`len: 32`
442			`:t2_wb_dat_i: SOCM_PORT`
443			`defn: dat_i`
444			`len: 32`
445			`:t2_wb_ack_i: SOCM_PORT`
446			`defn: ack`
447			`len: 1`
448			`:t2_wb_err_i: SOCM_PORT`
449			`defn: err`
450			`len: 1`
451			`:t3: SOCM_IFC`
452			`name: wishbone_sl`
453	7	feddischso	`dir: 0`
454	10	feddischso	`id: wishbone_sl,b3`
455	5	feddischso	`ports:`
456	7	feddischso	`:t3_wb_clk_o: SOCM_PORT`
457			`defn: clk`
458			`len: 1`
459			`:t3_wb_rst_o: SOCM_PORT`
460			`defn: rst`
461			`len: 1`
462	5	feddischso	`:t3_wb_cyc_o: SOCM_PORT`
463			`defn: cyc`
464			`len: 1`
465			`:t3_wb_stb_o: SOCM_PORT`
466			`defn: stb`
467			`len: 1`
468			`:t3_wb_adr_o: SOCM_PORT`
469			`defn: adr`
470			`len: 32`
471			`:t3_wb_sel_o: SOCM_PORT`
472			`defn: sel`
473	7	feddischso	`len: 4`
474	5	feddischso	`:t3_wb_we_o: SOCM_PORT`
475			`defn: we`
476			`len: 1`
477			`:t3_wb_dat_o: SOCM_PORT`
478	7	feddischso	`defn: dat_o`
479	5	feddischso	`len: 32`
480			`:t3_wb_dat_i: SOCM_PORT`
481			`defn: dat_i`
482			`len: 32`
483			`:t3_wb_ack_i: SOCM_PORT`
484			`defn: ack`
485			`len: 1`
486			`:t3_wb_err_i: SOCM_PORT`
487			`defn: err`
488			`len: 1`
489			`:t4: SOCM_IFC`
490			`name: wishbone_sl`
491	7	feddischso	`dir: 0`
492	10	feddischso	`id: wishbone_sl,b3`
493	5	feddischso	`ports:`
494	7	feddischso	`:t4_wb_clk_o: SOCM_PORT`
495			`defn: clk`
496			`len: 1`
497			`:t4_wb_rst_o: SOCM_PORT`
498			`defn: rst`
499			`len: 1`
500	5	feddischso	`:t4_wb_cyc_o: SOCM_PORT`

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