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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [verilog/] [sram_be.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 module
  cde_sram_be
    #( parameter
      ADDR=10,
      WIDTH=8,
      WORDS=1024,
      WRITETHRU=0,
      DEFAULT={WIDTH{1'b1}},
      INIT_FILE="NONE",
      MEM="NONE",
      INSTANCE_NAME="../../../../../children/")
     (
 input   wire                 be,
 input   wire                 clk,
 input   wire                 cs,
 input   wire                 rd,
 input   wire                 wr,
 input   wire    [ ADDR-1 :  0]        addr,
 input   wire    [ WIDTH-1 :  0]        wdata,
 output   reg    [ WIDTH-1 :  0]        rdata);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial
  begin
   if( MEM  == "NONE")
     begin
     end
   else
        begin
        $readmemh(MEM, mem);
        end
  end
// Write function   
// Write function   
always@(posedge clk)
        if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if( WRITETHRU)
  begin
  // Read function gets new data if also a write cycle
  // latch the read addr for next cycle   
  reg   [ADDR-1:0]          l_raddr;
 
 
  reg                       l_cycle;
 
  always@(posedge clk)
        l_cycle    <=  rd && cs ;
 
 
 
  always@(posedge clk)
        if( rd && cs ) l_raddr    <= addr;
        else           l_raddr    <= l_raddr;
 
 
  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
  wire  [7:0] tmp_rdata;
  assign                    tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
  always@(*)                rdata  =      tmp_rdata;
  end
else
  begin
  // Read function gets old data if also a write cycle
  always@(posedge clk)
        if( rd && cs ) rdata             <= mem[{addr[ADDR-1:0]}];
        else           rdata             <= DEFAULT;
  end
endgenerate
  endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21			`module`
22			`cde_sram_be`
23			`#( parameter`
24			`ADDR=10,`
25			`WIDTH=8,`
26			`WORDS=1024,`
27			`WRITETHRU=0,`
28			`DEFAULT={WIDTH{1'b1}},`
29			`INIT_FILE="NONE",`
30			`MEM="NONE",`
31			`INSTANCE_NAME="../../../../../children/")`
32			`(`
33			`input wire be,`
34			`input wire clk,`
35			`input wire cs,`
36			`input wire rd,`
37			`input wire wr,`
38			`input wire [ ADDR-1 : 0] addr,`
39			`input wire [ WIDTH-1 : 0] wdata,`
40			`output reg [ WIDTH-1 : 0] rdata);`
41			`// Memory Array`
42			`reg [WIDTH-1:0] mem[0:WORDS-1];`
43			`// If used as Rom then load a memory image at startup`
44			`initial`
45			`begin`
46			`if( MEM == "NONE")`
47			`begin`
48			`end`
49			`else`
50			`begin`
51			`$readmemh(MEM, mem);`
52			`end`
53			`end`
54			`// Write function`
55			`// Write function`
56			`always@(posedge clk)`
57			`if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];`
58			`generate`
59			`if( WRITETHRU)`
60			`begin`
61			`// Read function gets new data if also a write cycle`
62			`// latch the read addr for next cycle`
63			`reg [ADDR-1:0] l_raddr;`
64
65
66			`reg l_cycle;`
67
68			`always@(posedge clk)`
69			`l_cycle <= rd && cs ;`
70
71
72
73			`always@(posedge clk)`
74			`if( rd && cs ) l_raddr <= addr;`
75			`else l_raddr <= l_raddr;`
76
77
78			`// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block`
79			`wire [7:0] tmp_rdata;`
80			`assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;`
81			`always@(*) rdata = tmp_rdata;`
82			`end`
83			`else`
84			`begin`
85			`// Read function gets old data if also a write cycle`
86			`always@(posedge clk)`
87			`if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];`
88			`else rdata <= DEFAULT;`
89			`end`
90			`endgenerate`
91			`endmodule`

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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [verilog/] [sram_be.v] - Blame information for rev 131