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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3
4
5			`//=============================================================================`
6			`// Rtl Glue Logic`
7			`//=============================================================================`
8
9			`assign cpu_pg0_data = pg0_add[0]?mem_rdata[15:8]:mem_rdata[7:0];`
10			`assign pg00_ram_rd = pg0_rd\|\|(mem_cs && mem_rd);`
11			`assign pg00_ram_l_wr = (pg0_wr\|\|(mem_cs && mem_wr)) && (!pg0_add[0]);`
12			`assign pg00_ram_h_wr = (pg0_wr\|\|(mem_cs && mem_wr)) && ( pg0_add[0]);`
13			`assign io_module_pic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`
14			`assign io_module_vic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`
15
16
17			`cde_sram_dp`
18			`#( .WIDTH (8),`
19			`.ADDR (7),`
20			`.WORDS (128),`
21			`.DEFAULT (8'hff))`
22			`pg00_ram_l`
23			`(`
24			`.clk (clk),`
25			`.cs (1'b1),`
26			`.raddr (pg0_add[7:1]),`
27			`.rd (pg00_ram_rd),`
28			`.rdata (mem_rdata[7:0]),`
29			`.waddr (pg0_add[7:1]),`
30			`.wdata (mem_wdata[7:0]),`
31			`.wr (pg00_ram_l_wr));`
32			`cde_sram_dp`
33			`#( .WIDTH (8),`
34			`.ADDR (7),`
35			`.WORDS (128),`
36			`.DEFAULT (8'hff))`
37			`pg00_ram_h`
38			`(`
39			`.clk (clk),`
40			`.cs (1'b1),`
41			`.raddr (pg0_add[7:1]),`
42			`.rd (pg00_ram_rd),`
43			`.rdata (mem_rdata[15:8]),`
44			`.waddr (pg0_add[7:1]),`
45			`.wdata (mem_wdata[15:8]),`
46			`.wr (pg00_ram_h_wr));`
47
48
49			`//=============================================================================`
50			`//`
51			`//=============================================================================`
52