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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
ctrl  default
 

 
 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      ctrl_default
    
    
      destination
      top.ctrl
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.ctrl
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.ctrl
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 

 
 
 
 
 
 
 

 

    VEC_TABLE8'hff

 
 
 
 
   
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     fs-common
     
 
     
     sim:*Simulation:*
     Verilog
     
     fs-sim
     
 
 
     
     syn:*Synthesis:*
     Verilog
     
     fs-syn
     
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
   
 
 
 
 
 
 

 
 

clk
wire
in

 
 

cpu_pg0_data
wire
out70

 
 
 

pg00_ram_rd
wire
out

 
 

pg00_ram_l_wr
wire
out

 
 

pg00_ram_h_wr
wire
out

 
 
 
 
 
 
 
 

io_module_pic_irq_in
wire
out70

 
 
 
 
 

io_module_vic_irq_in
wire
out70

 
 
 
 
 
 
 
 

mem_rdata
wire
out150

 
 
 

mem_wdata
wire
in150

 
 
 
 
 

pg0_add
wire
in70

 
 

mem_addr
wire
in00

 
 

mem_cs
wire
in

 
 
 
 
mem_wr
wire
in

 
 
pg0_wr
wire
in

 
 
mem_rd
wire
in

 
 
 
pg0_rd
wire
in

 
 
 
 
 

timer_irq
wire
in10

 
 
 
rx_irq
wire
in

 
 
tx_irq
wire
in

 
 
ps2_data_avail
wire
in

 
 
 
ext_irq_in
wire
in20

 
 

 

 
 
 
 
 
 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`ctrl default`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`configuration`
60			`ctrl_default`
61
62
63			`destination`
64			`top.ctrl`
65
66
67			`dest_dir`
68			`../verilog`
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86			`fs-common`
87
88
89
90			`../verilog/top.rtl`
91			`verilogSourcefragment`
92
93
94
95
96
97
98
99
100			`fs-sim`
101
102
103
104			`../verilog/copyright.v`
105			`verilogSourceinclude`
106
107
108
109
110			`../verilog/common/top.ctrl`
111			`verilogSourcemodule`
112
113
114
115
116
117
118
119			`fs-syn`
120
121
122
123			`../verilog/copyright.v`
124			`verilogSourceinclude`
125
126
127
128
129			`../verilog/common/top.ctrl`
130			`verilogSourcemodule`
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152			`VEC_TABLE8'hff`
153
154
155
156
157
158
159
160
161			`verilog`
162
163
164			`spirit:library="Testbench"`
165			`spirit:name="toolflow"`
166			`spirit:version="verilog"/>`
167
168
169
170
171
172
173
174
175			`commoncommon`
176			`Verilog`
177
178			`fs-common`
179
180
181
182			`sim:Simulation:`
183			`Verilog`
184
185			`fs-sim`
186
187
188
189
190			`syn:Synthesis:`
191			`Verilog`
192
193			`fs-syn`
194
195
196
197
198
199			`doc`
200
201
202			`spirit:library="Testbench"`
203			`spirit:name="toolflow"`
204			`spirit:version="documentation"/>`
205
206			`:Documentation:`
207			`Verilog`
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222			`clk`
223			`wire`
224			`in`
225
226
227
228
229			`cpu_pg0_data`
230			`wire`
231			`out70`
232
233
234
235
236
237			`pg00_ram_rd`
238			`wire`
239			`out`
240
241
242
243
244			`pg00_ram_l_wr`
245			`wire`
246			`out`
247
248
249
250
251			`pg00_ram_h_wr`
252			`wire`
253			`out`
254
255
256
257
258
259
260
261
262
263
264			`io_module_pic_irq_in`
265			`wire`
266			`out70`
267
268
269
270
271
272
273
274			`io_module_vic_irq_in`
275			`wire`
276			`out70`
277
278
279
280
281
282
283
284
285
286
287			`mem_rdata`
288			`wire`
289			`out150`
290
291
292
293
294
295			`mem_wdata`
296			`wire`
297			`in150`
298
299
300
301
302
303
304
305			`pg0_add`
306			`wire`
307			`in70`
308
309
310
311
312			`mem_addr`
313			`wire`
314			`in00`
315
316
317
318
319			`mem_cs`
320			`wire`
321			`in`
322
323
324
325
326
327			`mem_wr`
328			`wire`
329			`in`
330
331
332
333			`pg0_wr`
334			`wire`
335			`in`
336
337
338
339			`mem_rd`
340			`wire`
341			`in`
342
343
344
345
346			`pg0_rd`
347			`wire`
348			`in`
349
350
351
352
353
354
355
356			`timer_irq`
357			`wire`
358			`in10`
359
360
361
362
363			`rx_irq`
364			`wire`
365			`in`
366
367
368
369			`tx_irq`
370			`wire`
371			`in`
372
373
374
375			`ps2_data_avail`
376			`wire`
377			`in`
378
379
380
381
382			`ext_irq_in`
383			`wire`
384			`in20`
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403