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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 
 
 jtag
  
  
    
 
      
        shiftcapture_dr_clk
        jtag_shiftcapture_dr_clk
      
 
 
      
        test_logic_reset
        jtag_test_logic_reset
      
 
      
        capture_dr
        jtag_capture_dr
      
 
      
        shift_dr
        jtag_shift_dr
      
 
      
        update_dr_clk
        jtag_update_dr_clk
      
 
 
      
        tdi
        jtag_tdi
      
 
      
        tdo
        jtag_tdo
      
 
      
        select
        jtag_select
      
 
    
 
 
 
 

 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/syn.v
        verilogSourceinclude
      
 
 
 
   
 
 

 
 
 
 
 
 
 

 

    CPU_ADD16
    VEC_TABLE8'hff
    ROM_DEFAULT16'hffff
    BOOT_ROM_WIDTH16
    ROM_WRITETHRU0

 
 
 
 
   
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     
 
     
     sim:*Simulation:*
      Verilog
     
     fs-sim
     
 
     
     syn:*Synthesis:*
      Verilog
     
     fs-sim
     
 
 
     
     syn2:*Synthesis:*
      Verilog
     
     fs-syn
     
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
   
 
 
 

 
 

ext_addr
wire
out231

 

ext_wdata
wire
out150

 

ext_rdata
wire
in150

 
 

ext_ub
wire
out

 
ext_wait
wire
in

 
ext_lb
wire
out

 
ext_rd
wire
out

 
ext_stb
wire
out

 
ext_wr
wire
out

 
ext_cs
wire
out10

 
 
alu_status
wire
out70

 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
 
gpio_0_out
wire
out70

 
gpio_0_oe
wire
out70

 
 
gpio_0_in
wire
in70

 
gpio_1_out
wire
out70

 
gpio_1_oe
wire
out70

 
 
gpio_1_in
wire
in70

 
ext_irq_in
wire
in30

 
 
 
 
jsp_data_out
wire
out70

 
 
 
wb_jsp_dat_i
wire
in70

 
 
biu_wr_strobe
wire
out

 
 
wb_jsp_stb_i
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75			`jtag`
76
77
78
79
80
81			`shiftcapture_dr_clk`
82			`jtag_shiftcapture_dr_clk`
83
84
85
86
87			`test_logic_reset`
88			`jtag_test_logic_reset`
89
90
91
92			`capture_dr`
93			`jtag_capture_dr`
94
95
96
97			`shift_dr`
98			`jtag_shift_dr`
99
100
101
102			`update_dr_clk`
103			`jtag_update_dr_clk`
104
105
106
107
108			`tdi`
109			`jtag_tdi`
110
111
112
113			`tdo`
114			`jtag_tdo`
115
116
117
118			`select`
119			`jtag_select`
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135			`elab_verilog`
136	133	jt_eaton	`102.1`
137	131	jt_eaton	`none`
138			`:Simulation:`
139			`./tools/verilog/elab_verilog`
140
141
142	133	jt_eaton	`configuration`
143			`default`
144	131	jt_eaton
145
146	133	jt_eaton	`dest_dir`
147			`io_ports`
148	131	jt_eaton
149
150
151
152
153
154			`gen_verilog`
155			`104.0`
156			`none`
157			`common`
158			`./tools/verilog/gen_verilog`
159
160
161			`destination`
162			`top`
163
164
165			`dest_dir`
166			`../verilog`
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-common`
188
189
190
191			`../verilog/top.rtl`
192			`verilogSourcefragment`
193
194
195
196
197
198
199
200
201			`fs-sim`
202
203
204
205			`../verilog/copyright.v`
206			`verilogSourceinclude`
207
208
209
210
211			`../verilog/common/top`
212			`verilogSourcemodule`
213
214
215
216
217
218
219
220			`fs-syn`
221
222
223
224			`../verilog/syn.v`
225			`verilogSourceinclude`
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244			`CPU_ADD16`
245			`VEC_TABLE8'hff`
246	133	jt_eaton	`ROM_DEFAULT16'hffff`
247			`BOOT_ROM_WIDTH16`
248			`ROM_WRITETHRU0`
249	131	jt_eaton
250
251
252	133	jt_eaton
253	131	jt_eaton
254
255
256
257
258			`Hierarchical`
259
260
261			`spirit:library="Mos6502"`
262			`spirit:name="T6502"`
263			`spirit:version="def.design"/>`
264
265
266
267
268			`verilog`
269
270
271			`spirit:library="Testbench"`
272			`spirit:name="toolflow"`
273			`spirit:version="verilog"/>`
274
275
276
277
278
279
280
281
282			`commoncommon`
283			`Verilog`
284
285
286
287
288			`sim:Simulation:`
289			`Verilog`
290
291			`fs-sim`
292
293
294
295			`syn:Synthesis:`
296			`Verilog`
297
298			`fs-sim`
299
300
301
302
303			`syn2:Synthesis:`
304			`Verilog`
305
306			`fs-syn`
307
308
309
310
311
312
313
314			`doc`
315
316
317			`spirit:library="Testbench"`
318			`spirit:name="toolflow"`
319			`spirit:version="documentation"/>`
320
321			`:Documentation:`
322			`Verilog`
323
324
325
326
327
328
329
330
331
332
333
334
335
336			`ext_addr`
337			`wire`
338			`out231`
339
340
341
342			`ext_wdata`
343			`wire`
344			`out150`
345
346
347
348			`ext_rdata`
349			`wire`
350			`in150`
351
352
353
354
355			`ext_ub`
356			`wire`
357			`out`
358
359
360			`ext_wait`
361			`wire`
362			`in`
363
364
365			`ext_lb`
366			`wire`
367			`out`
368
369
370			`ext_rd`
371			`wire`
372			`out`
373
374
375			`ext_stb`
376			`wire`
377			`out`
378
379
380			`ext_wr`
381			`wire`
382			`out`
383
384
385			`ext_cs`
386			`wire`
387			`out10`
388
389
390
391			`alu_status`
392			`wire`
393			`out70`
394
395
396			`cts_pad_in`
397			`wire`
398			`in`
399
400
401			`rts_pad_out`
402			`wire`
403			`out`
404
405
406
407			`gpio_0_out`
408			`wire`
409			`out70`
410
411
412			`gpio_0_oe`
413			`wire`
414			`out70`
415
416
417
418			`gpio_0_in`
419			`wire`
420			`in70`
421
422
423			`gpio_1_out`
424			`wire`
425			`out70`
426
427
428			`gpio_1_oe`
429			`wire`
430			`out70`
431
432
433
434			`gpio_1_in`
435			`wire`
436			`in70`
437
438
439			`ext_irq_in`
440			`wire`
441			`in30`
442
443
444
445
446
447			`jsp_data_out`
448			`wire`
449			`out70`
450
451
452
453
454			`wb_jsp_dat_i`
455			`wire`
456			`in70`
457
458
459
460			`biu_wr_strobe`
461			`wire`
462			`out`
463
464
465
466			`wb_jsp_stb_i`
467			`wire`
468			`in`
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
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495