URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [tb.int_m] - Blame information for rev 131

Details | Compare with Previous | View Log


assign ext_irq_in           = 4'h0;
assign cts_pad_in           = 1'b0;
assign ext_wait             = 1'b0;
assign ps2_clk_pad_in       = 1'b0;
assign ps2_data_pad_in      = 1'b0;
assign uart_rxd_pad_in      = 1'b0;
assign ext_rdata            = 16'b0;
assign gpio_0_in            = 8'b0;
assign gpio_1_in            = 8'b0;
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`assign ext_irq_in = 4'h0;`
2			`assign cts_pad_in = 1'b0;`
3			`assign ext_wait = 1'b0;`
4			`assign ps2_clk_pad_in = 1'b0;`
5			`assign ps2_data_pad_in = 1'b0;`
6			`assign uart_rxd_pad_in = 1'b0;`
7			`assign ext_rdata = 16'b0;`
8			`assign gpio_0_in = 8'b0;`
9			`assign gpio_1_in = 8'b0;`
10
11

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [tb.int_m] - Blame information for rev 131