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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [top.vtb] - Blame information for rev 131

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   reg                          x_FINISH;
   reg                          x_FAIL;
 
always@(posedge clk or negedge START)
  if(!START)  x_FINISH             <= 1'b0;
  else
  if(gpio_0_out == 8'hee) x_FINISH <= 1'b1;
  else
  if(gpio_0_out == 8'hff) x_FINISH <= 1'b1;
  else                    x_FINISH <= 1'b0;
 
always@(posedge clk or negedge START)
  if(!START)  x_FAIL  <= 1'b0;
  else
  if(gpio_1_out != 8'h00) x_FAIL <= (gpio_0_out == 8'hff);
 
 
assign STOP = x_FINISH;
assign BAD = x_FAIL;

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg x_FINISH;`
2			`reg x_FAIL;`
3
4			`always@(posedge clk or negedge START)`
5			`if(!START) x_FINISH <= 1'b0;`
6			`else`
7			`if(gpio_0_out == 8'hee) x_FINISH <= 1'b1;`
8			`else`
9			`if(gpio_0_out == 8'hff) x_FINISH <= 1'b1;`
10			`else x_FINISH <= 1'b0;`
11
12			`always@(posedge clk or negedge START)`
13			`if(!START) x_FAIL <= 1'b0;`
14			`else`
15			`if(gpio_1_out != 8'h00) x_FAIL <= (gpio_0_out == 8'hff);`
16
17
18			`assign STOP = x_FINISH;`
19			`assign BAD = x_FAIL;`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [top.vtb] - Blame information for rev 131