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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def_vtb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      top
    
    
      configuration
      default
    
    
      destination
      tb.vtb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
 
 
 


    TIMEOUT10000

 
 
       
 
              
              Params
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def_dut.params"/>
              
 
              
 
 
 
              
              Sram
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="sram.design"/>
              
 
 
 
              
              verilator
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilator"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.int_m
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.vtb
        verilogSourcefragment
      
 
   
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_vtb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`top`
57
58
59	133	jt_eaton	`configuration`
60			`default`
61
62
63	131	jt_eaton	`destination`
64			`tb.vtb`
65
66
67			`dest_dir`
68			`../verilog`
69
70
71
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82
83
84			`TIMEOUT10000`
85
86
87
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89
90
91			`Params`
92
93
94			`spirit:library="Mos6502"`
95			`spirit:name="T6502"`
96			`spirit:version="def_dut.params"/>`
97
98
99
100
101
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103
104			`Sram`
105
106			`spirit:library="Mos6502"`
107			`spirit:name="T6502"`
108			`spirit:version="sram.design"/>`
109
110
111
112
113
114			`verilator`
115
116
117			`spirit:library="Testbench"`
118			`spirit:name="toolflow"`
119			`spirit:version="verilator"/>`
120
121
122
123
124
125
126			`commoncommon`
127			`Verilog`
128
129
130			`fs-common`
131
132
133
134
135
136
137
138			`syn:Synthesis:`
139			`Verilog`
140
141
142			`fs-syn`
143
144
145
146
147
148			`lint:Lint:`
149			`Verilog`
150
151
152			`fs-lint`
153
154
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172			`fs-common`
173
174
175
176			`../verilog/sram.load`
177			`verilogSourcefragment`
178
179
180
181
182
183			`../verilog/tb.int_m`
184			`verilogSourcefragment`
185
186
187
188
189
190			`../verilog/top.vtb`
191			`verilogSourcefragment`
192
193
194
195
196
197
198
199
200
201			`fs-syn`
202
203
204
205			`../verilog/common/tb.vtb`
206			`verilogSourcemodule`
207
208
209
210
211
212
213
214			`fs-lint`
215
216
217
218			`../verilog/common/tb.vtb`
219			`verilogSourcemodule`
220
221
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