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module `VARIANT`SEQUENCER
 
#(parameter VEC_TABLE = 8'hff,
  parameter STATE_SIZE=3
)
 
(
 
    input  wire            clk,
    input  wire            reset,
    input  wire            enable,
    input  wire            now_fetch_op,
    input  wire    [STATE_SIZE:0]   state,         // current and next state registers
    input  wire    [1:0]   cmd,
    input  wire    [7:0]   vector,
    input  wire    [1:0]   length,
    input  wire    [7:0]   alu_a,
    input  wire    [7:0]   alu_result,    // result from alu operation
    input  wire    [7:0]   alu_status,    //
    input  wire    [7:0]   data_in,       // data that comes from the bus controller
    input  wire    [15:0]  prog_data16,       // data that comes from the bus controller
    input  wire    [7:0]   prog_data,
    input  wire    [7:0]   pg0_data,
    input  wire    [7:0]   index,         // selected index
 
    input  wire    [1:0]   ins_type,
    input  wire    [2:0]   alu_op_a_sel,
 
    input  wire            implied,
    input  wire            immediate,
    input  wire            relative,
    input  wire            absolute,
    input  wire            zero_page,
    input  wire            indirectx,
    input  wire            indirecty,
    input  wire            stack,
    input  wire            jump_indirect,
 
    input  wire            brk,
    input  wire            rti,
    input  wire            rts,
    input  wire            jump,
    input  wire            jsr,
 
    input  wire            branch_inst,
 
 
    output  reg            fetch_op,
    output  reg   [15:0]   prog_counter,            // program counter
 
 
    output  reg   [15:0]   address,       // system bus address
    output  reg            alu_enable,
 
    output  reg    [7:0]   pg0_add,
    output  reg            pg0_wr,
    output  reg            pg0_rd,
 
 
    output  reg   [7:0]    operand,
    output  reg   [7:0]    imm_data,
    output  reg            rd,        // read = 1
    output  reg            wr,        // write = 1
    output  reg    [7:0]   data_out,      // data that will be written somewhere else
 
 
    output  reg    [15:0]  offset,
 
    output  reg            stk_push,
    output  reg  [15:0]    stk_push_data,
    output  reg            stk_pull,
    input  wire  [15:0]    stk_pull_data
);
 
 
 
 
 
 
  reg              stk_push_p;
 
 
 
 
 wire [15:0]   next_pc;             // a simple logic to add one to the PC
 wire  [8:0]   p_indexed;
 
 assign next_pc              = prog_counter + 16'b0000000000000001;
 assign p_indexed            = prog_data +index;
 
 
 
always @ (posedge clk )
   if (reset)     stk_push              <= 1'b1;
   else           stk_push              <= stk_push_p  ||
                                           (stack   &&   !enable &&   (state == `EXECUTE )  &&     (ins_type == `ins_type_write )) ||
                                           (              enable &&   (state != `INT_1 )  &&     now_fetch_op &&   (cmd == `cmd_load_vec))  ;
 
 
 
 
 
 
 
 
always @ (posedge clk ) begin
   if (reset)
        begin
            stk_push_p      <=  1'b0;
 
        end
   else if(!enable)
        begin
            stk_push_p      <=  1'b0;
        end
    else begin
            case (state)
 
                `EXECUTE:
                    begin
                     if( jsr )
                          begin
                          stk_push_p         <= 1'b1;
                          end
                    end
 
                default:
                  begin
                   stk_push_p      <=  1'b0;
                  end
            endcase
        end
    end
 
 
 
 
 
 
 
 
always @ (posedge clk ) begin
   if (reset)
        begin
            stk_pull        <=  1'b0;
 
        end
   else if( enable)
        begin
            stk_pull        <=  1'b0;
        end
    else begin
            case (state)
 
 
                `EXECUTE:
                    begin
                     if( rts || rti)
                       begin
                       stk_pull               <= 1'b1;
                       end
                     else
                     if( stack )
                       begin
                        if(ins_type == `ins_type_read )
                         begin
                         stk_pull             <= 1'b1;
                         end
                       end
 
                    end
 
                default:
                  begin
                   stk_pull        <=  1'b0;
                  end
            endcase
        end
    end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge clk )
   begin
   if (reset)                                      stk_push_data      <= 16'h0000;
   else
   if((state ==  `AXE_1)  &&  jsr )                stk_push_data      <= prog_counter;
   else
   if((cmd == `cmd_load_vec) && now_fetch_op )     stk_push_data      <= prog_counter;
   else                                            stk_push_data      <= (alu_op_a_sel ==  `alu_op_a_psr)? {alu_status,alu_status}:{alu_a,alu_a};
   end
 
 
 
 
 
always @ (posedge clk )
   begin
   if (reset)
        begin
            prog_counter    <= 16'h0000;
            alu_enable      <=  1'b0;
            pg0_add         <=  8'h00;
            pg0_wr          <=  1'b0;
            pg0_rd          <=  1'b0;
            fetch_op        <=  1'b0;
            operand         <=  8'h00;
            imm_data        <=  8'h00;
            address         <= 16'h0000;
            rd          <=  1'b0;
            wr          <=  1'b0;
            data_out        <=  8'h00;
            offset          <=  16'h0000;
        end // if (reset)
   else if(!enable)
 
 
 
 
 
           begin
            case (state)
 
 
 
                `EXECUTE:
                    begin
                     if( jump || jsr || absolute)
                       begin
                       prog_counter           <= next_pc;
                       end
 
                    end
 
 
 
                `AXE_1:
                    begin
 
                     if( jump || jsr  )
                       begin
                          prog_counter       <= {prog_data,address[7:0]};
                          end
                     else
                     if( absolute  )
                       begin
                        address               <= {prog_data,8'h00}  + {7'b0000000,address[8:0]};
                        if((ins_type == `ins_type_read) || (ins_type == `ins_type_rmw))
                           begin
                           rd             <= 1'b1;
                           end
                          end
 
 
                    end
 
 
 
 
 
 
 
              default:
             begin
            prog_counter    <=  prog_counter;
            pg0_add         <=  pg0_add;
            pg0_wr          <=  pg0_wr;
            pg0_rd          <=  pg0_rd;
            alu_enable      <=  alu_enable;
            operand         <=  operand;
            imm_data        <=  imm_data;
            address         <=  address;
            rd          <=  rd;
            fetch_op        <=  fetch_op;
            wr          <=  wr;
            data_out        <=  data_out;
            offset          <=  offset;
        end
            endcase // case (state)
           end
 
 
 
    else begin
            case (state)
 
                `RESET:
                    begin
                     prog_counter             <=  {VEC_TABLE,vector};
                    end
 
                `FETCH_OP:
                    begin
                     prog_counter             <= next_pc;
                    end
 
                `EXECUTE:
                    begin
                       alu_enable             <= 1'b0;
                       wr                 <= 1'b0;
                       pg0_wr                 <= 1'b0;
                     if(immediate)
                       begin
                       prog_counter           <= next_pc;
                       imm_data               <= prog_data;
                       alu_enable             <= 1'b1;
                       fetch_op               <= 1'b1;
                       end
                     else
                     if(zero_page  )
                       begin
                       prog_counter           <= next_pc;
                       address                <= {8'h00,p_indexed[7:0]};
                       pg0_add                <= p_indexed[7:0];
                       alu_enable             <= 1'b1;
                       fetch_op               <= 1'b1;
                       if((ins_type == `ins_type_read) || (ins_type == `ins_type_rmw))
                          begin
                          pg0_rd              <= 1'b1;
                          end
                       end
                     else
                     if( absolute || jump  || jsr || jump_indirect)
                       begin
                       prog_counter           <= next_pc;
                       address                <= {7'b0000000,p_indexed};
                       pg0_add                <= p_indexed[7:0];
                       end
                     else
                     if( relative )
                       begin
                         fetch_op             <= 1'b1;
                         alu_enable           <= 1'b1;
                         if(branch_inst)
                         prog_counter         <= prog_counter + 1'b1 + { prog_data[7],prog_data[7],prog_data[7],prog_data[7],
                                                 prog_data[7],prog_data[7],prog_data[7],prog_data[7],prog_data} ;
                         else
                         prog_counter         <= next_pc;
                       end
                     else
 
                     if( rts || rti)
                       begin
                       prog_counter           <= stk_pull_data;
                       end
                     else
 
                     if( stack )
                       begin
                       prog_counter           <= next_pc;
                        if(ins_type == `ins_type_read )
                         begin
                         operand              <= stk_pull_data[7:0];
                         end
                       end
                     else
 
                     if(indirectx  )
                       begin
                       prog_counter           <= next_pc;
                       pg0_add                <= p_indexed[7:0];
                       pg0_rd                 <= 1'b1;
                       end
                     else
                     if(indirecty  )
                       begin
                       prog_counter           <= next_pc;
                       pg0_add                <= prog_data;
                       pg0_rd                 <= 1'b1;
                       end
                     else
                      prog_counter            <= next_pc;
                    end
 
 
 
                `EXE_1:
                    begin
                     if(immediate )
                       begin
                        fetch_op              <=  1'b0;
                        prog_counter          <= next_pc;
                        alu_enable            <= 1'b0;
                        end
                     else
                     if(zero_page  )
                       begin
                        fetch_op              <=  1'b0;
                        prog_counter          <= next_pc;
                        rd                <= 1'b0;
                        wr                <= 1'b0;
                        pg0_rd                <= 1'b0;
                        operand               <= data_in;
                        alu_enable            <= 1'b0;
                       if((ins_type == `ins_type_write ) || (ins_type == `ins_type_rmw ))
                          begin
                          pg0_wr              <= 1'b1;
                          data_out            <= alu_result;
                          end
                        end
                     else
                     if( relative )
                       begin
                          fetch_op            <= 1'b0;
                          alu_enable          <= 1'b0;
                          prog_counter        <= next_pc;
                          end
                     else
                     prog_counter            <= next_pc;
                    end
 
 
 
                `AXE_1:
                    begin
                     if(absolute  )
                       begin
                        fetch_op              <=  1'b1;
                        prog_counter          <= prog_counter;
                        alu_enable            <= 1'b1;
                        end
                     else
                     if(  jump || jsr)
                       begin
                          fetch_op           <=  1'b1;
                          prog_counter       <= prog_counter;
                          end
                     else
                     if( jump_indirect )
                          begin
                          prog_counter       <= next_pc;
                          address            <= {prog_data,address[7:0]};
                          end
                     else
                     prog_counter            <= next_pc;
                    end
 
 
 
 
 
 
 
                `AXE_2:
                     begin
                     fetch_op          <= 1'b0;
                     prog_counter      <= next_pc;
                     rd            <= 1'b0;
                     pg0_rd            <= 1'b0;
                     operand           <= data_in;
                     alu_enable        <= 1'b0;
                     if(absolute  )
                       begin
                        if((ins_type == `ins_type_rmw ) || (ins_type == `ins_type_write ))
                           begin
                           wr       <= 1'b1;
                           data_out     <= alu_result;
                           end
                       end
                     end
 
 
 
 
 
                `IDX_1:
                     begin
                     prog_counter     <= prog_counter;
                     address[7:0]     <= pg0_data;
                     pg0_add          <= pg0_add + 1'b1;
                     pg0_rd           <= 1'b1;
                     end
 
 
                `IDX_2:
                     begin
                     prog_counter     <= prog_counter;
                     address[15:8]    <= pg0_data;
                     pg0_add          <= address[7:0];
                     alu_enable       <= 1'b1;
                     fetch_op         <= 1'b1;
                     if( ins_type == `ins_type_read)
                          begin
                          rd      <= 1'b1;
                          pg0_rd      <= 1'b1;
                          end
                     else
                     if(ins_type == `ins_type_write )
                          begin
                          wr       <= 1'b1;
                          pg0_rd       <= 1'b0;
                          data_out     <= alu_result;
                          end
                     end
 
                `IDX_3:
                     begin
                     fetch_op         <= 1'b0;
                     prog_counter     <= next_pc;
                     alu_enable       <= 1'b0;
                     rd           <= 1'b0;
                     wr           <= 1'b0;
                     pg0_rd           <= 1'b0;
                     pg0_wr           <= 1'b0;
 
                     end
 
                `IDY_1:
                     begin
                     prog_counter    <= prog_counter;
                     address[8:0]    <= pg0_data + index;
                     pg0_add         <= pg0_add + 1'b1;
                     pg0_rd          <= 1'b1;
                     end
 
 
                `IDY_2:
                     begin
                     prog_counter     <= prog_counter;
                     address[15:8]    <= pg0_data + {7'b0,address[8]} ;
                     pg0_add          <= address[7:0];
                     pg0_rd           <= 1'b0;
                     alu_enable       <= 1'b1;
                     fetch_op         <=  1'b1;
                     if( ins_type == `ins_type_read)
                          begin
                          rd      <= 1'b1;
                          pg0_rd      <= 1'b1;
                          end
                     else
                     if(ins_type == `ins_type_write )
                       begin
                          pg0_rd      <= 1'b0;
                          wr      <= 1'b1;
                          data_out    <= alu_result;
                          end
                     end
 
 
                `IDY_3:
                     begin
                     fetch_op         <=  1'b0;
                     prog_counter     <= next_pc;
                     alu_enable       <= 1'b0;
                     rd           <= 1'b0;
                     wr           <= 1'b0;
                     pg0_rd           <= 1'b0;
                     pg0_wr           <= 1'b0;
 
                     end
 
 
 
                `INT_1:
                    begin
                    alu_enable               <= 1'b0;
                    if(cmd == `cmd_load_vec)
                       begin
                       address               <=  16'h0000;
                       rd                <=  1'b0;
                       prog_counter          <=  {VEC_TABLE,vector};
                       end
                    else
                       begin
                       prog_counter          <=  prog_data16;
                       end
                    end
 
 
 
 
                `INT_2:
                    begin
                     address               <=  16'h0000;
                     rd                <=  1'b0;
                     prog_counter          <=  prog_data16;
                    end
 
 
 
 
                `HALT:
                    begin
                    address                <= 16'h0000;
                    rd                 <= 1'b0;
                    wr                 <= 1'b0;
                    end
 
                default:
                  begin
                    address                <= 16'h0000;
                    prog_counter           <= 16'h0000;
                    rd                 <= 1'b0;
                    wr                 <= 1'b0;
                end
            endcase
        end
    end
 
 
 
 
 
 
 
 
 
endmodule
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [sequencer] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`SEQUENCER
3
4			`#(parameter VEC_TABLE = 8'hff,`
5			`parameter STATE_SIZE=3`
6			`)`
7
8			`(`
9
10			`input wire clk,`
11			`input wire reset,`
12			`input wire enable,`
13			`input wire now_fetch_op,`
14			`input wire [STATE_SIZE:0] state, // current and next state registers`
15			`input wire [1:0] cmd,`
16			`input wire [7:0] vector,`
17			`input wire [1:0] length,`
18			`input wire [7:0] alu_a,`
19			`input wire [7:0] alu_result, // result from alu operation`
20			`input wire [7:0] alu_status, //`
21			`input wire [7:0] data_in, // data that comes from the bus controller`
22			`input wire [15:0] prog_data16, // data that comes from the bus controller`
23			`input wire [7:0] prog_data,`
24			`input wire [7:0] pg0_data,`
25			`input wire [7:0] index, // selected index`
26
27			`input wire [1:0] ins_type,`
28			`input wire [2:0] alu_op_a_sel,`
29
30			`input wire implied,`
31			`input wire immediate,`
32			`input wire relative,`
33			`input wire absolute,`
34			`input wire zero_page,`
35			`input wire indirectx,`
36			`input wire indirecty,`
37			`input wire stack,`
38			`input wire jump_indirect,`
39
40			`input wire brk,`
41			`input wire rti,`
42			`input wire rts,`
43			`input wire jump,`
44			`input wire jsr,`
45
46			`input wire branch_inst,`
47
48
49			`output reg fetch_op,`
50			`output reg [15:0] prog_counter, // program counter`
51
52
53			`output reg [15:0] address, // system bus address`
54			`output reg alu_enable,`
55
56			`output reg [7:0] pg0_add,`
57			`output reg pg0_wr,`
58			`output reg pg0_rd,`
59
60
61			`output reg [7:0] operand,`
62			`output reg [7:0] imm_data,`
63			`output reg rd, // read = 1`
64			`output reg wr, // write = 1`
65			`output reg [7:0] data_out, // data that will be written somewhere else`
66
67
68			`output reg [15:0] offset,`
69
70			`output reg stk_push,`
71			`output reg [15:0] stk_push_data,`
72			`output reg stk_pull,`
73			`input wire [15:0] stk_pull_data`
74			`);`
75
76
77
78
79
80
81			`reg stk_push_p;`
82
83
84
85
86			`wire [15:0] next_pc; // a simple logic to add one to the PC`
87			`wire [8:0] p_indexed;`
88
89			`assign next_pc = prog_counter + 16'b0000000000000001;`
90			`assign p_indexed = prog_data +index;`
91
92
93
94			`always @ (posedge clk )`
95			`if (reset) stk_push <= 1'b1;`
96			`else stk_push <= stk_push_p \|\|`
97			(stack && !enable && (state == `EXECUTE ) && (ins_type == `ins_type_write )) \|\|
98			( enable && (state != `INT_1 ) && now_fetch_op && (cmd == `cmd_load_vec)) ;
99
100
101
102
103
104
105
106
107			`always @ (posedge clk ) begin`
108			`if (reset)`
109			`begin`
110			`stk_push_p <= 1'b0;`
111
112			`end`
113			`else if(!enable)`
114			`begin`
115			`stk_push_p <= 1'b0;`
116			`end`
117			`else begin`
118			`case (state)`
119
120			`EXECUTE:
121			`begin`
122			`if( jsr )`
123			`begin`
124			`stk_push_p <= 1'b1;`
125			`end`
126			`end`
127
128			`default:`
129			`begin`
130			`stk_push_p <= 1'b0;`
131			`end`
132			`endcase`
133			`end`
134			`end`
135
136
137
138
139
140
141
142
143			`always @ (posedge clk ) begin`
144			`if (reset)`
145			`begin`
146			`stk_pull <= 1'b0;`
147
148			`end`
149			`else if( enable)`
150			`begin`
151			`stk_pull <= 1'b0;`
152			`end`
153			`else begin`
154			`case (state)`
155
156
157			`EXECUTE:
158			`begin`
159			`if( rts \|\| rti)`
160			`begin`
161			`stk_pull <= 1'b1;`
162			`end`
163			`else`
164			`if( stack )`
165			`begin`
166			if(ins_type == `ins_type_read )
167			`begin`
168			`stk_pull <= 1'b1;`
169			`end`
170			`end`
171
172			`end`
173
174			`default:`
175			`begin`
176			`stk_pull <= 1'b0;`
177			`end`
178			`endcase`
179			`end`
180			`end`
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195			`always @ (posedge clk )`
196			`begin`
197			`if (reset) stk_push_data <= 16'h0000;`
198			`else`
199			if((state == `AXE_1) && jsr ) stk_push_data <= prog_counter;
200			`else`
201			if((cmd == `cmd_load_vec) && now_fetch_op ) stk_push_data <= prog_counter;
202			else stk_push_data <= (alu_op_a_sel == `alu_op_a_psr)? {alu_status,alu_status}:{alu_a,alu_a};
203			`end`
204
205
206
207
208
209			`always @ (posedge clk )`
210			`begin`
211			`if (reset)`
212			`begin`
213			`prog_counter <= 16'h0000;`
214			`alu_enable <= 1'b0;`
215			`pg0_add <= 8'h00;`
216			`pg0_wr <= 1'b0;`
217			`pg0_rd <= 1'b0;`
218			`fetch_op <= 1'b0;`
219			`operand <= 8'h00;`
220			`imm_data <= 8'h00;`
221			`address <= 16'h0000;`
222			`rd <= 1'b0;`
223			`wr <= 1'b0;`
224			`data_out <= 8'h00;`
225			`offset <= 16'h0000;`
226			`end // if (reset)`
227			`else if(!enable)`
228
229
230
231
232
233			`begin`
234			`case (state)`
235
236
237
238			`EXECUTE:
239			`begin`
240			`if( jump \|\| jsr \|\| absolute)`
241			`begin`
242			`prog_counter <= next_pc;`
243			`end`
244
245			`end`
246
247
248
249			`AXE_1:
250			`begin`
251
252			`if( jump \|\| jsr )`
253			`begin`
254			`prog_counter <= {prog_data,address[7:0]};`
255			`end`
256			`else`
257			`if( absolute )`
258			`begin`
259			`address <= {prog_data,8'h00} + {7'b0000000,address[8:0]};`
260			if((ins_type == `ins_type_read) \|\| (ins_type == `ins_type_rmw))
261			`begin`
262			`rd <= 1'b1;`
263			`end`
264			`end`
265
266
267			`end`
268
269
270
271
272
273
274
275			`default:`
276			`begin`
277			`prog_counter <= prog_counter;`
278			`pg0_add <= pg0_add;`
279			`pg0_wr <= pg0_wr;`
280			`pg0_rd <= pg0_rd;`
281			`alu_enable <= alu_enable;`
282			`operand <= operand;`
283			`imm_data <= imm_data;`
284			`address <= address;`
285			`rd <= rd;`
286			`fetch_op <= fetch_op;`
287			`wr <= wr;`
288			`data_out <= data_out;`
289			`offset <= offset;`
290			`end`
291			`endcase // case (state)`
292			`end`
293
294
295
296			`else begin`
297			`case (state)`
298
299			`RESET:
300			`begin`
301			`prog_counter <= {VEC_TABLE,vector};`
302			`end`
303
304			`FETCH_OP:
305			`begin`
306			`prog_counter <= next_pc;`
307			`end`
308
309			`EXECUTE:
310			`begin`
311			`alu_enable <= 1'b0;`
312			`wr <= 1'b0;`
313			`pg0_wr <= 1'b0;`
314			`if(immediate)`
315			`begin`
316			`prog_counter <= next_pc;`
317			`imm_data <= prog_data;`
318			`alu_enable <= 1'b1;`
319			`fetch_op <= 1'b1;`
320			`end`
321			`else`
322			`if(zero_page )`
323			`begin`
324			`prog_counter <= next_pc;`
325			`address <= {8'h00,p_indexed[7:0]};`
326			`pg0_add <= p_indexed[7:0];`
327			`alu_enable <= 1'b1;`
328			`fetch_op <= 1'b1;`
329			if((ins_type == `ins_type_read) \|\| (ins_type == `ins_type_rmw))
330			`begin`
331			`pg0_rd <= 1'b1;`
332			`end`
333			`end`
334			`else`
335			`if( absolute \|\| jump \|\| jsr \|\| jump_indirect)`
336			`begin`
337			`prog_counter <= next_pc;`
338			`address <= {7'b0000000,p_indexed};`
339			`pg0_add <= p_indexed[7:0];`
340			`end`
341			`else`
342			`if( relative )`
343			`begin`
344			`fetch_op <= 1'b1;`
345			`alu_enable <= 1'b1;`
346			`if(branch_inst)`
347			`prog_counter <= prog_counter + 1'b1 + { prog_data[7],prog_data[7],prog_data[7],prog_data[7],`
348			`prog_data[7],prog_data[7],prog_data[7],prog_data[7],prog_data} ;`
349			`else`
350			`prog_counter <= next_pc;`
351			`end`
352			`else`
353
354			`if( rts \|\| rti)`
355			`begin`
356			`prog_counter <= stk_pull_data;`
357			`end`
358			`else`
359
360			`if( stack )`
361			`begin`
362			`prog_counter <= next_pc;`
363			if(ins_type == `ins_type_read )
364			`begin`
365			`operand <= stk_pull_data[7:0];`
366			`end`
367			`end`
368			`else`
369
370			`if(indirectx )`
371			`begin`
372			`prog_counter <= next_pc;`
373			`pg0_add <= p_indexed[7:0];`
374			`pg0_rd <= 1'b1;`
375			`end`
376			`else`
377			`if(indirecty )`
378			`begin`
379			`prog_counter <= next_pc;`
380			`pg0_add <= prog_data;`
381			`pg0_rd <= 1'b1;`
382			`end`
383			`else`
384			`prog_counter <= next_pc;`
385			`end`
386
387
388
389			`EXE_1:
390			`begin`
391			`if(immediate )`
392			`begin`
393			`fetch_op <= 1'b0;`
394			`prog_counter <= next_pc;`
395			`alu_enable <= 1'b0;`
396			`end`
397			`else`
398			`if(zero_page )`
399			`begin`
400			`fetch_op <= 1'b0;`
401			`prog_counter <= next_pc;`
402			`rd <= 1'b0;`
403			`wr <= 1'b0;`
404			`pg0_rd <= 1'b0;`
405			`operand <= data_in;`
406			`alu_enable <= 1'b0;`
407			if((ins_type == `ins_type_write ) \|\| (ins_type == `ins_type_rmw ))
408			`begin`
409			`pg0_wr <= 1'b1;`
410			`data_out <= alu_result;`
411			`end`
412			`end`
413			`else`
414			`if( relative )`
415			`begin`
416			`fetch_op <= 1'b0;`
417			`alu_enable <= 1'b0;`
418			`prog_counter <= next_pc;`
419			`end`
420			`else`
421			`prog_counter <= next_pc;`
422			`end`
423
424
425
426			`AXE_1:
427			`begin`
428			`if(absolute )`
429			`begin`
430			`fetch_op <= 1'b1;`
431			`prog_counter <= prog_counter;`
432			`alu_enable <= 1'b1;`
433			`end`
434			`else`
435			`if( jump \|\| jsr)`
436			`begin`
437			`fetch_op <= 1'b1;`
438			`prog_counter <= prog_counter;`
439			`end`
440			`else`
441			`if( jump_indirect )`
442			`begin`
443			`prog_counter <= next_pc;`
444			`address <= {prog_data,address[7:0]};`
445			`end`
446			`else`
447			`prog_counter <= next_pc;`
448			`end`
449
450
451
452
453
454
455
456			`AXE_2:
457			`begin`
458			`fetch_op <= 1'b0;`
459			`prog_counter <= next_pc;`
460			`rd <= 1'b0;`
461			`pg0_rd <= 1'b0;`
462			`operand <= data_in;`
463			`alu_enable <= 1'b0;`
464			`if(absolute )`
465			`begin`
466			if((ins_type == `ins_type_rmw ) \|\| (ins_type == `ins_type_write ))
467			`begin`
468			`wr <= 1'b1;`
469			`data_out <= alu_result;`
470			`end`
471			`end`
472			`end`
473
474
475
476
477
478			`IDX_1:
479			`begin`
480			`prog_counter <= prog_counter;`
481			`address[7:0] <= pg0_data;`
482			`pg0_add <= pg0_add + 1'b1;`
483			`pg0_rd <= 1'b1;`
484			`end`
485
486
487			`IDX_2:
488			`begin`
489			`prog_counter <= prog_counter;`
490			`address[15:8] <= pg0_data;`
491			`pg0_add <= address[7:0];`
492			`alu_enable <= 1'b1;`
493			`fetch_op <= 1'b1;`
494			if( ins_type == `ins_type_read)
495			`begin`
496			`rd <= 1'b1;`
497			`pg0_rd <= 1'b1;`
498			`end`
499			`else`
500			if(ins_type == `ins_type_write )
501			`begin`
502			`wr <= 1'b1;`
503			`pg0_rd <= 1'b0;`
504			`data_out <= alu_result;`
505			`end`
506			`end`
507
508			`IDX_3:
509			`begin`
510			`fetch_op <= 1'b0;`
511			`prog_counter <= next_pc;`
512			`alu_enable <= 1'b0;`
513			`rd <= 1'b0;`
514			`wr <= 1'b0;`
515			`pg0_rd <= 1'b0;`
516			`pg0_wr <= 1'b0;`
517
518			`end`
519
520			`IDY_1:
521			`begin`
522			`prog_counter <= prog_counter;`
523			`address[8:0] <= pg0_data + index;`
524			`pg0_add <= pg0_add + 1'b1;`
525			`pg0_rd <= 1'b1;`
526			`end`
527
528
529			`IDY_2:
530			`begin`
531			`prog_counter <= prog_counter;`
532			`address[15:8] <= pg0_data + {7'b0,address[8]} ;`
533			`pg0_add <= address[7:0];`
534			`pg0_rd <= 1'b0;`
535			`alu_enable <= 1'b1;`
536			`fetch_op <= 1'b1;`
537			if( ins_type == `ins_type_read)
538			`begin`
539			`rd <= 1'b1;`
540			`pg0_rd <= 1'b1;`
541			`end`
542			`else`
543			if(ins_type == `ins_type_write )
544			`begin`
545			`pg0_rd <= 1'b0;`
546			`wr <= 1'b1;`
547			`data_out <= alu_result;`
548			`end`
549			`end`
550
551
552			`IDY_3:
553			`begin`
554			`fetch_op <= 1'b0;`
555			`prog_counter <= next_pc;`
556			`alu_enable <= 1'b0;`
557			`rd <= 1'b0;`
558			`wr <= 1'b0;`
559			`pg0_rd <= 1'b0;`
560			`pg0_wr <= 1'b0;`
561
562			`end`
563
564
565
566			`INT_1:
567			`begin`
568			`alu_enable <= 1'b0;`
569			if(cmd == `cmd_load_vec)
570			`begin`
571			`address <= 16'h0000;`
572			`rd <= 1'b0;`
573			`prog_counter <= {VEC_TABLE,vector};`
574			`end`
575			`else`
576			`begin`
577			`prog_counter <= prog_data16;`
578			`end`
579			`end`
580
581
582
583
584			`INT_2:
585			`begin`
586			`address <= 16'h0000;`
587			`rd <= 1'b0;`
588			`prog_counter <= prog_data16;`
589			`end`
590
591
592
593
594			`HALT:
595			`begin`
596			`address <= 16'h0000;`
597			`rd <= 1'b0;`
598			`wr <= 1'b0;`
599			`end`
600
601			`default:`
602			`begin`
603			`address <= 16'h0000;`
604			`prog_counter <= 16'h0000;`
605			`rd <= 1'b0;`
606			`wr <= 1'b0;`
607			`end`
608			`endcase`
609			`end`
610			`end`
611
612
613
614
615
616
617
618
619
620			`endmodule`
621
622
623