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    localparam STATE_SIZE = 3;
 
 
    wire    [7:0]   ir;                       // instruction register
    wire    [1:0]   length;                   // instruction length
 
    wire    [STATE_SIZE:0]   state;          // current and next state registers
 
    wire    [2:0]   dest;
    wire    [2:0]   ctrl;
 
    wire   [7:0]   vector;
 
    wire    [7:0]   operand  ;
    wire    [7:0]   imm_data;     //
    reg     [7:0]   index;         // will be assigned with either X or Y
    wire    [15:0]  offset;
 
   wire     now_fetch_op;
 
    // wiring that simplifies the FSM logic by simplifying the addressing modes
    wire absolute;
    wire immediate;
    wire implied;
    wire indirectx;
    wire indirecty;
    wire relative;
    wire zero_page;
    wire stack;
 
    wire fetch_op;
 
 
    wire [1:0] ins_type;
 
    wire jump;
    wire jump_indirect;
 
    // regs for the special instructions
    wire brk;
    wire rti;
    wire rts;
    wire jsr;
 
    wire invalid;
    wire core_reset;
 
 
    wire branch_inst;     // a simple reg that is asserted everytime a branch will be executed.
    wire [7:0] brn_value;
    wire [7:0] brn_enable;
    wire [4:0] alu_status_update;
 
    wire [2:0]      alu_op_a_sel;
    wire [1:0]      alu_op_b_sel;
 
    wire     alu_op_b_inv;
    wire [1:0]     alu_op_c_sel;
    wire [2:0]      alu_mode;
 
    wire [1:0]     idx_sel;
 
 
    wire    [7:0]   alu_result;    // result from alu operation
 
 
    wire    [7:0]   alu_a;         // alu accumulator
    wire    [7:0]   alu_x;         // alu x index register
    wire    [7:0]   alu_y;         // alu y index register
 
     reg    [7:0]   alu_op_b;
 
    wire            alu_enable;     // a flag that when high tells the alu when to perform the operations
    wire            alu_enable_s;
    wire        Error;
 
    wire    [1:0]   cmd;
 
assign alu_enable =  ((alu_enable_s || implied || stack  ) && !((state == `INT_1)||  (state == `INT_2) )              );
 
 
 
`VARIANT`CONTROL
#( .BOOT_VEC (BOOT_VEC),
   .STATE_SIZE(STATE_SIZE)
)
control(
   .clk               ( clk               ),
   .reset             ( reset             ),
   .enable            ( enable            ),
   .state             ( state             ),
   .ir                ( ir                ),
   .nmi               ( nmi               ),
   .vec_int           ( vec_int           ),
   .invalid           ( invalid           ),
   .run_status        ( alu_status[5]     ),
   .irq_status        ( alu_status[2]     ),
   .brk_status        ( alu_status[4]     ),
   .cmd               ( cmd               ),
   .ctrl              ( ctrl              ),
   .address           ( addr          ),
   .branch_inst       ( branch_inst       ),
   .vector            ( vector            ),
   .core_reset        ( core_reset        )
);
 
 
`VARIANT`STATE_FSM
#(.STATE_SIZE(STATE_SIZE))
state_fsm (
   .clk               ( clk               ),
   .reset             ( core_reset        ),
   .enable            ( enable            ),
   .cmd               ( cmd               ),
   .now_fetch_op      ( now_fetch_op      ),
   .run               ( alu_status[5]     ),
   .length            ( length            ),
   .immediate         ( immediate         ),
   .absolute          ( absolute          ),
   .stack             ( stack             ),
   .relative          ( relative          ),
   .implied           ( implied           ),
   .indirectx         ( indirectx         ),
   .indirecty         ( indirecty         ),
   .brk               ( brk               ),
   .rts               ( rts               ),
   .jump_indirect     ( jump_indirect     ),
   .jump              ( jump              ),
   .jsr               ( jsr               ),
   .rti               ( rti               ),
   .branch_inst       ( branch_inst       ),
   .ins_type          ( ins_type          ),
   .invalid           ( invalid           ),
   .state             ( state             )
 
);
 
`VARIANT`INST_DECODE
#(.STATE_SIZE(STATE_SIZE))
inst_decode (
   .clk               ( clk               ),
   .reset             ( reset             ),
   .enable            ( enable            ),
   .disable_ir        ((state == `INT_1) || (state == `INT_2) ),
   .now_fetch_op      ( now_fetch_op      ),
   .fetch_op          ( fetch_op          ),
   .state             ( state             ),
   .prog_data         ( prog_counter[0]? prog_data[15:8]:prog_data[7:0]),
 
   .length            ( length            ),
   .ir                ( ir                ),
   .absolute          ( absolute          ),
   .immediate         ( immediate         ),
   .implied           ( implied           ),
   .indirectx         ( indirectx         ),
   .indirecty         ( indirecty         ),
   .relative          ( relative          ),
   .zero_page         ( zero_page         ),
   .stack             ( stack             ),
   .jump              ( jump              ),
   .jump_indirect     ( jump_indirect     ),
   .brk               ( brk               ),
   .rti               ( rti               ),
   .rts               ( rts               ),
   .jsr               ( jsr               ),
   .ins_type          ( ins_type          ),
   .alu_mode          ( alu_mode          ),
   .alu_op_a_sel      ( alu_op_a_sel      ),
   .alu_op_b_sel      ( alu_op_b_sel      ),
   .alu_op_b_inv      ( alu_op_b_inv      ),
   .alu_op_c_sel      ( alu_op_c_sel      ),
   .idx_sel           ( idx_sel           ),
   .alu_status_update ( alu_status_update ),
   .brn_value         ( brn_value         ),
   .brn_enable        ( brn_enable        ),
   .dest              ( dest              ),
   .ctrl              ( ctrl              ),
   .invalid           ( invalid           )
 );
 
 
   reg     last_prg_cnt_0;
 
   always@(posedge clk )
          last_prg_cnt_0 <= prog_counter[0];
 
`VARIANT`SEQUENCER
#( .VEC_TABLE (VEC_TABLE),
   .STATE_SIZE(STATE_SIZE))
 
sequencer (
   .clk               ( clk               ),
   .reset             ( reset             ),
   .enable            ( enable            ),
   .now_fetch_op      ( now_fetch_op      ),
   .cmd               ( cmd               ),
   .state             ( state             ),
   .length            ( length            ),
   .vector            ( vector            ),
   .alu_result        ( alu_result        ),
   .alu_a             ( alu_a             ),
   .alu_status        ( alu_status        ),
   .alu_enable        ( alu_enable_s      ),
   .alu_op_a_sel      ( alu_op_a_sel      ),
   .pg0_data          ( pg0_data          ),
   .data_in           ( addr[0]? rdata[15:8]: rdata[7:0]),
   .prog_data16       ( prog_data         ),
   .index             ( index             ),
   .prog_data         ( last_prg_cnt_0? prog_data[15:8]:prog_data[7:0]),
   .implied           ( implied           ),
   .fetch_op          ( fetch_op          ),
   .immediate         ( immediate         ),
   .relative          ( relative          ),
   .absolute          ( absolute          ),
   .zero_page         ( zero_page         ),
   .stack             ( stack             ),
   .indirectx         ( indirectx         ),
   .indirecty         ( indirecty         ),
   .jump_indirect     ( jump_indirect     ),
   .jump              ( jump              ),
   .jsr               ( jsr               ),
   .brk               ( brk               ),
   .rti               ( rti               ),
   .rts               ( rts               ),
   .branch_inst       ( branch_inst       ),
   .ins_type          ( ins_type          ),
   .prog_counter      ( prog_counter      ),
   .address           ( addr          ),
   .operand           ( operand           ),
   .imm_data          ( imm_data          ),
 
   .pg0_add           ( pg0_add           ),
   .pg0_rd            ( pg0_rd            ),
   .pg0_wr            ( pg0_wr            ),
 
 
 
   .rd            ( rd            ),
   .wr            ( wr            ),
   .data_out          ( wdata         ),
   .offset            ( offset            ),
   .stk_push          ( stk_push          ),
   .stk_push_data     ( stk_push_data     ),
   .stk_pull          ( stk_pull          ),
   .stk_pull_data     ( stk_pull_data     )
 
 
);
 
 
always@(*)
 
  case (idx_sel)
    `idx_sel_00:          index  = 8'h00;
    `idx_sel_x:           index  = alu_x;
    `idx_sel_y:           index  = alu_y;
     default:             index  = 8'bxxxxxxxx;
  endcase
 
 
reg [7:0]     mem_dat;
 
always@(*) mem_dat  = addr[0] ? rdata[15:8] : rdata[7:0];
 
 
always@(*)
 
  case (alu_op_b_sel)
    `alu_op_b_00:         alu_op_b  = 8'h00;
    `alu_op_b_imm:        alu_op_b  = imm_data;
    `alu_op_b_stk:        alu_op_b  = stk_pull_data[7:0];
    `alu_op_b_opnd:       alu_op_b  = mem_dat;
  endcase
 
 
`VARIANT`ALU
alu (
    .clk                ( clk                 ),
    .reset              ( reset               ),
    .enable             ( enable              ),
    .alu_enable         ( alu_enable          ),
    .alu_result         ( alu_result          ),
    .alu_status         ( alu_status          ),
    .alu_op_b           ( alu_op_b            ),
    .psp_res            ( stk_pull_data[15:8] ),
    .alu_mode           ( alu_mode            ),
    .alu_op_a_sel       ( alu_op_a_sel        ),
    .alu_op_b_inv       ( alu_op_b_inv        ),
    .alu_op_c_sel       ( alu_op_c_sel        ),
    .alu_status_update  ( alu_status_update   ),
    .branch_inst        ( branch_inst         ),
    .relative           ( relative            ),
    .dest               ( dest                ),
    .brn_enable         ( brn_enable          ),
    .brn_value          ( brn_value           ),
    .alu_x              ( alu_x               ),
    .alu_y              ( alu_y               ),
    .alu_a              ( alu_a               )
    );
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`localparam STATE_SIZE = 3;`
3
4
5			`wire [7:0] ir; // instruction register`
6			`wire [1:0] length; // instruction length`
7
8			`wire [STATE_SIZE:0] state; // current and next state registers`
9
10			`wire [2:0] dest;`
11			`wire [2:0] ctrl;`
12
13			`wire [7:0] vector;`
14
15			`wire [7:0] operand ;`
16			`wire [7:0] imm_data; //`
17			`reg [7:0] index; // will be assigned with either X or Y`
18			`wire [15:0] offset;`
19
20			`wire now_fetch_op;`
21
22			`// wiring that simplifies the FSM logic by simplifying the addressing modes`
23			`wire absolute;`
24			`wire immediate;`
25			`wire implied;`
26			`wire indirectx;`
27			`wire indirecty;`
28			`wire relative;`
29			`wire zero_page;`
30			`wire stack;`
31
32			`wire fetch_op;`
33
34
35			`wire [1:0] ins_type;`
36
37			`wire jump;`
38			`wire jump_indirect;`
39
40			`// regs for the special instructions`
41			`wire brk;`
42			`wire rti;`
43			`wire rts;`
44			`wire jsr;`
45
46			`wire invalid;`
47			`wire core_reset;`
48
49
50			`wire branch_inst; // a simple reg that is asserted everytime a branch will be executed.`
51			`wire [7:0] brn_value;`
52			`wire [7:0] brn_enable;`
53			`wire [4:0] alu_status_update;`
54
55			`wire [2:0] alu_op_a_sel;`
56			`wire [1:0] alu_op_b_sel;`
57
58			`wire alu_op_b_inv;`
59			`wire [1:0] alu_op_c_sel;`
60			`wire [2:0] alu_mode;`
61
62			`wire [1:0] idx_sel;`
63
64
65			`wire [7:0] alu_result; // result from alu operation`
66
67
68			`wire [7:0] alu_a; // alu accumulator`
69			`wire [7:0] alu_x; // alu x index register`
70			`wire [7:0] alu_y; // alu y index register`
71
72			`reg [7:0] alu_op_b;`
73
74			`wire alu_enable; // a flag that when high tells the alu when to perform the operations`
75			`wire alu_enable_s;`
76			`wire Error;`
77
78			`wire [1:0] cmd;`
79
80			assign alu_enable = ((alu_enable_s \|\| implied \|\| stack ) && !((state == `INT_1)\|\| (state == `INT_2) ) );
81
82
83
84			`VARIANT`CONTROL
85			`#( .BOOT_VEC (BOOT_VEC),`
86			`.STATE_SIZE(STATE_SIZE)`
87			`)`
88			`control(`
89			`.clk ( clk ),`
90			`.reset ( reset ),`
91			`.enable ( enable ),`
92			`.state ( state ),`
93			`.ir ( ir ),`
94			`.nmi ( nmi ),`
95			`.vec_int ( vec_int ),`
96			`.invalid ( invalid ),`
97			`.run_status ( alu_status[5] ),`
98			`.irq_status ( alu_status[2] ),`
99			`.brk_status ( alu_status[4] ),`
100			`.cmd ( cmd ),`
101			`.ctrl ( ctrl ),`
102			`.address ( addr ),`
103			`.branch_inst ( branch_inst ),`
104			`.vector ( vector ),`
105			`.core_reset ( core_reset )`
106			`);`
107
108
109			`VARIANT`STATE_FSM
110			`#(.STATE_SIZE(STATE_SIZE))`
111			`state_fsm (`
112			`.clk ( clk ),`
113			`.reset ( core_reset ),`
114			`.enable ( enable ),`
115			`.cmd ( cmd ),`
116			`.now_fetch_op ( now_fetch_op ),`
117			`.run ( alu_status[5] ),`
118			`.length ( length ),`
119			`.immediate ( immediate ),`
120			`.absolute ( absolute ),`
121			`.stack ( stack ),`
122			`.relative ( relative ),`
123			`.implied ( implied ),`
124			`.indirectx ( indirectx ),`
125			`.indirecty ( indirecty ),`
126			`.brk ( brk ),`
127			`.rts ( rts ),`
128			`.jump_indirect ( jump_indirect ),`
129			`.jump ( jump ),`
130			`.jsr ( jsr ),`
131			`.rti ( rti ),`
132			`.branch_inst ( branch_inst ),`
133			`.ins_type ( ins_type ),`
134			`.invalid ( invalid ),`
135			`.state ( state )`
136
137			`);`
138
139			`VARIANT`INST_DECODE
140			`#(.STATE_SIZE(STATE_SIZE))`
141			`inst_decode (`
142			`.clk ( clk ),`
143			`.reset ( reset ),`
144			`.enable ( enable ),`
145			.disable_ir ((state == `INT_1) \|\| (state == `INT_2) ),
146			`.now_fetch_op ( now_fetch_op ),`
147			`.fetch_op ( fetch_op ),`
148			`.state ( state ),`
149			`.prog_data ( prog_counter[0]? prog_data[15:8]:prog_data[7:0]),`
150
151			`.length ( length ),`
152			`.ir ( ir ),`
153			`.absolute ( absolute ),`
154			`.immediate ( immediate ),`
155			`.implied ( implied ),`
156			`.indirectx ( indirectx ),`
157			`.indirecty ( indirecty ),`
158			`.relative ( relative ),`
159			`.zero_page ( zero_page ),`
160			`.stack ( stack ),`
161			`.jump ( jump ),`
162			`.jump_indirect ( jump_indirect ),`
163			`.brk ( brk ),`
164			`.rti ( rti ),`
165			`.rts ( rts ),`
166			`.jsr ( jsr ),`
167			`.ins_type ( ins_type ),`
168			`.alu_mode ( alu_mode ),`
169			`.alu_op_a_sel ( alu_op_a_sel ),`
170			`.alu_op_b_sel ( alu_op_b_sel ),`
171			`.alu_op_b_inv ( alu_op_b_inv ),`
172			`.alu_op_c_sel ( alu_op_c_sel ),`
173			`.idx_sel ( idx_sel ),`
174			`.alu_status_update ( alu_status_update ),`
175			`.brn_value ( brn_value ),`
176			`.brn_enable ( brn_enable ),`
177			`.dest ( dest ),`
178			`.ctrl ( ctrl ),`
179			`.invalid ( invalid )`
180			`);`
181
182
183			`reg last_prg_cnt_0;`
184
185			`always@(posedge clk )`
186			`last_prg_cnt_0 <= prog_counter[0];`
187
188			`VARIANT`SEQUENCER
189			`#( .VEC_TABLE (VEC_TABLE),`
190			`.STATE_SIZE(STATE_SIZE))`
191
192			`sequencer (`
193			`.clk ( clk ),`
194			`.reset ( reset ),`
195			`.enable ( enable ),`
196			`.now_fetch_op ( now_fetch_op ),`
197			`.cmd ( cmd ),`
198			`.state ( state ),`
199			`.length ( length ),`
200			`.vector ( vector ),`
201			`.alu_result ( alu_result ),`
202			`.alu_a ( alu_a ),`
203			`.alu_status ( alu_status ),`
204			`.alu_enable ( alu_enable_s ),`
205			`.alu_op_a_sel ( alu_op_a_sel ),`
206			`.pg0_data ( pg0_data ),`
207			`.data_in ( addr[0]? rdata[15:8]: rdata[7:0]),`
208			`.prog_data16 ( prog_data ),`
209			`.index ( index ),`
210			`.prog_data ( last_prg_cnt_0? prog_data[15:8]:prog_data[7:0]),`
211			`.implied ( implied ),`
212			`.fetch_op ( fetch_op ),`
213			`.immediate ( immediate ),`
214			`.relative ( relative ),`
215			`.absolute ( absolute ),`
216			`.zero_page ( zero_page ),`
217			`.stack ( stack ),`
218			`.indirectx ( indirectx ),`
219			`.indirecty ( indirecty ),`
220			`.jump_indirect ( jump_indirect ),`
221			`.jump ( jump ),`
222			`.jsr ( jsr ),`
223			`.brk ( brk ),`
224			`.rti ( rti ),`
225			`.rts ( rts ),`
226			`.branch_inst ( branch_inst ),`
227			`.ins_type ( ins_type ),`
228			`.prog_counter ( prog_counter ),`
229			`.address ( addr ),`
230			`.operand ( operand ),`
231			`.imm_data ( imm_data ),`
232
233			`.pg0_add ( pg0_add ),`
234			`.pg0_rd ( pg0_rd ),`
235			`.pg0_wr ( pg0_wr ),`
236
237
238
239			`.rd ( rd ),`
240			`.wr ( wr ),`
241			`.data_out ( wdata ),`
242			`.offset ( offset ),`
243			`.stk_push ( stk_push ),`
244			`.stk_push_data ( stk_push_data ),`
245			`.stk_pull ( stk_pull ),`
246			`.stk_pull_data ( stk_pull_data )`
247
248
249			`);`
250
251
252			`always@(*)`
253
254			`case (idx_sel)`
255			`idx_sel_00: index = 8'h00;
256			`idx_sel_x: index = alu_x;
257			`idx_sel_y: index = alu_y;
258			`default: index = 8'bxxxxxxxx;`
259			`endcase`
260
261
262			`reg [7:0] mem_dat;`
263
264			`always@(*) mem_dat = addr[0] ? rdata[15:8] : rdata[7:0];`
265
266
267			`always@(*)`
268
269			`case (alu_op_b_sel)`
270			`alu_op_b_00: alu_op_b = 8'h00;
271			`alu_op_b_imm: alu_op_b = imm_data;
272			`alu_op_b_stk: alu_op_b = stk_pull_data[7:0];
273			`alu_op_b_opnd: alu_op_b = mem_dat;
274			`endcase`
275
276
277			`VARIANT`ALU
278			`alu (`
279			`.clk ( clk ),`
280			`.reset ( reset ),`
281			`.enable ( enable ),`
282			`.alu_enable ( alu_enable ),`
283			`.alu_result ( alu_result ),`
284			`.alu_status ( alu_status ),`
285			`.alu_op_b ( alu_op_b ),`
286			`.psp_res ( stk_pull_data[15:8] ),`
287			`.alu_mode ( alu_mode ),`
288			`.alu_op_a_sel ( alu_op_a_sel ),`
289			`.alu_op_b_inv ( alu_op_b_inv ),`
290			`.alu_op_c_sel ( alu_op_c_sel ),`
291			`.alu_status_update ( alu_status_update ),`
292			`.branch_inst ( branch_inst ),`
293			`.relative ( relative ),`
294			`.dest ( dest ),`
295			`.brn_enable ( brn_enable ),`
296			`.brn_value ( brn_value ),`
297			`.alu_x ( alu_x ),`
298			`.alu_y ( alu_y ),`
299			`.alu_a ( alu_a )`
300			`);`
301
302
303
304