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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [verilog/] [top.rtl] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
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5			`//=============================================================================`
6			`// Rtl Glue Logic`
7			`//=============================================================================`
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10			`assign pg0_data = pg0_add[0]?mem_rdata[15:8]:mem_rdata[7:0];`
11			`assign pg00_ram_rd = pg0_rd\|\|(mem_cs && rd);`
12			`assign pg00_ram_l_wr = (pg0_wr\|\|(mem_cs && wr)) && (!pg0_add[0]);`
13			`assign pg00_ram_h_wr = (pg0_wr\|\|(mem_cs && wr)) && ( pg0_add[0]);`
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