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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
cpu
def_tb
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      cpu_def_tb
    
  

 
 

 
 


    VEC_TABLE8'hff
    BOOT_VEC8'hfc
    CPU_ADD16
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4
    STARTUP"NONE"
    FONT"NONE"
    RAM_ADD11
    RAM_WORDS2048
    ROM_ADD12
    ROM_WORDS4096
    ROM_FILE"NONE"
    PROG_ROM_ADDROM_ADD
    PROG_ROM_WORDSROM_WORDS
    PROG_ROM_FILEROM_FILE

 
 
       
 
              
              Dut
              
              
                                   ipxact:library="Mos6502"
                                   ipxact:name="cpu"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   ipxact:library="Mos6502"
                                   ipxact:name="cpu"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 

 
 
 
 
 
 
 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.irq
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/cpu_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
    
      fs-lint
 
 
 
      
        
        ../verilog/common/cpu_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
  
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def_tb`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45	133	jt_eaton
46	135	jt_eaton
47			`gen_verilog`
48			`104.0`
49			`none`
50			`:common:`
51			`tools/verilog/gen_verilog`
52
53
54			`destination`
55			`cpu_def_tb`
56
57
58
59	131	jt_eaton
60
61	135	jt_eaton
62	131	jt_eaton
63
64	135	jt_eaton
65
66			`VEC_TABLE8'hff`
67			`BOOT_VEC8'hfc`
68			`CPU_ADD16`
69			`UART_MODEL_CLKCNT4'b1100`
70			`UART_MODEL_SIZE4`
71			`STARTUP"NONE"`
72			`FONT"NONE"`
73			`RAM_ADD11`
74			`RAM_WORDS2048`
75			`ROM_ADD12`
76			`ROM_WORDS4096`
77			`ROM_FILE"NONE"`
78			`PROG_ROM_ADDROM_ADD`
79			`PROG_ROM_WORDSROM_WORDS`
80			`PROG_ROM_FILEROM_FILE`
81
82	131	jt_eaton
83
84	135	jt_eaton
85	131	jt_eaton
86	135	jt_eaton
87			`Dut`
88
89
90			`ipxact:library="Mos6502"`
91			`ipxact:name="cpu"`
92			`ipxact:version="def_dut.params"/>`
93
94
95	131	jt_eaton
96
97
98	135	jt_eaton
99			`Bfm`
100
101			`ipxact:library="Mos6502"`
102			`ipxact:name="cpu"`
103			`ipxact:version="bfm.design"/>`
104
105	131	jt_eaton
106
107	135	jt_eaton
108			`icarus`
109
110
111			`ipxact:library="Testbench"`
112			`ipxact:name="toolflow"`
113			`ipxact:version="icarus"/>`
114
115
116	131	jt_eaton
117
118	135	jt_eaton
119			`common:common:`
120			`Verilog`
121
122
123			`fs-common`
124
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`sim:Simulation:`
130			`Verilog`
131
132
133			`fs-sim`
134
135
136	131	jt_eaton
137
138	135	jt_eaton
139			`lint:Lint:`
140			`Verilog`
141
142
143			`fs-lint`
144
145
146	131	jt_eaton
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152	135	jt_eaton
153	131	jt_eaton
154
155
156
157
158
159
160
161
162	135	jt_eaton
163	131	jt_eaton
164
165	135	jt_eaton
166			`fs-common`
167	131	jt_eaton
168
169	135	jt_eaton
170
171			`../verilog/sram.load`
172			`verilogSourcefragment`
173
174	131	jt_eaton
175
176	135	jt_eaton
177
178			`../verilog/top.rtl`
179			`verilogSourcefragment`
180
181	131	jt_eaton
182
183	135	jt_eaton
184
185			`../verilog/top.irq`
186			`verilogSourcefragment`
187
188	131	jt_eaton
189
190	135	jt_eaton
191	131	jt_eaton
192
193
194	135	jt_eaton
195			`fs-sim`
196	131	jt_eaton
197
198
199	135	jt_eaton
200
201			`../verilog/common/cpu_def_tb`
202			`verilogSourcemodule`
203
204	131	jt_eaton
205
206
207
208	135	jt_eaton
209	131	jt_eaton
210
211	135	jt_eaton
212			`fs-lint`
213	131	jt_eaton
214
215
216	135	jt_eaton
217
218			`../verilog/common/cpu_def_tb`
219			`verilogSourcemodule`
220
221	131	jt_eaton
222
223	135	jt_eaton
224	131	jt_eaton
225
226
227	135	jt_eaton
228	131	jt_eaton
229
230
231
232
233
234
235
236
237
238	135	jt_eaton