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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [sw/] [tim_2/] [tim_2.asm] - Blame information for rev 131

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         include ../io_module/io_module.asm
 
 
 
address       = $00
str_1         = $c000
 
 
             * = $f000  ; assemble start
               code
 
 
.put_c          pha
.put_cl         lda io_base+io_pic_int
                   and #$08
                   beq .put_cl
                   pla
                   sta io_base+io_uart_xmt
                   rts
 
.prtbyt            pha
                   lsr a
                   lsr a
                   lsr a
                   lsr a
                   jsr  .hexta
                   pla
 
.hexta             and #$0f
                   cmp #$0a
                   clc
                   bmi .hexta1
                   adc #$07
.hexta1            adc #$30
                   jmp .put_c
 
 
.delay             lda #$ff
                   clc
                   adc #$01
                   bne .delay
                   rts
 
 
.send_ps           sta io_base+io_ps2_data
                   lda #$64
                   sta io_base+io_utim_cnt
                   lda #$02
                   sta io_base+io_ps2_cntrl
.lp_100            lda io_base+io_utim_cnt
                   bne .lp_100
                   lda #$00
                   sta io_base+io_ps2_cntrl
 
.rcv_ps            lda io_base+io_ps2_stat
                   and #$40
                   beq .rcv_ps
                   lda io_base+io_ps2_data
                   nop
                   rts
 
 
.start             lda #$ff
                   jsr .send_ps
                   jsr .rcv_ps
                   jsr .rcv_ps
 
                   jsr .delay
                   jsr .delay
                   jsr .delay
                   jsr .delay
 
                   lda #$f3
                   jsr .send_ps
                   jsr .delay
 
                   lda #$c8
                   jsr .send_ps
                   jsr .delay
 
                   lda #$f3
                   jsr .send_ps
                   jsr .delay
 
                   lda #$64
                   jsr .send_ps
                   jsr .delay
 
                   lda #$f3
                   jsr .send_ps
                   jsr .delay
 
                   lda #$50
                   jsr .send_ps
                   jsr .delay
 
 
                   lda #$f2
                   jsr .send_ps
                   jsr .delay
 
                   jsr .rcv_ps
                   jsr .delay
 
                   lda #$e8
                   jsr .send_ps
                   jsr .delay
 
                   lda #$03
                   jsr .send_ps
                   jsr .delay
 
                   lda #$f3
                   jsr .send_ps
                   jsr .delay
 
                   lda #$28
                   jsr .send_ps
                   jsr .delay
 
                   lda #$f4
                   jsr .send_ps
 
 
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   nop
                   lda #$01
                   sta io_base+io_ps2_cntrl
 
 
 
                   lda #$c0
                   sta io_base+io_uart_cnt
                   ldx #$00
                   ldy #$00
                   lda #$fa
                   sta address
                   lda #$ff
                   sta address+1
 
.prn_add           ldy #$00
                   lda address+1
                   jsr .prtbyt
                   lda address
                   jsr .prtbyt
                   lda #$20
                   jsr .put_c
 
 
                   ldy  #$00
                   lda (address),y
                   jsr .prtbyt
                   lda #$20
                   jsr .put_c
 
                   ldx #$00
 
.lab_01            lda  str_1,X ;
                   beq .lab_80
                   jsr .put_c
                   inx
                   bne .lab_01  ;
.lab_80            lda #$0d
                   jsr .put_c
                   lda #$0a
                   jsr .put_c
 
.lab_81            lda io_base+io_ps2_xpos
                   sta io_base+io_gpio_0
                   lda io_base+io_ps2_ypos
                   sta io_base+io_gpio_1
 
                   lda io_base+io_pic_int
 
                   and #$04
                   beq .lab_81
                   lda io_base+io_uart_rcv
                   sta io_base+io_vga_ascii
                   inc address
                   bne .prn_add
                   inc address+1
                   jmp .prn_add
 
 
 
 
.irq_vec           pha
                   txa
                   tax
                   pla
                   rti
 
.nmi_vec           pha
                   pla
                   rti
 
 
             * = $fffa  ; vectors
 
 
     dw .nmi_vec               ;
     dw .start                 ;
     dw .irq_vec               ;
 
 code
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [sw/] [tim_2/] [tim_2.asm] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`include ../io_module/io_module.asm`
3
4
5
6			`address = $00`
7			`str_1 = $c000`
8
9
10			`* = $f000 ; assemble start`
11			`code`
12
13
14			`.put_c pha`
15			`.put_cl lda io_base+io_pic_int`
16			`and #$08`
17			`beq .put_cl`
18			`pla`
19			`sta io_base+io_uart_xmt`
20			`rts`
21
22			`.prtbyt pha`
23			`lsr a`
24			`lsr a`
25			`lsr a`
26			`lsr a`
27			`jsr .hexta`
28			`pla`
29
30			`.hexta and #$0f`
31			`cmp #$0a`
32			`clc`
33			`bmi .hexta1`
34			`adc #$07`
35			`.hexta1 adc #$30`
36			`jmp .put_c`
37
38
39			`.delay lda #$ff`
40			`clc`
41			`adc #$01`
42			`bne .delay`
43			`rts`
44
45
46			`.send_ps sta io_base+io_ps2_data`
47			`lda #$64`
48			`sta io_base+io_utim_cnt`
49			`lda #$02`
50			`sta io_base+io_ps2_cntrl`
51			`.lp_100 lda io_base+io_utim_cnt`
52			`bne .lp_100`
53			`lda #$00`
54			`sta io_base+io_ps2_cntrl`
55
56			`.rcv_ps lda io_base+io_ps2_stat`
57			`and #$40`
58			`beq .rcv_ps`
59			`lda io_base+io_ps2_data`
60			`nop`
61			`rts`
62
63
64			`.start lda #$ff`
65			`jsr .send_ps`
66			`jsr .rcv_ps`
67			`jsr .rcv_ps`
68
69			`jsr .delay`
70			`jsr .delay`
71			`jsr .delay`
72			`jsr .delay`
73
74			`lda #$f3`
75			`jsr .send_ps`
76			`jsr .delay`
77
78			`lda #$c8`
79			`jsr .send_ps`
80			`jsr .delay`
81
82			`lda #$f3`
83			`jsr .send_ps`
84			`jsr .delay`
85
86			`lda #$64`
87			`jsr .send_ps`
88			`jsr .delay`
89
90			`lda #$f3`
91			`jsr .send_ps`
92			`jsr .delay`
93
94			`lda #$50`
95			`jsr .send_ps`
96			`jsr .delay`
97
98
99			`lda #$f2`
100			`jsr .send_ps`
101			`jsr .delay`
102
103			`jsr .rcv_ps`
104			`jsr .delay`
105
106			`lda #$e8`
107			`jsr .send_ps`
108			`jsr .delay`
109
110			`lda #$03`
111			`jsr .send_ps`
112			`jsr .delay`
113
114			`lda #$f3`
115			`jsr .send_ps`
116			`jsr .delay`
117
118			`lda #$28`
119			`jsr .send_ps`
120			`jsr .delay`
121
122			`lda #$f4`
123			`jsr .send_ps`
124
125
126			`nop`
127			`nop`
128			`nop`
129			`nop`
130			`nop`
131			`nop`
132			`nop`
133			`nop`
134			`nop`
135			`nop`
136			`nop`
137			`nop`
138			`nop`
139			`lda #$01`
140			`sta io_base+io_ps2_cntrl`
141
142
143
144			`lda #$c0`
145			`sta io_base+io_uart_cnt`
146			`ldx #$00`
147			`ldy #$00`
148			`lda #$fa`
149			`sta address`
150			`lda #$ff`
151			`sta address+1`
152
153			`.prn_add ldy #$00`
154			`lda address+1`
155			`jsr .prtbyt`
156			`lda address`
157			`jsr .prtbyt`
158			`lda #$20`
159			`jsr .put_c`
160
161
162			`ldy #$00`
163			`lda (address),y`
164			`jsr .prtbyt`
165			`lda #$20`
166			`jsr .put_c`
167
168			`ldx #$00`
169
170			`.lab_01 lda str_1,X ;`
171			`beq .lab_80`
172			`jsr .put_c`
173			`inx`
174			`bne .lab_01 ;`
175			`.lab_80 lda #$0d`
176			`jsr .put_c`
177			`lda #$0a`
178			`jsr .put_c`
179
180			`.lab_81 lda io_base+io_ps2_xpos`
181			`sta io_base+io_gpio_0`
182			`lda io_base+io_ps2_ypos`
183			`sta io_base+io_gpio_1`
184
185			`lda io_base+io_pic_int`
186
187			`and #$04`
188			`beq .lab_81`
189			`lda io_base+io_uart_rcv`
190			`sta io_base+io_vga_ascii`
191			`inc address`
192			`bne .prn_add`
193			`inc address+1`
194			`jmp .prn_add`
195
196
197
198
199			`.irq_vec pha`
200			`txa`
201			`tax`
202			`pla`
203			`rti`
204
205			`.nmi_vec pha`
206			`pla`
207			`rti`
208
209
210			`* = $fffa ; vectors`
211
212
213			`dw .nmi_vec ;`
214			`dw .start ;`
215			`dw .irq_vec ;`
216
217			`code`
218
219
220
221
222
223