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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jfifo
 
 
 
 
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      fifo
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESIS
        verilogSource
        include
      
 
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="jtag_i"/>
              
              
 
 
 
              
              jfifo
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="jfifo_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 

jsp_data_out
wire
out70

 
 

biu_wr_strobe
wire
out

 
 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jfifo`
41	131	jt_eaton
42
43
44
45
46
47
48
49
50
51	135	jt_eaton
52	131	jt_eaton
53
54	133	jt_eaton
55
56	135	jt_eaton
57			`gen_verilog`
58			`104.0`
59			`none`
60			`:Simulation:`
61			`tools/verilog/gen_verilog`
62
63
64			`destination`
65			`fifo`
66
67
68
69	131	jt_eaton
70
71
72
73
74
75
76
77
78	135	jt_eaton
79	131	jt_eaton
80
81
82
83
84	135	jt_eaton
85	131	jt_eaton
86
87
88	135	jt_eaton
89			`fs-sim`
90	131	jt_eaton
91	135	jt_eaton
92
93			`../verilog/jfifo_defines.v`
94			`verilogSource`
95			`include`
96
97	131	jt_eaton
98
99	135	jt_eaton
100
101			`../verilog/adbg_jfifo.v`
102			`verilogSource`
103			`module`
104
105	131	jt_eaton
106	135	jt_eaton
107			`crc32`
108			`../verilog/adbg_crc32.v`
109			`verilogSource`
110			`module`
111
112	131	jt_eaton
113	135	jt_eaton
114			`jfifo_biu`
115			`../verilog/adbg_jfifo_biu.v`
116			`verilogSource`
117			`module`
118
119	131	jt_eaton
120	135	jt_eaton
121			`jfifo_module`
122			`../verilog/adbg_jfifo_module.v`
123			`verilogSource`
124			`module`
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`bytefifo`
130			`../verilog/adbg_bytefifo.v`
131			`verilogSource`
132			`module`
133
134	131	jt_eaton
135	135	jt_eaton
136			`syncflop`
137			`../verilog/adbg_syncflop.v`
138			`verilogSource`
139			`module`
140
141	131	jt_eaton
142	135	jt_eaton
143			`syncreg`
144			`../verilog/adbg_syncreg.v`
145			`verilogSource`
146			`module`
147
148	131	jt_eaton
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156
157
158	135	jt_eaton
159			`fs-syn`
160	131	jt_eaton
161	135	jt_eaton
162
163			`../verilog/SYNTHESIS`
164			`verilogSource`
165			`include`
166
167	131	jt_eaton
168
169	135	jt_eaton
170
171			`../verilog/jfifo_defines.v`
172			`verilogSource`
173			`include`
174
175	131	jt_eaton
176
177	135	jt_eaton
178
179			`../verilog/adbg_jfifo.v`
180			`verilogSource`
181			`module`
182
183	131	jt_eaton
184	135	jt_eaton
185			`crc32`
186			`../verilog/adbg_crc32.v`
187			`verilogSource`
188			`module`
189
190	131	jt_eaton
191	135	jt_eaton
192			`jfifo_biu`
193			`../verilog/adbg_jfifo_biu.v`
194			`verilogSource`
195			`module`
196
197	131	jt_eaton
198	135	jt_eaton
199			`jfifo_module`
200			`../verilog/adbg_jfifo_module.v`
201			`verilogSource`
202			`module`
203
204	131	jt_eaton
205
206	135	jt_eaton
207			`bytefifo`
208			`../verilog/adbg_bytefifo.v`
209			`verilogSource`
210			`module`
211
212	131	jt_eaton
213	135	jt_eaton
214			`syncflop`
215			`../verilog/adbg_syncflop.v`
216			`verilogSource`
217			`module`
218
219	131	jt_eaton
220	135	jt_eaton
221			`syncreg`
222			`../verilog/adbg_syncreg.v`
223			`verilogSource`
224			`module`
225
226	131	jt_eaton
227
228	135	jt_eaton
229	131	jt_eaton
230
231
232
233
234
235
236
237
238
239
240	135	jt_eaton
241	131	jt_eaton
242
243
244
245
246	135	jt_eaton
247
248	131	jt_eaton
249
250	135	jt_eaton
251			`jtag`
252
253
254			`ipxact:library="adv_debug_sys"`
255			`ipxact:name="adv_dbg_if"`
256			`ipxact:version="jtag_i"/>`
257
258
259	131	jt_eaton
260
261
262	135	jt_eaton
263			`jfifo`
264
265
266			`ipxact:library="adv_debug_sys"`
267			`ipxact:name="adv_dbg_if"`
268			`ipxact:version="jfifo_i"/>`
269
270
271	131	jt_eaton
272
273
274
275
276
277
278	135	jt_eaton
279			`verilog`
280
281
282			`ipxact:library="Testbench"`
283			`ipxact:name="toolflow"`
284			`ipxact:version="verilog"/>`
285
286
287	131	jt_eaton
288
289
290
291
292
293	135	jt_eaton
294			`sim:Simulation:`
295			`Verilog`
296
297
298			`fs-sim`
299
300
301	131	jt_eaton
302
303	135	jt_eaton
304			`syn:Synthesis:`
305			`Verilog`
306
307
308			`fs-syn`
309
310
311	131	jt_eaton
312
313
314	135	jt_eaton
315			`doc`
316
317
318			`ipxact:library="Testbench"`
319			`ipxact:name="toolflow"`
320			`ipxact:version="documentation"/>`
321
322			`:Documentation:`
323			`Verilog`
324
325	131	jt_eaton
326
327
328	135	jt_eaton
329	131	jt_eaton
330
331
332
333	135	jt_eaton
334	131	jt_eaton
335
336	135	jt_eaton
337			`jsp_data_out`
338			`wire`
339			`out70`
340
341	131	jt_eaton
342
343	135	jt_eaton
344			`biu_wr_strobe`
345			`wire`
346			`out`
347
348	131	jt_eaton
349
350
351
352	135	jt_eaton
353	131	jt_eaton
354
355
356	135	jt_eaton
357	131	jt_eaton
358
359
360
361
362
363
364
365
366
367
368
369	135	jt_eaton