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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jfifo  default
 
 
 
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
 
    
      destination
      fifo
    
 
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESYS
        verilogSource
        include
      
 
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
 
              
              jfifo
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jfifo_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 

jsp_data_out
wire
out70

 
 

biu_wr_strobe
wire
out

 
 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jfifo default`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55			`gen_verilog`
56			`104.0`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/gen_verilog`
60
61
62
63			`destination`
64			`fifo`
65
66
67
68			`dest_dir`
69			`../verilog`
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93			`fs-sim`
94
95
96
97			`../verilog/jfifo_defines.v`
98			`verilogSource`
99			`include`
100
101
102
103
104
105			`../verilog/adbg_jfifo.v`
106			`verilogSource`
107			`module`
108
109
110
111			`crc32`
112			`../verilog/adbg_crc32.v`
113			`verilogSource`
114			`module`
115
116
117
118			`jfifo_biu`
119			`../verilog/adbg_jfifo_biu.v`
120			`verilogSource`
121			`module`
122
123
124
125			`jfifo_module`
126			`../verilog/adbg_jfifo_module.v`
127			`verilogSource`
128			`module`
129
130
131
132
133			`bytefifo`
134			`../verilog/adbg_bytefifo.v`
135			`verilogSource`
136			`module`
137
138
139
140			`syncflop`
141			`../verilog/adbg_syncflop.v`
142			`verilogSource`
143			`module`
144
145
146
147			`syncreg`
148			`../verilog/adbg_syncreg.v`
149			`verilogSource`
150			`module`
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-syn`
164
165
166
167			`../verilog/SYNTHESYS`
168			`verilogSource`
169			`include`
170
171
172
173
174
175			`../verilog/jfifo_defines.v`
176			`verilogSource`
177			`include`
178
179
180
181
182
183			`../verilog/adbg_jfifo.v`
184			`verilogSource`
185			`module`
186
187
188
189			`crc32`
190			`../verilog/adbg_crc32.v`
191			`verilogSource`
192			`module`
193
194
195
196			`jfifo_biu`
197			`../verilog/adbg_jfifo_biu.v`
198			`verilogSource`
199			`module`
200
201
202
203			`jfifo_module`
204			`../verilog/adbg_jfifo_module.v`
205			`verilogSource`
206			`module`
207
208
209
210
211			`bytefifo`
212			`../verilog/adbg_bytefifo.v`
213			`verilogSource`
214			`module`
215
216
217
218			`syncflop`
219			`../verilog/adbg_syncflop.v`
220			`verilogSource`
221			`module`
222
223
224
225			`syncreg`
226			`../verilog/adbg_syncreg.v`
227			`verilogSource`
228			`module`
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255			`jtag`
256
257
258			`spirit:library="adv_debug_sys"`
259			`spirit:name="adv_dbg_if"`
260			`spirit:version="jtag_i"/>`
261
262
263
264
265
266
267			`jfifo`
268
269
270			`spirit:library="adv_debug_sys"`
271			`spirit:name="adv_dbg_if"`
272			`spirit:version="jfifo_i"/>`
273
274
275
276
277
278
279
280
281
282
283			`verilog`
284
285
286			`spirit:library="Testbench"`
287			`spirit:name="toolflow"`
288			`spirit:version="verilog"/>`
289
290
291
292
293
294
295
296
297
298			`sim:Simulation:`
299			`Verilog`
300
301
302			`fs-sim`
303
304
305
306
307
308			`syn:Synthesis:`
309			`Verilog`
310
311
312			`fs-syn`
313
314
315
316
317
318
319			`doc`
320
321
322			`spirit:library="Testbench"`
323			`spirit:name="toolflow"`
324			`spirit:version="documentation"/>`
325
326			`:Documentation:`
327			`Verilog`
328
329
330
331
332
333
334
335
336
337
338
339
340
341			`jsp_data_out`
342			`wire`
343			`out70`
344
345
346
347
348			`biu_wr_strobe`
349			`wire`
350			`out`
351
352
353
354
355
356
357
358
359
360
361
362
363
364
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