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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [cpu1/] [test_define] - Blame information for rev 131

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reg actual;
 
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
initial
begin
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
 
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
 
Shift_Cmp_53(53'h18000000000000,53'h00000000000000);
 
 
Shift_Cmp_53(53'h07000006780008,53'h00000000000000);
Shift_Cmp_53(53'h00000000000001,53'h159e248d159e26);
Shift_Cmp_53(53'h00456554454565,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h00645645456457,53'h00000000000000);
Shift_Cmp_53(53'h10000000000000,53'h00000000000000);
 
 
 
 
 
 
 
 
 
 
 
test.cg.next(100);
 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
 
test.cg.next(100);
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_53;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  53;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg actual;`
2
3
4			`parameter EXTEST=4'b0000;`
5			`parameter SAMPLE=4'b0001;`
6			`parameter HIGHZ_MODE=4'b0010;`
7			`parameter CHIP_ID_ACCESS=4'b0011;`
8			`parameter CLAMP=4'b1000;`
9			`parameter RPC_DATA=4'b1010;`
10			`parameter RPC_ADD=4'b1001;`
11			`parameter BYPASS=4'b1111;`
12			`parameter INST_RETURN=4'b1101;`
13
14			`initial`
15			`begin`
16			`$display(" ");`
17			`$display(" ===================================================");`
18			`$display(" Test Start");`
19			`$display(" ===================================================");`
20			`$display(" ");`
21			`test.cg.next(2);`
22			`test.jtag_model.enable_tclk;`
23			`test.cg.next(20);`
24
25			`test.cg.next(20);`
26			`test.jtag_model.enable_trst_n;`
27			`test.jtag_model.enable_reset;`
28			`test.jtag_model.init;`
29			`test.cg.next(10);`
30			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
31			`test.cg.next(100);`
32			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
33
34
35			`test.cg.next(100);`
36			`test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);`
37			`test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);`
38
39
40			`test.cg.next(100);`
41			`test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);`
42
43			`Shift_Cmp_53(53'h18000000000000,53'h00000000000000);`
44
45
46			`Shift_Cmp_53(53'h07000006780008,53'h00000000000000);`
47			`Shift_Cmp_53(53'h00000000000001,53'h159e248d159e26);`
48			`Shift_Cmp_53(53'h00456554454565,53'h00000000000000);`
49			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
50			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
51			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
52			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
53			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
54			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
55			`Shift_Cmp_53(53'h00645645456457,53'h00000000000000);`
56			`Shift_Cmp_53(53'h10000000000000,53'h00000000000000);`
57
58
59
60
61
62
63
64
65
66
67
68			`test.cg.next(100);`
69
70			`test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);`
71
72			`test.cg.next(100);`
73
74
75			`test.cg.exit;`
76			`end`
77
78
79
80
81
82
83			`task automatic Shift_Cmp_53; // Initialize boundary register with outputs disabled`
84			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
85
86			`parameter [15:0] LENGTH = 53;`
87
88
89			`input [LENGTH:1] Dataout;`
90			`input [LENGTH:1] DataExp;`
91
92			`integer i;`
93
94			`reg [LENGTH:1] DataBack;`
95
96			`begin`
97			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
98			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
99			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
100			`for (i = 1; i <= LENGTH; i = i+1)`
101			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
102			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
103
104			`if (DataBack !== DataExp )`
105			`begin`
106			`test.cg.fail (" Shift_cmp receive error ");`
107			`end`
108
109			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
110			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
111			`end`
112			`endtask // ShiftRegister`
113
114
115
116
117
118
119

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [cpu1/] [test_define] - Blame information for rev 131