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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [jfifo_sync1/] [test_define] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
reg actual;
2 
reg [31:0] d;
3 
 
4 
parameter       EXTEST=4'b0000;
5 
parameter       SAMPLE=4'b0001;
6 
parameter       HIGHZ_MODE=4'b0010;
7 
parameter       CHIP_ID_ACCESS=4'b0011;
8 
parameter       CLAMP=4'b1000;
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parameter       RPC_DATA=4'b1010;
10 
parameter       RPC_ADD=4'b1001;
11 
parameter       BYPASS=4'b1111;
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parameter       INST_RETURN=4'b1101;
13 
 
14 
initial
15 
begin
16 
$display("              ");
17 
$display("              ===================================================");
18 
$display("              Test Start");
19 
$display("              ===================================================");
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$display("              ");
21 
test.cg.next(2);
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test.jtag_model.enable_tclk;
23 
test.cg.next(20);
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fork
25 
begin
26 
test.cg.next(20);
27 
test.mask_jsp_data_out = 8'hff;
28 
test.cg.next(20);
29 
 
30 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
31 
test.mask_jsp_data_out = 8'h00;
32 
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
33 
test.exp_jsp_data_out = 8'hff;
34 
test.mask_jsp_data_out = 8'hff;
35 
 
36 
 
37 
 
38 
 
39 
 
40 
 
41 
 
42 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
43 
test.mask_jsp_data_out = 8'h00;
44 
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
45 
test.exp_jsp_data_out = 8'h7e;
46 
test.mask_jsp_data_out = 8'hff;
47 
 
48 
 
49 
 
50 
 
51 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
52 
test.mask_jsp_data_out = 8'h00;
53 
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
54 
test.exp_jsp_data_out = 8'hc3;
55 
test.mask_jsp_data_out = 8'hff;
56 
 
57 
 
58 
 
59 
 
60 
 
61 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
62 
test.mask_jsp_data_out = 8'h00;
63 
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
64 
test.exp_jsp_data_out = 8'h3c;
65 
test.mask_jsp_data_out = 8'hff;
66 
 
67 
 
68 
 
69 
 
70 
 
71 
 
72 
 
73 
end
74 
 
75 
 
76 
 
77 
begin
78 
test.cg.next(20);
79 
test.jtag_model.enable_trst_n;
80 
test.jtag_model.enable_reset;
81 
test.jtag_model.init;
82 
test.cg.next(10);
83 
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
84 
test.cg.next(100);
85 
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
86 
 
87 
test.cg.next(100);
88 
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
89 
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
90 
 
91 
 
92 
test.cg.next(100);
93 
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
94 
 
95 
//Shift_Cmp_18(18'h38000,18'h00000);
96 
 
97 
test.cg.next(5000);
98 
 
99 
 
100 
Shift_Cmp_18(18'b0_11111111_0001_00001       ,18'h00084);
101 
Shift_Cmp_18(18'b0_01111110_0001_00001       ,18'h00064);
102 
Shift_Cmp_18(18'b0_11000011_0001_00001       ,18'h00044);
103 
Shift_Cmp_18(18'b0_00111100_0001_00001       ,18'h00024);
104 
 
105 
 
106 
test.cg.next(5000);
107 
 
108 
 
109 
 
110 
 
111 
test.cg.next(100);
112 
 
113 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
114 
 
115 
test.cg.next(100);
116 
end
117 
 
118 
 
119 
begin
120 
 
121 
 
122 
test.cg.next(1000);
123 
 
124 
 
125 
fork
126 
  begin
127 
  test.jsp_data_in <= 8'h00;
128 
  test.jsp_data_in_stb <= 1'b1;
129 
  test.cg.next(2);
130 
  test.jsp_data_in_stb <= 1'b0;
131 
  end
132 
  begin
133 
 
134 
  test.cg.next(1);
135 
  end
136 
join
137 
 
138 
test.cg.next(30);
139 
 
140 
fork
141 
  begin
142 
  test.jsp_data_in <= 8'h00;
143 
  test.jsp_data_in_stb <= 1'b1;
144 
  test.cg.next(2);
145 
  test.jsp_data_in_stb <= 1'b0;
146 
  end
147 
  begin
148 
  test.cg.next(1);
149 
  end
150 
join
151 
 
152 
test.cg.next(30);
153 
 
154 
 
155 
fork
156 
  begin
157 
  test.jsp_data_in <= 8'h00;
158 
  test.jsp_data_in_stb <= 1'b1;
159 
  test.cg.next(2);
160 
  test.jsp_data_in_stb <= 1'b0;
161 
  end
162 
  begin
163 
  test.cg.next(1);
164 
  end
165 
join
166 
 
167 
test.cg.next(30);
168 
 
169 
 
170 
 
171 
fork
172 
  begin
173 
  test.jsp_data_in <= 8'h00;
174 
  test.jsp_data_in_stb <= 1'b1;
175 
  test.cg.next(2);
176 
  test.jsp_data_in_stb <= 1'b0;
177 
  end
178 
  begin
179 
  test.cg.next(1);
180 
  end
181 
join
182 
test.cg.next(30);
183 
 
184 
 
185 
 
186 
fork
187 
  begin
188 
  test.jsp_data_in <= 8'h00;
189 
  test.jsp_data_in_stb <= 1'b1;
190 
  test.cg.next(2);
191 
  test.jsp_data_in_stb <= 1'b0;
192 
  end
193 
  begin
194 
  test.cg.next(1);
195 
  end
196 
join
197 
 
198 
 
199 
 
200 
test.cg.next(30);
201 
 
202 
 
203 
 
204 
fork
205 
  begin
206 
  test.jsp_data_in <= 8'h00;
207 
  test.jsp_data_in_stb <= 1'b1;
208 
  test.cg.next(2);
209 
  test.jsp_data_in_stb <= 1'b0;
210 
  end
211 
  begin
212 
  test.cg.next(1);
213 
  end
214 
join
215 
 
216 
 
217 
test.cg.next(30);
218 
 
219 
 
220 
 
221 
 
222 
 
223 
 
224 
fork
225 
  begin
226 
  test.jsp_data_in <= 8'h00;
227 
  test.jsp_data_in_stb <= 1'b1;
228 
  test.cg.next(2);
229 
  test.jsp_data_in_stb <= 1'b0;
230 
  end
231 
  begin
232 
  test.cg.next(1);
233 
  end
234 
join
235 
 
236 
 
237 
test.cg.next(30);
238 
 
239 
 
240 
 
241 
 
242 
 
243 
 
244 
fork
245 
  begin
246 
  test.jsp_data_in <= 8'h00;
247 
  test.jsp_data_in_stb <= 1'b1;
248 
  test.cg.next(2);
249 
  test.jsp_data_in_stb <= 1'b0;
250 
  end
251 
  begin
252 
  test.cg.next(1);
253 
  end
254 
join
255 
 
256 
 
257 
test.cg.next(30);
258 
 
259 
 
260 
 
261 
 
262 
 
263 
 
264 
fork
265 
  begin
266 
  test.jsp_data_in <= 8'h00;
267 
  test.jsp_data_in_stb <= 1'b1;
268 
  test.cg.next(2);
269 
  test.jsp_data_in_stb <= 1'b0;
270 
  end
271 
  begin
272 
  test.cg.next(1);
273 
  end
274 
join
275 
 
276 
 
277 
test.cg.next(30);
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284 
 
285 
end
286 
 
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288 
 
289 
join
290 
 
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294 
test.cg.exit;
295 
end
296 
 
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299 
 
300 
 
301 
task automatic  Shift_Cmp_18;    // Initialize boundary register with outputs disabled
302 
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
303 
 
304 
  parameter [15:0] LENGTH =  18;
305 
 
306 
 
307 
  input [LENGTH:1]  Dataout;
308 
  input [LENGTH:1]  DataExp;
309 
 
310 
  integer i;
311 
 
312 
  reg [LENGTH:1]  DataBack;
313 
 
314 
  begin
315 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
316 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
317 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
318 
    for (i = 1; i <= LENGTH; i = i+1)
319 
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
320 
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
321 
 
322 
   if (DataBack  !== DataExp )
323 
   begin
324 
   test.cg.fail  (" Shift_cmp  receive error  ");
325 
   end
326 
 
327 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
328 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
329 
  end
330 
endtask // ShiftRegister
331 
 
332 
 
333 
 
334 
 
335 
task automatic  Shift_Cmp_25;    // Initialize boundary register with outputs disabled
336 
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
337 
 
338 
  parameter [15:0] LENGTH =  25;
339 
 
340 
 
341 
  input [LENGTH:1]  Dataout;
342 
  input [LENGTH:1]  DataExp;
343 
 
344 
  integer i;
345 
 
346 
  reg [LENGTH:1]  DataBack;
347 
 
348 
  begin
349 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
350 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
351 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
352 
    for (i = 1; i <= LENGTH; i = i+1)
353 
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
354 
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
355 
 
356 
   if (DataBack  !== DataExp )
357 
   begin
358 
   test.cg.fail  (" Shift_cmp  receive error  ");
359 
   end
360 
 
361 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
362 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
363 
  end
364 
endtask // ShiftRegister
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