URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.cpu0] - Blame information for rev 133

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assign cpu0_clk_i   = clk;
assign cpu0_bp_i    = 1'b0;
assign cpu0_ack_i   = cpu0_stb_o;
assign cpu0_data_i  = 32'h23456789;assign tck_i          = jtag_clk;
assign capture_dr_i   = capture_dr_o;
assign shift_dr_i     = shift_dr_o;
assign update_dr_i    = update_dr_o;
assign debug_select_i = select_o;
assign rst_i          = test_logic_reset_o;
assign tdo_i          = tdo_o;
assign bsr_tdo_i      = 1'b0;
assign tdi_i          = tdi_o;
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`assign cpu0_clk_i = clk;`
2			`assign cpu0_bp_i = 1'b0;`
3			`assign cpu0_ack_i = cpu0_stb_o;`
4			`assign cpu0_data_i = 32'h23456789;assign tck_i = jtag_clk;`
5			`assign capture_dr_i = capture_dr_o;`
6			`assign shift_dr_i = shift_dr_o;`
7			`assign update_dr_i = update_dr_o;`
8	133	jt_eaton	`assign debug_select_i = select_o;`
9	131	jt_eaton	`assign rst_i = test_logic_reset_o;`
10	133	jt_eaton	`assign tdo_i = tdo_o;`
11	131	jt_eaton	`assign bsr_tdo_i = 1'b0;`
12			`assign tdi_i = tdi_o;`
13
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.cpu0] - Blame information for rev 133