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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tb.wb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4
    wb_addr_width         32
    wb_data_width         32
    wb_byte_lanes         4

 
       
 
              
              Params
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="wb_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="bfm.design"/>
              
 
 
              
              wb_Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="wb_bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
      
        
        ../verilog/tb.wb
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/top.tb.wb
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/top.tb.wb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`wb_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	133	jt_eaton	`top.tb.wb`
34	131	jt_eaton
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
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55
56
57			`JTAG_MODEL_DIVCNT 4'h4`
58			`JTAG_MODEL_SIZE 4`
59			`wb_addr_width 32`
60			`wb_data_width 32`
61			`wb_byte_lanes 4`
62
63
64
65
66
67			`Params`
68
69
70			`spirit:library="adv_debug_sys"`
71			`spirit:name="adv_dbg_if"`
72			`spirit:version="wb_dut.params"/>`
73
74
75
76
77
78			`Bfm`
79
80			`spirit:library="adv_debug_sys"`
81			`spirit:name="adv_dbg_if"`
82			`spirit:version="bfm.design"/>`
83
84
85
86
87			`wb_Bfm`
88
89			`spirit:library="adv_debug_sys"`
90			`spirit:name="adv_dbg_if"`
91			`spirit:version="wb_bfm.design"/>`
92
93
94
95
96			`icarus`
97
98
99			`spirit:library="Testbench"`
100			`spirit:name="toolflow"`
101			`spirit:version="icarus"/>`
102
103
104
105
106
107
108
109			`commoncommon`
110			`Verilog`
111
112
113			`fs-common`
114
115
116
117
118
119			`sim:Simulation:`
120			`Verilog`
121
122
123			`fs-sim`
124
125
126
127
128			`lint:Lint:`
129			`Verilog`
130
131
132			`fs-lint`
133
134
135
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139
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142
143
144
145
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152
153			`fs-common`
154
155
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158			`../verilog/tb.wb`
159			`verilogSource`
160			`fragment`
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`fs-sim`
178
179
180
181
182			`../verilog/tb.ext`
183			`verilogSource`
184			`fragment`
185
186
187
188
189
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191
192	133	jt_eaton	`../verilog/common/top.tb.wb`
193	131	jt_eaton	`verilogSourcemodule`
194
195
196
197
198
199
200
201
202
203			`fs-lint`
204
205
206	133	jt_eaton	`../verilog/common/top.tb.wb`
207	131	jt_eaton	`verilogSourcemodule`
208
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