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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
fpgas
Nexys2_T6502
core  default
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.T6502
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 
 

 
 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.jabc
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.gpio
        verilogSourcefragment
      
 
 
 
      
        
        ../verilog/top.rs_uart
        verilogSourcefragment
      
 
      
        ../verilog
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.T6502
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="core.design"/>
              
 
 
              
              Core
 
              
              
                                   spirit:library="Nexys2"
                                   spirit:name="fpga"
                                   spirit:version="core"/>
              
 
 
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
 
      
 
 
 

 RAM_WORDS2048
 RAM_ADD11
 ROM_WORDS4096
 ROM_ADD12
 PROG_ROM_WORDSROM_WORDS
 PROG_ROM_ADDROM_ADD
 VEC_TABLE8'hff
 UART_PRESCALE5'b01100
 UART_PRE_SIZE5
 UART_DIV0
 JTAG_SEL1
 JTAG_USER1_WIDTH8
 JTAG_USER1_RESET8'h12
 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`fpgas`
39			`Nexys2_T6502`
40			`core default`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`top.T6502`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
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80
81
82			`fs-common`
83
84
85
86
87			`../verilog/top.jabc`
88			`verilogSourcefragment`
89
90
91
92
93
94			`../verilog/top.gpio`
95			`verilogSourcefragment`
96
97
98
99
100
101
102			`../verilog/top.rs_uart`
103			`verilogSourcefragment`
104
105
106
107			`../verilog`
108			`verilogSourcelibraryDir`
109
110
111
112
113
114
115
116
117			`fs-sim`
118
119
120
121			`../verilog/copyright.v`
122			`verilogSourceinclude`
123
124
125
126
127			`../verilog/common/top.T6502`
128			`verilogSourcemodule`
129
130
131
132
133
134
135
136
137
138
139
140
141
142
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151
152			`Hierarchical`
153
154
155			`spirit:library="fpgas"`
156			`spirit:name="Nexys2_T6502"`
157			`spirit:version="core.design"/>`
158
159
160
161
162			`Core`
163
164
165
166			`spirit:library="Nexys2"`
167			`spirit:name="fpga"`
168			`spirit:version="core"/>`
169
170
171
172
173
174
175
176			`verilog`
177
178
179			`spirit:library="Testbench"`
180			`spirit:name="toolflow"`
181			`spirit:version="verilog"/>`
182
183
184
185
186
187
188
189
190			`commoncommon`
191			`Verilog`
192
193
194			`fs-common`
195
196
197
198
199			`sim:Simulation:`
200			`Verilog`
201
202
203			`fs-sim`
204
205
206
207
208
209			`syn:Synthesis:`
210			`Verilog`
211
212
213			`fs-sim`
214
215
216
217
218
219
220
221
222
223
224
225
226			`RAM_WORDS2048`
227			`RAM_ADD11`
228			`ROM_WORDS4096`
229			`ROM_ADD12`
230			`PROG_ROM_WORDSROM_WORDS`
231			`PROG_ROM_ADDROM_ADD`
232			`VEC_TABLE8'hff`
233			`UART_PRESCALE5'b01100`
234			`UART_PRE_SIZE5`
235			`UART_DIV0`
236			`JTAG_SEL1`
237			`JTAG_USER1_WIDTH8`
238			`JTAG_USER1_RESET8'h12`
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
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