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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default  default
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.T6502_default
    
    
      dest_dir
      ../verilog
    
  

 

 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.T6502_default
        verilogSourcemodule
      
 
    
 
  
 

 
  
 
              
              Hierarchical
 
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="fpga.design"/>
              
 
    
     Pad_Ring
 
     
     
                          spirit:library="Nexys2"
                          spirit:name="fpga"
                          spirit:version="jtag_padring"/>
     
    
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
 
    
    commoncommon
    Verilog
    
    fs-common
    
 
 
 
    
    sim:*Simulation:*
    Verilog
    
    fs-sim
    
 
 
    
    syn:*Synthesis:*
    Verilog
    
    fs-sim
    
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default default`
40
41	133	jt_eaton
42	131	jt_eaton
43	133	jt_eaton
44			`elab_verilog`
45			`102.1`
46			`none`
47			`:Simulation:`
48			`./tools/verilog/elab_verilog`
49
50
51			`configuration`
52			`default`
53
54
55			`dest_dir`
56			`io_ports`
57
58
59
60	131	jt_eaton
61
62
63
64			`gen_verilog`
65			`104.0`
66			`none`
67			`common`
68			`./tools/verilog/gen_verilog`
69
70
71			`destination`
72			`top.T6502_default`
73
74
75			`dest_dir`
76			`../verilog`
77
78
79
80
81
82
83
84
85
86			`fs-sim`
87
88
89
90			`../verilog/copyright.v`
91			`verilogSourceinclude`
92
93
94
95
96			`../verilog/common/top.T6502_default`
97			`verilogSourcemodule`
98
99
100
101
102
103
104
105
106
107
108
109			`Hierarchical`
110
111
112			`spirit:library="fpgas"`
113			`spirit:name="Nexys2_T6502"`
114			`spirit:version="fpga.design"/>`
115
116
117
118			`Pad_Ring`
119
120
121
122			`spirit:library="Nexys2"`
123			`spirit:name="fpga"`
124			`spirit:version="jtag_padring"/>`
125
126
127
128
129			`verilog`
130
131
132			`spirit:library="Testbench"`
133			`spirit:name="toolflow"`
134			`spirit:version="verilog"/>`
135
136
137
138
139
140
141
142
143
144
145			`commoncommon`
146			`Verilog`
147
148			`fs-common`
149
150
151
152
153
154			`sim:Simulation:`
155			`Verilog`
156
157			`fs-sim`
158
159
160
161
162			`syn:Synthesis:`
163			`Verilog`
164
165			`fs-sim`
166
167
168
169
170
171
172			`doc`
173
174
175			`spirit:library="Testbench"`
176			`spirit:name="toolflow"`
177			`spirit:version="documentation"/>`
178
179			`:Documentation:`
180			`Verilog`
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 133