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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_tb
 
 
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut.core.T6502.cpu
    
    
      bus_name
      cpu
    
  
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.T6502_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 


    JTAG_MODEL_DIVCNT 4'h4     
    JTAG_MODEL_SIZE   4        
    UART_MODEL_CLKCNT 5'b11001 
    UART_MODEL_SIZE   5        
    PS2_MODEL_CLKCNT  10'h177  
    PS2_MODEL_SIZE    10       
 

       
 
 
 
              
              Params
              
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="default_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.T6502_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.T6502_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default_tb`
40
41
42
43
44
45
46
47
48			`elab_verilog`
49			`103.0`
50			`none`
51			`:Simulation:`
52			`./tools/verilog/elab_verilog`
53
54
55
56			`trace_bus`
57			`103.0`
58			`none`
59			`:Simulation:`
60			`./tools/verilog/trace_bus`
61
62
63			`path`
64			`root.dut.core.T6502.cpu`
65
66
67			`bus_name`
68			`cpu`
69
70
71
72
73
74
75
76
77
78			`gen_verilog`
79			`104.0`
80			`none`
81			`common`
82			`./tools/verilog/gen_verilog`
83
84
85			`destination`
86			`top.T6502_tb`
87
88
89			`dest_dir`
90			`../verilog`
91
92
93			`top`
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`JTAG_MODEL_DIVCNT 4'h4`
109			`JTAG_MODEL_SIZE 4`
110			`UART_MODEL_CLKCNT 5'b11001`
111			`UART_MODEL_SIZE 5`
112			`PS2_MODEL_CLKCNT 10'h177`
113			`PS2_MODEL_SIZE 10`
114
115
116
117
118
119
120
121			`Params`
122
123
124			`spirit:library="fpgas"`
125			`spirit:name="Nexys2_T6502"`
126			`spirit:version="default_dut.params"/>`
127
128
129
130
131
132
133			`Bfm`
134
135			`spirit:library="fpgas"`
136			`spirit:name="Nexys2_T6502"`
137			`spirit:version="bfm.design"/>`
138
139
140
141
142
143			`icarus`
144
145
146			`spirit:library="Testbench"`
147			`spirit:name="toolflow"`
148			`spirit:version="icarus"/>`
149
150
151
152
153
154
155
156			`commoncommon`
157			`Verilog`
158
159
160			`fs-common`
161
162
163
164
165
166			`sim:Simulation:`
167			`Verilog`
168
169
170			`fs-sim`
171
172
173
174
175			`lint:Lint:`
176			`Verilog`
177
178
179			`fs-lint`
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196			`fs-common`
197
198
199
200			`../verilog/sram.load`
201			`verilogSourcefragment`
202
203
204
205
206
207			`../verilog/tb.ext`
208			`verilogSourcefragment`
209
210
211
212
213
214
215
216
217
218
219			`fs-sim`
220
221
222
223			`../verilog/common/top.T6502_tb`
224			`verilogSourcemodule`
225
226
227
228
229
230
231			`fs-lint`
232
233
234
235			`../verilog/common/top.T6502_tb`
236			`verilogSourcemodule`
237
238
239
240
241
242
243
244
245
246
247
248
249
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