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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ext_mem_interface
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
 
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
 
        
         cs
         
         cs
         
       
 
 
      
  
 
 
 
 
 
 
 
 
 
mem
   
   
     
     
 
        
         addr
         
         mem_addr
           150
         
       
 
        
         cs
         
         mem_cs
         
       
 
 
        
         rdata
         
         mem_rdata
           150
         
       
 
 
 
        
         wdata
         
         mem_wdata
           150
         
       
 
 
        
         rd
         
         mem_rd
         
       
 
        
         wr
         
         mem_wr
         
       
 
 
        
         wait
         
         mem_wait
         
       
 
 
      
  
 
 
 
 
 
 
 
 
ext
   
   
   
     
 
        
         addr
         
         ext_add
           reg
           231
         
       
 
 
        
         wdata
         
         ext_wdata
           reg
           150
         
       
 
 
        
         rdata
         
         ext_rdata
           wire
           150
         
       
 
 
        
         rd
         
         ext_rd
           reg
         
       
 
 
        
         wr
         
         ext_wr
           reg
         
       
 
 
        
         wait
         
         ext_wait
           wire
         
       
 
 
        
         cs
         
         ext_cs
           reg
           10
         
       
 
 
 
      
  
 
 
 
 
 

 
 

 
 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
      
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ext_mem_interface"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

BASE_ADDR4'h0
BASE_WIDTH4
ADDR_WIDTH8
MEM_WIDTH23
MEM_FRAME10

 

 
enable
wire
in

 
 
 
 
wait_st
wire
out
70

 
 
 
 
 
 
bank
wire
out
70

 
 
 
 
 
 
 
ext_ub
reg
out

 
ext_stb
reg
out

 
 
 
ext_lb
reg
out

 
 
 

 

 
 
 
 
 
 

 

 mb
 8
 
   mb
   0x0
   
    ext_mem
    0x10
    8
     
     bank
     0x2
     8
     read-write
     
     
     wait_st
     0x0
     8
     read-write
     
    
   

 
 
 

 mem
 8
 
   mem
   0x0
   
    mem
    0x4000
    16
    
   

 
 
 
 
 
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ext_mem_interface`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81
82			`rdata`
83
84			`rdata`
85			`wire`
86			`70`
87
88
89
90
91
92			`addr`
93
94			`addr`
95			`30`
96
97
98
99
100			`wdata`
101
102			`wdata`
103			`70`
104
105
106
107
108
109			`rd`
110
111			`rd`
112
113
114
115
116			`wr`
117
118			`wr`
119
120
121
122
123
124			`cs`
125
126			`cs`
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142			`mem`
143
144
145
146
147
148
149			`addr`
150
151			`mem_addr`
152			`150`
153
154
155
156
157			`cs`
158
159			`mem_cs`
160
161
162
163
164
165			`rdata`
166
167			`mem_rdata`
168			`150`
169
170
171
172
173
174
175			`wdata`
176
177			`mem_wdata`
178			`150`
179
180
181
182
183
184			`rd`
185
186			`mem_rd`
187
188
189
190
191			`wr`
192
193			`mem_wr`
194
195
196
197
198
199			`wait`
200
201			`mem_wait`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216			`ext`
217
218
219
220
221
222
223			`addr`
224
225			`ext_add`
226			`reg`
227			`231`
228
229
230
231
232
233			`wdata`
234
235			`ext_wdata`
236			`reg`
237			`150`
238
239
240
241
242
243			`rdata`
244
245			`ext_rdata`
246			`wire`
247			`150`
248
249
250
251
252
253			`rd`
254
255			`ext_rd`
256			`reg`
257
258
259
260
261
262			`wr`
263
264			`ext_wr`
265			`reg`
266
267
268
269
270
271			`wait`
272
273			`ext_wait`
274			`wire`
275
276
277
278
279
280			`cs`
281
282			`ext_cs`
283			`reg`
284			`10`
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310			`gen_registers`
311			`103.0`
312			`common`
313			`none`
314			`./tools/regtool/gen_registers`
315
316
317			`bus_intf`
318			`mb`
319
320
321			`dest_dir`
322			`../verilog`
323
324
325
326
327
328			`gen_verilog`
329			`104.0`
330			`none`
331			`common`
332			`./tools/verilog/gen_verilog`
333
334
335			`destination`
336			`top`
337
338
339			`dest_dir`
340			`../verilog`
341
342
343
344
345
346
347
348
349
350
351
352
353
354			`fs-common`
355
356
357
358			`../verilog/top.body`
359			`verilogSourcefragment`
360
361
362
363
364
365			`fs-sim`
366
367
368
369			`../verilog/copyright.v`
370			`verilogSourceinclude`
371
372
373
374			`../verilog/common/top`
375			`verilogSourcemodule`
376
377
378
379
380			`mb`
381			`../verilog/io_ext_mem_interface_def_mb`
382			`verilogSourcemodule`
383
384
385
386
387
388
389
390
391
392			`fs-syn`
393
394
395
396			`../verilog/copyright.v`
397			`verilogSourceinclude`
398
399
400
401
402			`../verilog/common/top`
403			`verilogSourcemodule`
404
405
406
407
408			`mb`
409			`../verilog/io_ext_mem_interface_def_mb`
410			`verilogSourcemodule`
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430			`Hierarchical`
431
432
433			`spirit:library="io"`
434			`spirit:name="io_ext_mem_interface"`
435			`spirit:version="def.design"/>`
436
437
438
439
440			`verilog`
441
442
443			`spirit:library="Testbench"`
444			`spirit:name="toolflow"`
445			`spirit:version="verilog"/>`
446
447
448
449
450
451
452
453
454			`commoncommon`
455
456			`Verilog`
457
458
459			`fs-common`
460
461
462
463
464			`sim:Simulation:`
465
466			`Verilog`
467
468
469			`fs-sim`
470
471
472
473
474
475			`syn:Synthesis:`
476
477			`Verilog`
478
479
480			`fs-syn`
481
482
483
484
485
486
487			`doc`
488
489
490			`spirit:library="Testbench"`
491			`spirit:name="toolflow"`
492			`spirit:version="documentation"/>`
493
494			`:Documentation:`
495			`Verilog`
496
497
498
499
500
501
502
503
504
505			`BASE_ADDR4'h0`
506			`BASE_WIDTH4`
507			`ADDR_WIDTH8`
508			`MEM_WIDTH23`
509			`MEM_FRAME10`
510
511
512
513
514			`enable`
515			`wire`
516			`in`
517
518
519
520
521
522			`wait_st`
523			`wire`
524			`out`
525			`70`
526
527
528
529
530
531
532
533			`bank`
534			`wire`
535			`out`
536			`70`
537
538
539
540
541
542
543
544
545			`ext_ub`
546			`reg`
547			`out`
548
549
550			`ext_stb`
551			`reg`
552			`out`
553
554
555
556
557			`ext_lb`
558			`reg`
559			`out`
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576			`mb`
577			`8`
578
579			`mb`
580			`0x0`
581
582			`ext_mem`
583			`0x10`
584			`8`
585
586			`bank`
587			`0x2`
588			`8`
589			`read-write`
590
591
592			`wait_st`
593			`0x0`
594			`8`
595			`read-write`
596
597
598
599
600
601
602
603
604			`mem`
605			`8`
606
607			`mem`
608			`0x0`
609
610			`mem`
611			`0x4000`
612			`16`
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629