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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [rtl/] [xml/] [io_gpio_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_gpio
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 mb
   
   
   little
   8
     
 
     
 
 
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 
 

 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
     
        mb
        ../verilog/io_gpio_def_mb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_gpio"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
enable
wire
in

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
gpio_1_in
wire
in
70

 
 
 

 

 
 
 
 
 


 
8
 mb

 mb
 0x0000
 
  
  mb_microbus
  0x10
  8
 
 
 
   gpio_0_out
   0x2
   8
   read-write
  
 
 
   gpio_0_oe
   0x1
   8
   read-write
  
 
 
   gpio_0_in
   0x0
   8
   read-only
  
 
 
 
   gpio_1_out
   0x6
   8
   read-write
  
 
 
   gpio_1_oe
   0x5
   8
   read-write
  
 
 
   gpio_1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [rtl/] [xml/] [io_gpio_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_gpio`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70			`mb`
71
72
73			`little`
74			`8`
75
76
77
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90
91			`wdata`
92
93			`wdata`
94			`70`
95
96
97
98
99
100			`addr`
101
102			`addr`
103			`30`
104
105
106
107
108
109			`rd`
110
111			`rd`
112
113
114
115
116			`wr`
117
118			`wr`
119
120
121
122
123			`cs`
124
125			`cs`
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147			`gen_registers`
148			`103.0`
149			`common`
150			`none`
151			`./tools/regtool/gen_registers`
152
153
154			`bus_intf`
155			`mb`
156
157
158			`dest_dir`
159			`../verilog`
160
161
162
163
164
165
166			`gen_verilog`
167			`104.0`
168			`none`
169			`common`
170			`./tools/verilog/gen_verilog`
171
172
173			`destination`
174			`top`
175
176
177			`dest_dir`
178			`../verilog`
179
180
181
182
183
184
185
186
187
188
189
190
191			`fs-common`
192
193
194
195
196			`../verilog/top.body`
197			`verilogSourcefragment`
198
199
200
201
202
203
204			`fs-sim`
205
206
207
208			`../verilog/copyright.v`
209			`verilogSourceinclude`
210
211
212
213
214			`../verilog/common/top`
215			`verilogSourcemodule`
216
217
218
219
220			`mb`
221			`../verilog/io_gpio_def_mb`
222			`verilogSourcemodule`
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242			`Hierarchical`
243
244
245			`spirit:library="io"`
246			`spirit:name="io_gpio"`
247			`spirit:version="def.design"/>`
248
249
250
251			`verilog`
252
253
254			`spirit:library="Testbench"`
255			`spirit:name="toolflow"`
256			`spirit:version="verilog"/>`
257
258
259
260
261
262
263
264
265			`commoncommon`
266
267			`Verilog`
268
269
270			`fs-common`
271
272
273
274
275			`sim:Simulation:`
276			`Verilog`
277
278
279			`fs-sim`
280
281
282
283
284			`syn:Synthesis:`
285			`Verilog`
286
287
288			`fs-sim`
289
290
291
292
293
294			`doc`
295
296
297			`spirit:library="Testbench"`
298			`spirit:name="toolflow"`
299			`spirit:version="documentation"/>`
300
301			`:Documentation:`
302			`Verilog`
303
304
305
306
307
308
309
310
311
312
313
314
315			`enable`
316			`wire`
317			`in`
318
319
320
321			`gpio_0_out`
322			`wire`
323			`out`
324			`70`
325
326
327			`gpio_0_oe`
328			`wire`
329			`out`
330			`70`
331
332
333
334
335			`gpio_0_in`
336			`wire`
337			`in`
338			`70`
339
340
341
342			`gpio_1_out`
343			`wire`
344			`out`
345			`70`
346
347
348			`gpio_1_oe`
349			`wire`
350			`out`
351			`70`
352
353
354
355			`gpio_1_in`
356			`wire`
357			`in`
358			`70`
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374			`8`
375			`mb`
376
377			`mb`
378			`0x0000`
379
380
381			`mb_microbus`
382			`0x10`
383			`8`
384
385
386
387			`gpio_0_out`
388			`0x2`
389			`8`
390			`read-write`
391
392
393
394			`gpio_0_oe`
395			`0x1`
396			`8`
397			`read-write`
398
399
400
401			`gpio_0_in`
402			`0x0`
403			`8`
404			`read-only`
405
406
407
408
409			`gpio_1_out`
410			`0x6`
411			`8`
412			`read-write`
413
414
415
416			`gpio_1_oe`
417			`0x5`
418			`8`
419			`read-write`
420
421
422
423			`gpio_1_in`
424			`0x4`
425			`8`
426			`read-only`
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443