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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def_lint
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 

 
 
 
       
 
 
              
              Dut
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 

 
 
 
 
 

 
 
 
 
   
      fs-lint
 
 
      
        
        ../verilog/lint/io_module_def_lint
        verilogSource
        module
      
 
 
   
 
 
 

 
 
 
 
 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def_lint`
41
42	133	jt_eaton
43	131	jt_eaton
44	133	jt_eaton
45			`elab_verilog`
46			`102.1`
47			`none`
48			`:Simulation:`
49			`>`
50			`./tools/verilog/elab_verilog`
51
52
53			`configuration`
54			`default`
55
56
57			`dest_dir`
58			`io_ports`
59
60
61
62	131	jt_eaton
63	133	jt_eaton
64			`gen_design`
65			`102.1`
66			`none`
67			`:Simulation:`
68			`>`
69			`./tools/verilog/gen_design`
70
71
72			`dest_dir`
73			`io_ports`
74
75
76
77
78
79
80
81	131	jt_eaton
82
83
84
85
86
87
88
89			`Dut`
90
91
92			`spirit:library="io"`
93			`spirit:name="io_module"`
94			`spirit:version="def_dut.params"/>`
95
96
97
98
99
100			`lint`
101			`:Lint:`
102			`Verilog`
103			`fs-lint`
104
105
106
107
108			`rtl_check`
109
110
111			`spirit:library="Testbench"`
112			`spirit:name="toolflow"`
113			`spirit:version="rtl_check"/>`
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132			`fs-lint`
133
134
135
136
137			`../verilog/lint/io_module_def_lint`
138			`verilogSource`
139			`module`
140
141
142
143
144
145
146
147
148
149
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_lint.xml] - Blame information for rev 133