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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def_tb
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 

    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8
    BUS_ADDR_WIDTH16

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Vga
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="vga.design"/>
              
 
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def_tb`
41
42
43
44
45
46
47			`elab_verilog`
48	133	jt_eaton	`102.1`
49	131	jt_eaton	`none`
50			`:Simulation:`
51			`./tools/verilog/elab_verilog`
52
53
54	133	jt_eaton	`configuration`
55			`default`
56	131	jt_eaton
57
58	133	jt_eaton	`dest_dir`
59			`io_ports`
60	131	jt_eaton
61
62
63
64
65
66
67
68			`gen_verilog`
69			`104.0`
70			`none`
71			`common`
72			`./tools/verilog/gen_verilog`
73
74
75	133	jt_eaton	`configuration`
76			`default`
77
78
79	131	jt_eaton	`destination`
80			`top.tb`
81
82
83			`dest_dir`
84			`../verilog`
85
86
87			`top`
88
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102			`PS2_MODEL_CLKCNT8'h7f`
103			`PS2_MODEL_SIZE8`
104			`BUS_ADDR_WIDTH16`
105
106
107
108
109
110
111			`Params`
112
113
114			`spirit:library="io"`
115			`spirit:name="io_module"`
116			`spirit:version="def_dut.params"/>`
117
118
119
120
121			`Bfm`
122
123			`spirit:library="io"`
124			`spirit:name="io_module"`
125			`spirit:version="bfm.design"/>`
126
127
128
129
130			`Vga`
131
132			`spirit:library="io"`
133			`spirit:name="io_module"`
134			`spirit:version="vga.design"/>`
135
136
137
138
139
140
141
142
143			`Ps2_bfm`
144
145
146			`spirit:library="Testbench"`
147			`spirit:name="ps2_model"`
148			`spirit:version="bfm"/>`
149
150
151
152
153
154			`icarus`
155
156
157			`spirit:library="Testbench"`
158			`spirit:name="toolflow"`
159			`spirit:version="icarus"/>`
160
161
162
163
164
165
166
167
168			`commoncommon`
169			`Verilog`
170
171
172			`fs-common`
173
174
175
176
177
178
179
180
181
182
183			`sim:Simulation:`
184			`Verilog`
185
186
187			`fs-sim`
188
189
190
191
192			`lint:Lint:`
193			`Verilog`
194
195
196			`fs-lint`
197
198
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218			`fs-common`
219
220
221
222			`../verilog/sram.load`
223			`verilogSourcefragment`
224
225
226
227
228			`../verilog/top.ext`
229			`verilogSourcefragment`
230
231
232
233
234
235
236			`fs-sim`
237
238
239
240
241			`../verilog/common/top.tb`
242			`verilogSourcemodule`
243
244
245
246
247
248
249
250			`fs-lint`
251
252
253
254
255			`../verilog/common/top.tb`
256			`verilogSourcemodule`
257
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