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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_gpio_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
gpio_tb
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top.gpio_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 

 
 
 
 


    BUS_ADDR_WIDTH16

 
 
       
 
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="gpio_dut.params"/>
 
 
 
 
             
              
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.ext.gpio
        verilogSourcefragment
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/common/top.gpio_tb
        verilogSourcemodule
      
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.gpio_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
 

 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_gpio_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`gpio_tb`
41
42
43
44
45
46	133	jt_eaton
47	131	jt_eaton
48			`elab_verilog`
49	133	jt_eaton	`102.1`
50	131	jt_eaton	`none`
51			`:Simulation:`
52			`./tools/verilog/elab_verilog`
53
54
55	133	jt_eaton	`configuration`
56			`default`
57	131	jt_eaton
58
59	133	jt_eaton	`dest_dir`
60			`io_ports`
61	131	jt_eaton
62
63
64
65
66
67	133	jt_eaton
68	131	jt_eaton
69			`gen_verilog`
70			`104.0`
71			`none`
72			`common`
73			`./tools/verilog/gen_verilog`
74
75
76	133	jt_eaton	`configuration`
77			`default`
78
79
80	131	jt_eaton	`destination`
81			`top.gpio_tb`
82
83
84			`dest_dir`
85			`../verilog`
86
87
88			`top`
89
90
91
92
93
94
95
96
97
98
99
100			`BUS_ADDR_WIDTH16`
101
102
103
104
105
106
107
108			`Params`
109
110
111			`spirit:library="io"`
112			`spirit:name="io_module"`
113			`spirit:version="gpio_dut.params"/>`
114
115
116
117
118
119
120
121
122			`Bfm`
123
124			`spirit:library="io"`
125			`spirit:name="io_module"`
126			`spirit:version="bfm.design"/>`
127
128
129
130
131			`icarus`
132
133
134			`spirit:library="Testbench"`
135			`spirit:name="toolflow"`
136			`spirit:version="icarus"/>`
137
138
139
140
141
142
143
144			`commoncommon`
145			`Verilog`
146
147
148			`fs-common`
149
150
151
152
153			`sim:Simulation:`
154			`Verilog`
155
156
157			`fs-sim`
158
159
160
161
162
163			`lint:Lint:`
164			`Verilog`
165
166
167			`fs-lint`
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-common`
188
189
190
191			`../verilog/top.ext.gpio`
192			`verilogSourcefragment`
193
194
195
196
197
198
199
200
201			`fs-sim`
202
203
204
205			`../verilog/common/top.gpio_tb`
206			`verilogSourcemodule`
207
208
209
210
211
212
213			`fs-lint`
214
215
216
217
218			`../verilog/common/top.gpio_tb`
219			`verilogSourcemodule`
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236